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Fri, 27 Jan 2023 11:41:33 +0000 From: Joey Gouly To: Andrew Jones , , CC: , Alexandru Elisei , Christoffer Dall , Fuad Tabba , Jean-Philippe Brucker , Joey Gouly , Marc Zyngier , Mark Rutland , Oliver Upton , Paolo Bonzini , Quentin Perret , Steven Price , Suzuki K Poulose , "Thomas Huth" , Will Deacon , Zenghui Yu , , , , Subject: [RFC kvm-unit-tests 04/27] arm: Make physical address mask dynamic Date: Fri, 27 Jan 2023 11:40:45 +0000 Message-ID: <20230127114108.10025-5-joey.gouly@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230127114108.10025-1-joey.gouly@arm.com> References: <20230127112248.136810-1-suzuki.poulose@arm.com> <20230127114108.10025-1-joey.gouly@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT040:EE_|PAWPR08MB10240:EE_|AM7EUR03FT028:EE_|DU0PR08MB8424:EE_ X-MS-Office365-Filtering-Correlation-Id: a5e2a941-b4af-4f92-9adf-08db005b7a84 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2023 11:41:49.9810 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5e2a941-b4af-4f92-9adf-08db005b7a84 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT028.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8424 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We are about to add Realm support where the physical address width may be k= nown via RSI. Make the Physical Address mask dynamic, so that it can be adjusted to the limit for the realm. This will be required for making pages shared, = as we introduce the "sharing" attribute as the top bit of the IPA. Signed-off-by: Joey Gouly --- lib/arm/mmu.c | 2 ++ lib/arm/setup.c | 1 + lib/arm64/asm/pgtable-hwdef.h | 6 ------ lib/arm64/asm/pgtable.h | 9 +++++++++ 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/lib/arm/mmu.c b/lib/arm/mmu.c index e1a72fe4..acaf5614 100644 --- a/lib/arm/mmu.c +++ b/lib/arm/mmu.c @@ -22,6 +22,8 @@ =20 pgd_t *mmu_idmap; =20 +unsigned long phys_mask_shift =3D 48; + /* CPU 0 starts with disabled MMU */ static cpumask_t mmu_enabled_cpumask; =20 diff --git a/lib/arm/setup.c b/lib/arm/setup.c index bcdf0d78..81052a3d 100644 --- a/lib/arm/setup.c +++ b/lib/arm/setup.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/lib/arm64/asm/pgtable-hwdef.h b/lib/arm64/asm/pgtable-hwdef.h index 8c41fe12..ac95550b 100644 --- a/lib/arm64/asm/pgtable-hwdef.h +++ b/lib/arm64/asm/pgtable-hwdef.h @@ -115,12 +115,6 @@ #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) =20 -/* - * Highest possible physical address supported. - */ -#define PHYS_MASK_SHIFT (48) -#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) - /* * TCR flags. */ diff --git a/lib/arm64/asm/pgtable.h b/lib/arm64/asm/pgtable.h index bfb8a993..22ce64f0 100644 --- a/lib/arm64/asm/pgtable.h +++ b/lib/arm64/asm/pgtable.h @@ -21,6 +21,15 @@ =20 #include =20 +extern unsigned long prot_ns_shared; +/* + * Highest possible physical address supported. + */ +extern unsigned long phys_mask_shift; +#define PHYS_MASK_SHIFT (phys_mask_shift) +#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) + + /* * We can convert va <=3D> pa page table addresses with simple casts * because we always allocate their pages with alloc_page(), and --=20 2.17.1