From nobody Wed Nov 13 07:05:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F79EC54E94 for ; Thu, 26 Jan 2023 08:53:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236580AbjAZIxy (ORCPT ); Thu, 26 Jan 2023 03:53:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236212AbjAZIxo (ORCPT ); Thu, 26 Jan 2023 03:53:44 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89C4E6C102; Thu, 26 Jan 2023 00:53:28 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 639406602DDC; Thu, 26 Jan 2023 08:53:26 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674723207; bh=O2dXAgLPaUw3PkOtSt7LNqIQn4RCHuSEGA3KmIfxgy8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Bx5H4u7z93PYNylZpG1m+FK7zwYuaSzy6BVKWNUafyPAb2G1H1/IwKmNyhHeozIqy WMMILibWPJhTJ+ZivA007Go6KnZY3gmHXf+2ncSG0FZEiH8G1x9cvInU+U8wlbQlwt 617FmTmiffzURhu3GrmgauJfbdS3pIbBD047Wl1ghLljrpz1tkIgmoiHkTMwlVzHBZ +Da2vBGTXDpulRQLwoiwkp2gz4cdSXifQ/mlPOR8uaJQSJYulLCJofm488Ro+Bj4e7 +LHaZ1+fec0Yocd2QK+HddCPlDZccGMpcLoHPhcwUq11DMBDbLy9TWQnxnMIOWKxRe 06JrHRzmEQeqg== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 1/6] clk: mediatek: fhctl: Add support for older fhctl register layout Date: Thu, 26 Jan 2023 09:53:16 +0100 Message-Id: <20230126085321.87267-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> References: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Frequency Hopping Controller (FHCTL) seems to have different versions, as it has a slightly different register layout on some older SoCs like MT6795, MT8173, MT8183 (and others). This driver is indeed compatible with at least some of those older IP revisions, so all we need to do is to add a way to select the right register layout at registration time. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-fhctl.c | 26 +++++++++++++++++--- drivers/clk/mediatek/clk-fhctl.h | 9 ++++++- drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 ++ drivers/clk/mediatek/clk-pllfh.c | 23 +++++++++++++---- drivers/clk/mediatek/clk-pllfh.h | 1 + 5 files changed, 52 insertions(+), 9 deletions(-) diff --git a/drivers/clk/mediatek/clk-fhctl.c b/drivers/clk/mediatek/clk-fh= ctl.c index 4f271acef5fe..45e4842cbf04 100644 --- a/drivers/clk/mediatek/clk-fhctl.c +++ b/drivers/clk/mediatek/clk-fhctl.c @@ -14,7 +14,20 @@ #define PERCENT_TO_DDSLMT(dds, percent_m10) \ ((((dds) * (percent_m10)) >> 5) / 100) =20 -static const struct fhctl_offset fhctl_offset =3D { +const struct fhctl_offset fhctl_offset_v1 =3D { + .offset_hp_en =3D 0x0, + .offset_clk_con =3D 0x4, + .offset_rst_con =3D 0x8, + .offset_slope0 =3D 0xc, + .offset_slope1 =3D 0x10, + .offset_cfg =3D 0x0, + .offset_updnlmt =3D 0x4, + .offset_dds =3D 0x8, + .offset_dvfs =3D 0xc, + .offset_mon =3D 0x10, +}; + +const struct fhctl_offset fhctl_offset_v2 =3D { .offset_hp_en =3D 0x0, .offset_clk_con =3D 0x8, .offset_rst_con =3D 0xc, @@ -27,9 +40,16 @@ static const struct fhctl_offset fhctl_offset =3D { .offset_mon =3D 0x10, }; =20 -const struct fhctl_offset *fhctl_get_offset_table(void) +const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v) { - return &fhctl_offset; + switch (v) { + case FHCTL_PLLFH_V1: + return &fhctl_offset_v1; + case FHCTL_PLLFH_V2: + return &fhctl_offset_v2; + default: + return ERR_PTR(-EINVAL); + }; } =20 static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs, diff --git a/drivers/clk/mediatek/clk-fhctl.h b/drivers/clk/mediatek/clk-fh= ctl.h index 51275febf086..bfa6d281a3ee 100644 --- a/drivers/clk/mediatek/clk-fhctl.h +++ b/drivers/clk/mediatek/clk-fhctl.h @@ -7,6 +7,13 @@ #ifndef __CLK_FHCTL_H #define __CLK_FHCTL_H =20 +#include "clk-pllfh.h" + +enum fhctl_variant { + FHCTL_PLLFH_V1, + FHCTL_PLLFH_V2, +}; + struct fhctl_offset { u32 offset_hp_en; u32 offset_clk_con; @@ -19,7 +26,7 @@ struct fhctl_offset { u32 offset_dvfs; u32 offset_mon; }; -const struct fhctl_offset *fhctl_get_offset_table(void); +const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v); const struct fh_operation *fhctl_get_ops(void); void fhctl_hw_init(struct mtk_fh *fh); =20 diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8186-apmixedsys.c index 1d673c6278a9..9fded5020ca4 100644 --- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c @@ -7,6 +7,7 @@ #include #include =20 +#include "clk-fhctl.h" #include "clk-mtk.h" #include "clk-pll.h" #include "clk-pllfh.h" @@ -98,6 +99,7 @@ enum fh_pll_id { .data =3D { \ .pll_id =3D _pllid, \ .fh_id =3D _fhid, \ + .fh_ver =3D FHCTL_PLLFH_V2, \ .fhx_offset =3D _offset, \ .dds_mask =3D GENMASK(21, 0), \ .slope0_value =3D 0x6003c97, \ diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pl= lfh.c index f48780bec507..b9297726f5a0 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -104,14 +104,16 @@ void fhctl_parse_dt(const u8 *compatible_node, struct= mtk_pllfh_data *pllfhs, } } =20 -static void pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_dat= a) +static int pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data) { struct fh_pll_regs *regs =3D &fh->regs; const struct fhctl_offset *offset; void __iomem *base =3D pllfh_data->state.base; void __iomem *fhx_base =3D base + pllfh_data->data.fhx_offset; =20 - offset =3D fhctl_get_offset_table(); + offset =3D fhctl_get_offset_table(pllfh_data->data.fh_ver); + if (IS_ERR(offset)) + return PTR_ERR(offset); =20 regs->reg_hp_en =3D base + offset->offset_hp_en; regs->reg_clk_con =3D base + offset->offset_clk_con; @@ -129,6 +131,8 @@ static void pllfh_init(struct mtk_fh *fh, struct mtk_pl= lfh_data *pllfh_data) fh->lock =3D &pllfh_lock; =20 fh->ops =3D fhctl_get_ops(); + + return 0; } =20 static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pl= lfh) @@ -142,20 +146,29 @@ mtk_clk_register_pllfh(const struct mtk_pll_data *pll= _data, { struct clk_hw *hw; struct mtk_fh *fh; + int ret; =20 fh =3D kzalloc(sizeof(*fh), GFP_KERNEL); if (!fh) return ERR_PTR(-ENOMEM); =20 - pllfh_init(fh, pllfh_data); + ret =3D pllfh_init(fh, pllfh_data); + if (ret) { + hw =3D ERR_PTR(ret); + goto out; + } =20 hw =3D mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, &mtk_pllfh_ops); =20 + if (IS_ERR(hw)) + goto out; + + fhctl_hw_init(fh); + +out: if (IS_ERR(hw)) kfree(fh); - else - fhctl_hw_init(fh); =20 return hw; } diff --git a/drivers/clk/mediatek/clk-pllfh.h b/drivers/clk/mediatek/clk-pl= lfh.h index c0a6e1537034..5f419c2ec01f 100644 --- a/drivers/clk/mediatek/clk-pllfh.h +++ b/drivers/clk/mediatek/clk-pllfh.h @@ -18,6 +18,7 @@ struct fh_pll_state { struct fh_pll_data { int pll_id; int fh_id; + int fh_ver; u32 fhx_offset; u32 dds_mask; u32 slope0_value; --=20 2.39.0 From nobody Wed Nov 13 07:05:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AB30C54E94 for ; Thu, 26 Jan 2023 08:53:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236549AbjAZIxs (ORCPT ); Thu, 26 Jan 2023 03:53:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233264AbjAZIxn (ORCPT ); Thu, 26 Jan 2023 03:53:43 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB2A66C103; Thu, 26 Jan 2023 00:53:29 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 8698E6602E6E; Thu, 26 Jan 2023 08:53:27 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674723208; bh=3eFP3ouO4RR+WchS8C8yL39f+/y+XVsgL/MqIts3FDc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hCd7auwGfsAqGbzLGINNtMthJ6Z4LLNiYQUBVw5/z4rQ9IXdMy9gZ4cArpmR06ZHh LB+RhJGMCpIzSsbwnSBQVr5PHNn4D2CDxz5Exg45Z52LzLYOJF55/BO9RU38bJ8N1o Qjy+yuYIIJDR75/8dLwBqTKkOnjdCgJWSktwSLzZKg0qwiBV4Gtb+xGoj/uNjmTi65 IqekUOBH0pA9Bqd2SFqXKQIfwZVRRcGGcgJ9QxvRRLA+D166FlDxyLKmTA1ZqhXuea /lxa+rvPaEMCU7EkBGBF7bppkoUT2UW3XDJfsKRagtPTtY/VtsxUdNiHFyxEj1/vFp JxV2R5kvkfsWA== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 2/6] dt-bindings: clock: mediatek,mt8186-fhctl: Support MT6795, MT8173/92/95 Date: Thu, 26 Jan 2023 09:53:17 +0100 Message-Id: <20230126085321.87267-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> References: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" MT6795, MT8173, MT8192 and MT8195 support Frequency Hopping: add the compatibles for them. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml index cfd042ac1e14..d00327d12e1e 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml @@ -16,7 +16,12 @@ description: | =20 properties: compatible: - const: mediatek,mt8186-fhctl + enum: + - mediatek,mt6795-fhctl + - mediatek,mt8173-fhctl + - mediatek,mt8186-fhctl + - mediatek,mt8192-fhctl + - mediatek,mt8195-fhctl =20 reg: maxItems: 1 --=20 2.39.0 From nobody Wed Nov 13 07:05:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3207C54E94 for ; Thu, 26 Jan 2023 08:53:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236553AbjAZIxv (ORCPT ); Thu, 26 Jan 2023 03:53:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236503AbjAZIxo (ORCPT ); Thu, 26 Jan 2023 03:53:44 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C251B6C106; Thu, 26 Jan 2023 00:53:30 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A56366602E72; Thu, 26 Jan 2023 08:53:28 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674723209; bh=hsRKdUlhnDLJbGIwsqwoaTUXgSw/PcP7XnAaJTpL7Eg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CuYI151MO1smp+eUtdrdF+nRp1BgPGBInO/mTfF/DmSHItqMT2y4aE0rL1D3sYfJG C6duC1UFYYOAhc1/NISGJvU5Z1fLLINOQUihZZ3jbHNW8dxibqbYtwpR5xdhRn1yLY M9BCZeimmD3bRG/EvTlYsRSfNNg17TMWRonSjUMtvsyYczvuSRllfjNh3mup7yUKcz k8mJseD8CMZIPD1lwwNHvVH3dkRoJxC/rmDmUKZu3P8E7aL46vTAAvzHKGBt6iFUBq Ifr7kDX/daaXVuPK6rZbQPkIzZHlskS0NKlzslOd9N1qI8sFycOPRWlWNgt7ccVZPy Up6xXLxn2XTlQ== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 3/6] clk: mediatek: mt6795: Add support for frequency hopping through FHCTL Date: Thu, 26 Jan 2023 09:53:18 +0100 Message-Id: <20230126085321.87267-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> References: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add FHCTL parameters and register PLLs through FHCTL to add support for frequency hopping and SSC. FHCTL will be enabled only on PLLs specified in devicetree. This commit brings functional changes only upon addition of devicetree configuration. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 63 +++++++++++++++++++- 1 file changed, 60 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/med= iatek/clk-mt6795-apmixedsys.c index 59761c72d3bc..03fa30527868 100644 --- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c @@ -7,8 +7,10 @@ #include #include #include +#include "clk-fhctl.h" #include "clk-mtk.h" #include "clk-pll.h" +#include "clk-pllfh.h" =20 #define REG_REF2USB 0x8 #define REG_AP_PLL_CON7 0x1c @@ -58,6 +60,56 @@ static const struct mtk_pll_data plls[] =3D { PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2bc, = 0x2b8, 0), }; =20 +enum fh_pll_id { + FH_CA53PLL_LL, + FH_CA53PLL_BL, + FH_MAINPLL, + FH_MPLL, + FH_MSDCPLL, + FH_MMPLL, + FH_VENCPLL, + FH_TVDPLL, + FH_VCODECPLL, + FH_NR_FH, +}; + +#define _FH(_pllid, _fhid, _slope, _offset) { \ + .data =3D { \ + .pll_id =3D _pllid, \ + .fh_id =3D _fhid, \ + .fh_ver =3D FHCTL_PLLFH_V1, \ + .fhx_offset =3D _offset, \ + .dds_mask =3D GENMASK(21, 0), \ + .slope0_value =3D _slope, \ + .slope1_value =3D _slope, \ + .sfstrx_en =3D BIT(2), \ + .frddsx_en =3D BIT(1), \ + .fhctlx_en =3D BIT(0), \ + .tgl_org =3D BIT(31), \ + .dvfs_tri =3D BIT(31), \ + .pcwchg =3D BIT(31), \ + .dt_val =3D 0x0, \ + .df_val =3D 0x9, \ + .updnlmt_shft =3D 16, \ + .msk_frddsx_dys =3D GENMASK(23, 20), \ + .msk_frddsx_dts =3D GENMASK(19, 16), \ + }, \ + } + +#define FH(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6003c97, _offset) +#define FH_M(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6000140, _offset) + +static struct mtk_pllfh_data pllfhs[] =3D { + FH(CLK_APMIXED_ARMCA53PLL, FH_CA53PLL_BL, 0x38), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60), + FH_M(CLK_APMIXED_MPLL, FH_MPLL, 0x74), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c), + FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0), + FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4), + FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8), +}; + static void clk_mt6795_apmixed_setup_md1(void __iomem *base) { void __iomem *reg =3D base + REG_AP_PLL_CON7; @@ -85,6 +137,7 @@ static int clk_mt6795_apmixed_probe(struct platform_devi= ce *pdev) struct clk_hw_onecell_data *clk_data; struct device *dev =3D &pdev->dev; struct device_node *node =3D dev->of_node; + const u8 *fhctl_node =3D "mediatek,mt6795-fhctl"; void __iomem *base; struct clk_hw *hw; int ret; @@ -97,7 +150,9 @@ static int clk_mt6795_apmixed_probe(struct platform_devi= ce *pdev) if (!clk_data) return -ENOMEM; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + ret =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (ret) goto free_clk_data; =20 @@ -124,7 +179,8 @@ static int clk_mt6795_apmixed_probe(struct platform_dev= ice *pdev) unregister_ref2usb: mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_clk_data: mtk_free_clk_data(clk_data); return ret; @@ -137,7 +193,8 @@ static int clk_mt6795_apmixed_remove(struct platform_de= vice *pdev) =20 of_clk_del_provider(node); mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); mtk_free_clk_data(clk_data); =20 return 0; --=20 2.39.0 From nobody Wed Nov 13 07:05:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 332BBC54E94 for ; Thu, 26 Jan 2023 08:53:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236600AbjAZIx4 (ORCPT ); Thu, 26 Jan 2023 03:53:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236507AbjAZIxo (ORCPT ); Thu, 26 Jan 2023 03:53:44 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5D7D6C101; Thu, 26 Jan 2023 00:53:31 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id CAC236602E91; Thu, 26 Jan 2023 08:53:29 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674723210; bh=e4X/ACfo4PczeBKqlI21xK5AuMzs072mhIO7l0YAHu0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gk+kydM9To+4Df2DPOVExYsAasKiw8/q/oRMhY306Tym2cyeLTs/+j01/8iT0BjdR 7o4xJpY22EeFDPUzkYzmL9c40OcF19AGCEUS3K0oVWY8yZiQHEJbxfUr+0ZCKqkSfl UgljbrT9mfxUuCjufq7HKUwUswfZN34UDDQJqXsh2ykl9t3PhF4tKBDcAuPRcpQ65N ezuETw3D+lC32jffnMkKmR2kgbMbNBD/7wEFHwWeZSymWU7sHqnhJyQM+PJGhJaKx7 r+dP3s//bMNJS+QnPvmyr8RZxCqVr7Ptsn6UeKvGdrKAZt7UGMWBooQVvm9A1h92d1 tcMjHJuEWTKoA== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 4/6] clk: mediatek: mt8173: Add support for frequency hopping through FHCTL Date: Thu, 26 Jan 2023 09:53:19 +0100 Message-Id: <20230126085321.87267-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> References: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add FHCTL parameters and register PLLs through FHCTL to add support for frequency hopping and SSC. FHCTL will be enabled only on PLLs specified in devicetree. This commit brings functional changes only upon addition of devicetree configuration. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 65 +++++++++++++++++++- 1 file changed, 62 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8173-apmixedsys.c index a56c5845d07a..0084203e67ad 100644 --- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c @@ -9,8 +9,10 @@ #include #include #include +#include "clk-fhctl.h" #include "clk-mtk.h" #include "clk-pll.h" +#include "clk-pllfh.h" =20 #define REGOFF_REF2USB 0x8 #define REGOFF_HDMI_REF 0x40 @@ -77,6 +79,58 @@ static const struct mtk_pll_data plls[] =3D { PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0= x0, 0x2f4, 0), }; =20 +enum fh_pll_id { + FH_ARMCA7PLL, + FH_ARMCA15PLL, + FH_MAINPLL, + FH_MPLL, + FH_MSDCPLL, + FH_MMPLL, + FH_VENCPLL, + FH_TVDPLL, + FH_VCODECPLL, + FH_LVDSPLL, + FH_MSDC2PLL, + FH_NR_FH, +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data =3D { \ + .pll_id =3D _pllid, \ + .fh_id =3D _fhid, \ + .fh_ver =3D FHCTL_PLLFH_V1, \ + .fhx_offset =3D _offset, \ + .dds_mask =3D GENMASK(21, 0), \ + .slope0_value =3D 0x6003c97, \ + .slope1_value =3D 0x6003c97, \ + .sfstrx_en =3D BIT(2), \ + .frddsx_en =3D BIT(1), \ + .fhctlx_en =3D BIT(0), \ + .tgl_org =3D BIT(31), \ + .dvfs_tri =3D BIT(31), \ + .pcwchg =3D BIT(31), \ + .dt_val =3D 0x0, \ + .df_val =3D 0x9, \ + .updnlmt_shft =3D 16, \ + .msk_frddsx_dys =3D GENMASK(23, 20), \ + .msk_frddsx_dts =3D GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] =3D { + FH(CLK_APMIXED_ARMCA7PLL, FH_ARMCA7PLL, 0x38), + FH(CLK_APMIXED_ARMCA15PLL, FH_ARMCA15PLL, 0x4c), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60), + FH(CLK_APMIXED_MPLL, FH_MPLL, 0x74), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c), + FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0), + FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4), + FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8), + FH(CLK_APMIXED_LVDSPLL, FH_LVDSPLL, 0xec), + FH(CLK_APMIXED_MSDCPLL2, FH_MSDC2PLL, 0x100), +}; + static const struct of_device_id of_match_clk_mt8173_apmixed[] =3D { { .compatible =3D "mediatek,mt8173-apmixedsys" }, { /* sentinel */ } @@ -84,6 +138,7 @@ static const struct of_device_id of_match_clk_mt8173_apm= ixed[] =3D { =20 static int clk_mt8173_apmixed_probe(struct platform_device *pdev) { + const u8 *fhctl_node =3D "mediatek,mt8173-fhctl"; struct device_node *node =3D pdev->dev.of_node; struct clk_hw_onecell_data *clk_data; void __iomem *base; @@ -98,7 +153,9 @@ static int clk_mt8173_apmixed_probe(struct platform_devi= ce *pdev) if (IS_ERR_OR_NULL(clk_data)) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + r =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_clk_data; =20 @@ -124,7 +181,8 @@ static int clk_mt8173_apmixed_probe(struct platform_dev= ice *pdev) unregister_ref2usb: mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_clk_data: mtk_free_clk_data(clk_data); return r; @@ -137,7 +195,8 @@ static int clk_mt8173_apmixed_remove(struct platform_de= vice *pdev) =20 of_clk_del_provider(node); mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); mtk_free_clk_data(clk_data); =20 return 0; --=20 2.39.0 From nobody Wed Nov 13 07:05:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BC10C61DA0 for ; Thu, 26 Jan 2023 08:54:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236611AbjAZIyA (ORCPT ); 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tv34dzq8/zvQ56rn+b98dM0W2HBHbbfENlA/yBM/c27HTXvKFKJROC1HKERVK8OAY 2ugvW8zPmlxB5KM9iOJXjetrnUPpP+ZDIWWHDByOl3owirn4X8KooRmOAyKS5XVWzp R2zrW5lDFe/7ay/o48jV6qUe+RhzApriqZR9EsNs+FHEKr/p+FTL1kNvMqMfzY8Cni RHyN3VzmxjNpCYXhKXVVahrppctr5XcHrS7IAPryA0HDz0hrhFEisRQa1gOU2AMb0x iLYKIU/hEyi5jvdzWdosdJJFGFywu7vpeXgHTz72lqRDf/oDgiheNhbLgxbeeo2+4O 8QHdRvQ1Usyng== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 5/6] clk: mediatek: mt8192: Add support for frequency hopping through FHCTL Date: Thu, 26 Jan 2023 09:53:20 +0100 Message-Id: <20230126085321.87267-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> References: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add FHCTL parameters and register PLLs through FHCTL to add support for frequency hopping and SSC. FHCTL will be enabled only on PLLs specified in devicetree. This commit brings functional changes only upon addition of devicetree configuration. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8192.c | 67 ++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index 61299960d28a..0f9f10172148 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -12,10 +12,12 @@ #include #include =20 +#include "clk-fhctl.h" #include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" #include "clk-pll.h" +#include "clk-pllfh.h" =20 #include #include @@ -1042,6 +1044,57 @@ static const struct mtk_pll_data plls[] =3D { 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), }; =20 +enum fh_pll_id { + FH_ARMPLL_LL, + FH_ARMPLL_BL0, + FH_ARMPLL_BL1, + FH_ARMPLL_BL2, + FH_ARMPLL_BL3, + FH_CCIPLL, + FH_MFGPLL, + FH_MEMPLL, + FH_MPLL, + FH_MMPLL, + FH_MAINPLL, + FH_MSDCPLL, + FH_ADSPPLL, + FH_APUPLL, + FH_TVDPLL, + FH_NR_FH, +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data =3D { \ + .pll_id =3D _pllid, \ + .fh_id =3D _fhid, \ + .fh_ver =3D FHCTL_PLLFH_V2, \ + .fhx_offset =3D _offset, \ + .dds_mask =3D GENMASK(21, 0), \ + .slope0_value =3D 0x6003c97, \ + .slope1_value =3D 0x6003c97, \ + .sfstrx_en =3D BIT(2), \ + .frddsx_en =3D BIT(1), \ + .fhctlx_en =3D BIT(0), \ + .tgl_org =3D BIT(31), \ + .dvfs_tri =3D BIT(31), \ + .pcwchg =3D BIT(31), \ + .dt_val =3D 0x0, \ + .df_val =3D 0x9, \ + .updnlmt_shft =3D 16, \ + .msk_frddsx_dys =3D GENMASK(23, 20), \ + .msk_frddsx_dts =3D GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] =3D { + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118), + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x12c), + FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154), +}; + /* Register mux notifier for MFG mux */ static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk = *clk) { @@ -1068,17 +1121,24 @@ static int clk_mt8192_apmixed_probe(struct platform= _device *pdev) { struct clk_hw_onecell_data *clk_data; struct device_node *node =3D pdev->dev.of_node; + const u8 *fhctl_node =3D "mediatek,mt8192-fhctl"; int r; =20 clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + + r =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); + if (r) + goto free_clk_data; + r =3D mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); if (r) - goto free_clk_data; + goto unregister_plls; =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -1088,6 +1148,9 @@ static int clk_mt8192_apmixed_probe(struct platform_d= evice *pdev) =20 unregister_gates: mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); +unregister_plls: + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_clk_data: mtk_free_clk_data(clk_data); return r; --=20 2.39.0 From nobody Wed Nov 13 07:05:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 661F3C54EED for ; Thu, 26 Jan 2023 08:54:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236606AbjAZIx6 (ORCPT ); Thu, 26 Jan 2023 03:53:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236552AbjAZIxs (ORCPT ); Thu, 26 Jan 2023 03:53:48 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAED139CE2; Thu, 26 Jan 2023 00:53:43 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0C48F6602E8A; Thu, 26 Jan 2023 08:53:32 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674723213; bh=pKMGoeKu4m5DJFVWyByEtDagZ1PUSFRsRa3TlZzOsdw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nJ7Dp18rXaD2PV9bjGm7alMnY0xRZiSN3N9p5TcIvxR5VTV6i/O0VR+aW99bNveuH rTOTug+CjPQAiqqtDJnpikOkJhiCASTHZQhE8ag9xqZG7HiicGlxXwsmC3lPov0GGl Xtg9SRAFsWqIEL6k489ZSK0lyk4a59UNiUUK2eeVz4THuLbt59UMsGeHFkQxJKJvKY EDsHuPUxrxA3OKTERdnc9iVpJXPN15DG8KD2sh9347lNgShJeiAez4AxXnZZ7UHC39 3NQPW93pbcQnloqQ7M1jgxqy7TaNABbCDWN93ke7i707wJK89rUp0DzU7YEgiuu/jg E4NW9pyHuFVGg== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 6/6] clk: mediatek: mt8195: Add support for frequency hopping through FHCTL Date: Thu, 26 Jan 2023 09:53:21 +0100 Message-Id: <20230126085321.87267-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> References: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add FHCTL parameters and register PLLs through FHCTL to add support for frequency hopping and SSC. FHCTL will be enabled only on PLLs specified in devicetree. This commit brings functional changes only upon addition of devicetree configuration. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 69 +++++++++++++++++++- 1 file changed, 66 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8195-apmixedsys.c index 1bc917f2667e..c0db31ce0741 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -3,9 +3,11 @@ // Copyright (c) 2021 MediaTek Inc. // Author: Chun-Jie Chen =20 +#include "clk-fhctl.h" #include "clk-gate.h" #include "clk-mtk.h" #include "clk-pll.h" +#include "clk-pllfh.h" =20 #include #include @@ -105,6 +107,61 @@ static const struct mtk_pll_data plls[] =3D { 0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9), }; =20 +enum fh_pll_id { + FH_ARMPLL_LL, + FH_ARMPLL_BL, + FH_MEMPLL, + FH_ADSPPLL, + FH_NNAPLL, + FH_CCIPLL, + FH_MFGPLL, + FH_TVDPLL2, + FH_MPLL, + FH_MMPLL, + FH_MAINPLL, + FH_MSDCPLL, + FH_IMGPLL, + FH_VDECPLL, + FH_TVDPLL1, + FH_NR_FH, +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data =3D { \ + .pll_id =3D _pllid, \ + .fh_id =3D _fhid, \ + .fh_ver =3D FHCTL_PLLFH_V2, \ + .fhx_offset =3D _offset, \ + .dds_mask =3D GENMASK(21, 0), \ + .slope0_value =3D 0x6003c97, \ + .slope1_value =3D 0x6003c97, \ + .sfstrx_en =3D BIT(2), \ + .frddsx_en =3D BIT(1), \ + .fhctlx_en =3D BIT(0), \ + .tgl_org =3D BIT(31), \ + .dvfs_tri =3D BIT(31), \ + .pcwchg =3D BIT(31), \ + .dt_val =3D 0x0, \ + .df_val =3D 0x9, \ + .updnlmt_shft =3D 16, \ + .msk_frddsx_dys =3D GENMASK(23, 20), \ + .msk_frddsx_dts =3D GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] =3D { + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x78), + FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x8c), + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4), + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL2, 0xc8), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118), + FH(CLK_APMIXED_IMGPLL, FH_IMGPLL, 0x12c), + FH(CLK_APMIXED_VDECPLL, FH_VDECPLL, 0x140), + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154), +}; + static const struct of_device_id of_match_clk_mt8195_apmixed[] =3D { { .compatible =3D "mediatek,mt8195-apmixedsys", }, {} @@ -114,13 +171,17 @@ static int clk_mt8195_apmixed_probe(struct platform_d= evice *pdev) { struct clk_hw_onecell_data *clk_data; struct device_node *node =3D pdev->dev.of_node; + const u8 *fhctl_node =3D "mediatek,mt8195-fhctl"; int r; =20 clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + + r =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_apmixed_data; =20 @@ -140,7 +201,8 @@ static int clk_mt8195_apmixed_probe(struct platform_dev= ice *pdev) unregister_gates: mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_apmixed_data: mtk_free_clk_data(clk_data); return r; @@ -153,7 +215,8 @@ static int clk_mt8195_apmixed_remove(struct platform_de= vice *pdev) =20 of_clk_del_provider(node); mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); mtk_free_clk_data(clk_data); =20 return 0; --=20 2.39.0