From nobody Sun Sep 14 05:38:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE2A2C54E94 for ; Thu, 26 Jan 2023 06:34:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236038AbjAZGe3 (ORCPT ); Thu, 26 Jan 2023 01:34:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235602AbjAZGeZ (ORCPT ); Thu, 26 Jan 2023 01:34:25 -0500 Received: from wout3-smtp.messagingengine.com (wout3-smtp.messagingengine.com [64.147.123.19]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A1814A239; Wed, 25 Jan 2023 22:34:24 -0800 (PST) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id C629B3200A55; Thu, 26 Jan 2023 01:34:22 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Thu, 26 Jan 2023 01:34:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; t=1674714862; x=1674801262; bh=/7 vsQYAZ7pK41UhsKZMQw8k1y0lXknyA0ndIUdSSThU=; b=YRdE1aYjlmPbAzQKcw 5XOLVCKMfzQbClQZxL9hbHJx7wCKNed1PQM5O69JtGFVRC5vrCb08p6umTk7CW4n 7AEFSHUthPIRwlrnGdg8HSxTJlbLQnUYPcsbp2gra8m3wcMRG3X67pRHnR2AALgs TA9UAlHJ0yKv55Wj+8zAQCnDjk6GzzQShesqMZfab0IN1Ruc+yfjFowh8QvCaPzu lIhKMzyzuTuyT7PbDXqqcrq/Zw9jB6cOSNVV5qAIHF+bmdHXV2VhIke3+Rlc/zdG OAN18iT0cM9i6rbHa6maVTQgM+WcMBDryUtT76tqiRGGOJ+dJZg4Mvw5vLV5AYz3 e2fA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; t=1674714862; x=1674801262; bh=/7vsQYAZ7pK41 UhsKZMQw8k1y0lXknyA0ndIUdSSThU=; b=XTqE0yaDz+fq9y/ph43kOJaeOQtFd Z3OyJ96m7AsMrA27OhXj+DDE1G3F0yhJbBPUUICDdg5O7lC/RWbj809ngbqA5uzO fVGUIKREaXfySaR2VdNVqEbtqR/HaaW1B5cB89w11Rw7EnUHtCx4qPx7Zb7bMs5M MfjXIYbdI9f8SrcFDFWx8dAw4O8vZjLgOcEqUs80dE3xHhUvNatd81WoG9hfAkZL qLscCDkiKLUV+6sekHsyTJpPCFQKVmlURQRajByBtD/JSZgcUOmj3XAjy0v4IMEP 4+eF0lkGgvedEcA3U2moFFbryxCrDTnnIAIkKvduYeI6Gsrl8Q9rsQt2g== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedruddvfedgleehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepgffhvefhgfehjeehgfekheeuffegheffjeegheeuudeufeffhffh ueeihfeufffhnecuffhomhgrihhnpeguvghvihgtvghtrhgvvgdrohhrghenucevlhhush htvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehsrghmuhgvlhesshhh ohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Thu, 26 Jan 2023 01:34:21 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Krzysztof Kozlowski , Samuel Holland , Andre Przywara , Conor Dooley , Heiko Stuebner , Palmer Dabbelt , Philipp Zabel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev, Krzysztof Kozlowski Subject: [PATCH v2 1/3] dt-bindings: power: Add Allwinner D1 PPU Date: Thu, 26 Jan 2023 00:34:17 -0600 Message-Id: <20230126063419.15971-2-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126063419.15971-1-samuel@sholland.org> References: <20230126063419.15971-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Allwinner D1 family of SoCs contain a PPU power domain controller separate from the PRCM. It can power down the video engine and DSP, and it contains special logic for hardware-assisted CPU idle. Other recent Allwinner SoCs (e.g. TV303) have a PPU with a different set of domains. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Samuel Holland --- Changes in v2: - Removed quotes from "PPU" - Fixed indentation in binding example .../power/allwinner,sun20i-d1-ppu.yaml | 54 +++++++++++++++++++ .../power/allwinner,sun20i-d1-ppu.h | 10 ++++ 2 files changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/allwinner,sun20= i-d1-ppu.yaml create mode 100644 include/dt-bindings/power/allwinner,sun20i-d1-ppu.h diff --git a/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-pp= u.yaml b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.ya= ml new file mode 100644 index 000000000000..46e2647a5d72 --- /dev/null +++ b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/allwinner,sun20i-d1-ppu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner SoCs PPU power domain controller + +maintainers: + - Samuel Holland + +description: + D1 and related SoCs contain a power domain controller for the CPUs, GPU,= and + video-related hardware. + +properties: + compatible: + enum: + - allwinner,sun20i-d1-ppu + + reg: + maxItems: 1 + + clocks: + description: Bus Clock + maxItems: 1 + + resets: + maxItems: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - resets + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + ppu: power-controller@7001000 { + compatible =3D "allwinner,sun20i-d1-ppu"; + reg =3D <0x7001000 0x1000>; + clocks =3D <&r_ccu CLK_BUS_R_PPU>; + resets =3D <&r_ccu RST_BUS_R_PPU>; + #power-domain-cells =3D <1>; + }; diff --git a/include/dt-bindings/power/allwinner,sun20i-d1-ppu.h b/include/= dt-bindings/power/allwinner,sun20i-d1-ppu.h new file mode 100644 index 000000000000..23cfb57256d6 --- /dev/null +++ b/include/dt-bindings/power/allwinner,sun20i-d1-ppu.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_ +#define _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_ + +#define PD_CPU 0 +#define PD_VE 1 +#define PD_DSP 2 + +#endif /* _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_ */ --=20 2.37.4 From nobody Sun Sep 14 05:38:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 353ACC05027 for ; Thu, 26 Jan 2023 06:34:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236184AbjAZGeg (ORCPT ); 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Thu, 26 Jan 2023 01:34:24 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Krzysztof Kozlowski , Samuel Holland , Andre Przywara , Conor Dooley , Heiko Stuebner , Palmer Dabbelt , Philipp Zabel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH v2 2/3] soc: sunxi: Add Allwinner D1 PPU driver Date: Thu, 26 Jan 2023 00:34:18 -0600 Message-Id: <20230126063419.15971-3-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126063419.15971-1-samuel@sholland.org> References: <20230126063419.15971-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The PPU contains a series of identical MMIO register ranges, one for each power domain. Each range contains control/status bits for a clock gate, reset line, output gates, and a power switch. (The clock and reset are separate from, and in addition to, the bits in the CCU.) It also contains a hardware power sequence engine to control the other bits. Acked-by: Jernej Skrabec Signed-off-by: Samuel Holland --- Changes in v2: - Removed possibly misleading comment from the Kconfig description drivers/soc/sunxi/Kconfig | 8 ++ drivers/soc/sunxi/Makefile | 1 + drivers/soc/sunxi/sun20i-ppu.c | 207 +++++++++++++++++++++++++++++++++ 3 files changed, 216 insertions(+) create mode 100644 drivers/soc/sunxi/sun20i-ppu.c diff --git a/drivers/soc/sunxi/Kconfig b/drivers/soc/sunxi/Kconfig index 8aecbc9b1976..29e9ba2d520d 100644 --- a/drivers/soc/sunxi/Kconfig +++ b/drivers/soc/sunxi/Kconfig @@ -19,3 +19,11 @@ config SUNXI_SRAM Say y here to enable the SRAM controller support. This device is responsible on mapping the SRAM in the sunXi SoCs whether to the CPU/DMA, or to the devices. + +config SUN20I_PPU + bool "Allwinner D1 PPU power domain driver" + depends on ARCH_SUNXI || COMPILE_TEST + select PM_GENERIC_DOMAINS + help + Say y to enable the PPU power domain driver. This saves power + when certain peripherals, such as the video engine, are idle. diff --git a/drivers/soc/sunxi/Makefile b/drivers/soc/sunxi/Makefile index 549159571d4f..90ff2ebe7655 100644 --- a/drivers/soc/sunxi/Makefile +++ b/drivers/soc/sunxi/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_SUNXI_MBUS) +=3D sunxi_mbus.o obj-$(CONFIG_SUNXI_SRAM) +=3D sunxi_sram.o +obj-$(CONFIG_SUN20I_PPU) +=3D sun20i-ppu.o diff --git a/drivers/soc/sunxi/sun20i-ppu.c b/drivers/soc/sunxi/sun20i-ppu.c new file mode 100644 index 000000000000..98cb41d36560 --- /dev/null +++ b/drivers/soc/sunxi/sun20i-ppu.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PD_STATE_ON 1 +#define PD_STATE_OFF 2 + +#define PD_RSTN_REG 0x00 +#define PD_CLK_GATE_REG 0x04 +#define PD_PWROFF_GATE_REG 0x08 +#define PD_PSW_ON_REG 0x0c +#define PD_PSW_OFF_REG 0x10 +#define PD_PSW_DELAY_REG 0x14 +#define PD_OFF_DELAY_REG 0x18 +#define PD_ON_DELAY_REG 0x1c +#define PD_COMMAND_REG 0x20 +#define PD_STATUS_REG 0x24 +#define PD_STATUS_COMPLETE BIT(1) +#define PD_STATUS_BUSY BIT(3) +#define PD_STATUS_STATE GENMASK(17, 16) +#define PD_ACTIVE_CTRL_REG 0x2c +#define PD_GATE_STATUS_REG 0x30 +#define PD_RSTN_STATUS BIT(0) +#define PD_CLK_GATE_STATUS BIT(1) +#define PD_PWROFF_GATE_STATUS BIT(2) +#define PD_PSW_STATUS_REG 0x34 + +#define PD_REGS_SIZE 0x80 + +struct sun20i_ppu_desc { + const char *const *names; + unsigned int num_domains; +}; + +struct sun20i_ppu_pd { + struct generic_pm_domain genpd; + void __iomem *base; +}; + +#define to_sun20i_ppu_pd(_genpd) \ + container_of(_genpd, struct sun20i_ppu_pd, genpd) + +static bool sun20i_ppu_pd_is_on(const struct sun20i_ppu_pd *pd) +{ + u32 status =3D readl(pd->base + PD_STATUS_REG); + + return FIELD_GET(PD_STATUS_STATE, status) =3D=3D PD_STATE_ON; +} + +static int sun20i_ppu_pd_set_power(const struct sun20i_ppu_pd *pd, bool po= wer_on) +{ + u32 state, status; + int ret; + + if (sun20i_ppu_pd_is_on(pd) =3D=3D power_on) + return 0; + + /* Wait for the power controller to be idle. */ + ret =3D readl_poll_timeout(pd->base + PD_STATUS_REG, status, + !(status & PD_STATUS_BUSY), 100, 1000); + if (ret) + return ret; + + state =3D power_on ? PD_STATE_ON : PD_STATE_OFF; + writel(state, pd->base + PD_COMMAND_REG); + + /* Wait for the state transition to complete. */ + ret =3D readl_poll_timeout(pd->base + PD_STATUS_REG, status, + FIELD_GET(PD_STATUS_STATE, status) =3D=3D state && + (status & PD_STATUS_COMPLETE), 100, 1000); + if (ret) + return ret; + + /* Clear the completion flag. */ + writel(status, pd->base + PD_STATUS_REG); + + return 0; +} + +static int sun20i_ppu_pd_power_on(struct generic_pm_domain *genpd) +{ + const struct sun20i_ppu_pd *pd =3D to_sun20i_ppu_pd(genpd); + + return sun20i_ppu_pd_set_power(pd, true); +} + +static int sun20i_ppu_pd_power_off(struct generic_pm_domain *genpd) +{ + const struct sun20i_ppu_pd *pd =3D to_sun20i_ppu_pd(genpd); + + return sun20i_ppu_pd_set_power(pd, false); +} + +static int sun20i_ppu_probe(struct platform_device *pdev) +{ + const struct sun20i_ppu_desc *desc; + struct device *dev =3D &pdev->dev; + struct genpd_onecell_data *ppu; + struct sun20i_ppu_pd *pds; + struct reset_control *rst; + void __iomem *base; + struct clk *clk; + int ret; + + desc =3D of_device_get_match_data(dev); + if (!desc) + return -EINVAL; + + pds =3D devm_kcalloc(dev, desc->num_domains, sizeof(*pds), GFP_KERNEL); + if (!pds) + return -ENOMEM; + + ppu =3D devm_kzalloc(dev, sizeof(*ppu), GFP_KERNEL); + if (!ppu) + return -ENOMEM; + + ppu->domains =3D devm_kcalloc(dev, desc->num_domains, + sizeof(*ppu->domains), GFP_KERNEL); + if (!ppu->domains) + return -ENOMEM; + + ppu->num_domains =3D desc->num_domains; + platform_set_drvdata(pdev, ppu); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + rst =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(rst)) + return PTR_ERR(rst); + + ret =3D reset_control_deassert(rst); + if (ret) + return ret; + + for (unsigned int i =3D 0; i < ppu->num_domains; ++i) { + struct sun20i_ppu_pd *pd =3D &pds[i]; + + pd->genpd.name =3D desc->names[i]; + pd->genpd.power_off =3D sun20i_ppu_pd_power_off; + pd->genpd.power_on =3D sun20i_ppu_pd_power_on; + pd->base =3D base + PD_REGS_SIZE * i; + + ret =3D pm_genpd_init(&pd->genpd, NULL, sun20i_ppu_pd_is_on(pd)); + if (ret) { + dev_warn(dev, "Failed to add '%s' domain: %d\n", + pd->genpd.name, ret); + continue; + } + + ppu->domains[i] =3D &pd->genpd; + } + + ret =3D of_genpd_add_provider_onecell(dev->of_node, ppu); + if (ret) + dev_warn(dev, "Failed to add provider: %d\n", ret); + + return 0; +} + +static const char *const sun20i_d1_ppu_pd_names[] =3D { + "CPU", + "VE", + "DSP", +}; + +static const struct sun20i_ppu_desc sun20i_d1_ppu_desc =3D { + .names =3D sun20i_d1_ppu_pd_names, + .num_domains =3D ARRAY_SIZE(sun20i_d1_ppu_pd_names), +}; + +static const struct of_device_id sun20i_ppu_of_match[] =3D { + { + .compatible =3D "allwinner,sun20i-d1-ppu", + .data =3D &sun20i_d1_ppu_desc, + }, + { } +}; +MODULE_DEVICE_TABLE(of, sun20i_ppu_of_match); + +static struct platform_driver sun20i_ppu_driver =3D { + .probe =3D sun20i_ppu_probe, + .driver =3D { + .name =3D "sun20i-ppu", + .of_match_table =3D sun20i_ppu_of_match, + /* Power domains cannot be removed while they are in use. */ + .suppress_bind_attrs =3D true, + }, +}; +module_platform_driver(sun20i_ppu_driver); + +MODULE_AUTHOR("Samuel Holland "); +MODULE_DESCRIPTION("Allwinner D1 PPU power domain driver"); +MODULE_LICENSE("GPL"); --=20 2.37.4 From nobody Sun Sep 14 05:38:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B7BFC05027 for ; Thu, 26 Jan 2023 06:34:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235972AbjAZGem (ORCPT ); Thu, 26 Jan 2023 01:34:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236156AbjAZGee (ORCPT ); Thu, 26 Jan 2023 01:34:34 -0500 Received: from wout3-smtp.messagingengine.com (wout3-smtp.messagingengine.com [64.147.123.19]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96B9947417; 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Thu, 26 Jan 2023 01:34:28 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Krzysztof Kozlowski , Samuel Holland , Andre Przywara , Conor Dooley , Heiko Stuebner , Palmer Dabbelt , Philipp Zabel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH v2 3/3] riscv: dts: allwinner: d1: Add power controller node Date: Thu, 26 Jan 2023 00:34:19 -0600 Message-Id: <20230126063419.15971-4-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126063419.15971-1-samuel@sholland.org> References: <20230126063419.15971-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Allwinner D1 family of SoCs contain a PPU power domain controller separate from the PRCM. It can power down the video engine and DSP, and it contains special logic for hardware-assisted CPU idle. Signed-off-by: Samuel Holland --- Changes in v2: - Include a patch adding the device tree node arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv= /boot/dts/allwinner/sunxi-d1s-t113.dtsi index 3723612b1fd8..6fadcee7800f 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -799,6 +799,14 @@ tcon_tv0_out_tcon_top_hdmi: endpoint { }; }; =20 + ppu: power-controller@7001000 { + compatible =3D "allwinner,sun20i-d1-ppu"; + reg =3D <0x7001000 0x1000>; + clocks =3D <&r_ccu CLK_BUS_R_PPU>; + resets =3D <&r_ccu RST_BUS_R_PPU>; + #power-domain-cells =3D <1>; + }; + r_ccu: clock-controller@7010000 { compatible =3D "allwinner,sun20i-d1-r-ccu"; reg =3D <0x7010000 0x400>; --=20 2.37.4