From nobody Sun Dec 22 12:20:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99444C05027 for ; Thu, 26 Jan 2023 04:58:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235934AbjAZE6E (ORCPT ); Wed, 25 Jan 2023 23:58:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234642AbjAZE5s (ORCPT ); Wed, 25 Jan 2023 23:57:48 -0500 Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE6FA552BF; Wed, 25 Jan 2023 20:57:43 -0800 (PST) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id 64BE75C01A6; Wed, 25 Jan 2023 23:57:43 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Wed, 25 Jan 2023 23:57:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; t=1674709063; x=1674795463; bh=o/ e/puF6snd7KFq3GxMEsxq1udDHzkLvKvVI5G9x/7s=; b=g9nPxRGayN9QsmCYb+ XoUUirWMb/7qEtXENZm27BFMCNDPYYI2XQVmhCdxFl/cuoAwvc9Sw24H8N8Xv0Vh zC7vyVmBDKJW+dHSZmHlxd90BJDIgoAEuexjJBf5TlNu27HmeJ0iBcTrSTGI9nkr R24ER+jul0w7e4w1Ij+dte4IOSVhMpTukX5X13rNC3eRnzXM2AllEe+Lv9Cu4Bff kMNrcmMu/af7nZhlTTu1H+IrdC16bPEjVzgWUD8W1zCcEw2HJbD2W9vSZXIvPrD2 xuHRqFK8hzUU8iXMS+MdRCKBvmysQK0dKV7YRpjYUy9KCBKt6qLl4kCcbzMyBxWf WVpQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; t=1674709063; x=1674795463; bh=o/e/puF6snd7K Fq3GxMEsxq1udDHzkLvKvVI5G9x/7s=; b=CVDM6qvrobMXLuGInIry59zZwfhNF d2NbyI1hWm/viN4/8kLa9QYmoxIhfotnn+/PSVXTq0z8zJmzF8Vh5ZcEptubm11i vVGsyEeVP3ZKNqGjOgXRXAs3+ogppSJxEg3r1uv/lmaSELAO6gN2kpJ2qeFWAIq8 8/Y+PrxJxqiMrw32Q99+p1JwEvcj8hL0kLU16dPC7J6J2ZJ4v9fdsOLL3ZsbOPth BO2BUsTvg4YykxXwculuAtMQ1GFmpv4DMumvWSbWGtLahWIqzEdyv1oRrrm2QnSa ROcJuz/xINqtMQvscenlW55DhNBpTx6iDgkECUrrUQ84cRWpfAMPGW5og== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedruddvfedgjeehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 25 Jan 2023 23:57:42 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev Cc: linux-riscv@lists.infradead.org, Heiko Stuebner , Palmer Dabbelt , Conor Dooley , Jisheng Zhang , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andre Przywara , Rob Herring , linux-arm-kernel@lists.infradead.org, Samuel Holland , Palmer Dabbelt , Conor Dooley , Heiko Stuebner Subject: [PATCH v5 04/11] riscv: dts: allwinner: Add the D1/D1s SoC devicetree Date: Wed, 25 Jan 2023 22:57:31 -0600 Message-Id: <20230126045738.47903-5-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126045738.47903-1-samuel@sholland.org> References: <20230126045738.47903-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based on a single die, or at a pair of dies derived from the same design. D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP variants. Because the original design supported both ARM and RISC-V CPUs, some peripherals are duplicated. In addition, all variants except D1s contain a HiFi 4 DSP with its own set of peripherals. The devicetrees are organized to minimize duplication: - Common perhiperals are described in sunxi-d1s-t113.dtsi - DSP-related peripherals are described in sunxi-d1-t113.dtsi - RISC-V specific hardware is described in sun20i-d1s.dtsi - Functionality unique to the D1 variant is described in sun20i-d1.dtsi The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC. Acked-by: Jernej Skrabec Acked-by: Palmer Dabbelt Reviewed-by: Andre Przywara Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Signed-off-by: Samuel Holland --- Changes in v5: - Drop system LDOs because the binding is still not merged Changes in v3: - Drop dummy DCXO clock-frequency property - Decrease the PLIC's riscv,ndev property to 175 - Fix `make W=3D1 dtbs` warnings (unnecessary #address/#size-cells) Changes in v2: - Split into separate files for sharing with D1s/R528/T113 - Use SOC_PERIPHERAL_IRQ macro for interrupts - Rename osc24M to dcxo and move the frequency to the board DTs - Drop analog LDOs due to the missing binding - Correct tcon_top DSI clock reference - Add DMIC, DSI controller, and DPHY (bindings are in linux-next) - Add CPU OPP table arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 66 ++ arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 76 ++ .../boot/dts/allwinner/sunxi-d1-t113.dtsi | 15 + .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 826 ++++++++++++++++++ 4 files changed, 983 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot= /dts/allwinner/sun20i-d1.dtsi new file mode 100644 index 000000000000..97e7cbb32597 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +#include "sun20i-d1s.dtsi" +#include "sunxi-d1-t113.dtsi" + +/ { + soc { + lradc: keys@2009800 { + compatible =3D "allwinner,sun20i-d1-lradc", + "allwinner,sun50i-r329-lradc"; + reg =3D <0x2009800 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_LRADC>; + resets =3D <&ccu RST_BUS_LRADC>; + status =3D "disabled"; + }; + + i2s0: i2s@2032000 { + compatible =3D "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg =3D <0x2032000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2S0>, + <&ccu CLK_I2S0>; + clock-names =3D "apb", "mod"; + resets =3D <&ccu RST_BUS_I2S0>; + dmas =3D <&dma 3>, <&dma 3>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #sound-dai-cells =3D <0>; + }; + }; +}; + +&pio { + /omit-if-no-ref/ + dmic_pb11_d0_pin: dmic-pb11-d0-pin { + pins =3D "PB11"; + function =3D "dmic"; + }; + + /omit-if-no-ref/ + dmic_pe17_clk_pin: dmic-pe17-clk-pin { + pins =3D "PE17"; + function =3D "dmic"; + }; + + /omit-if-no-ref/ + i2c0_pb10_pins: i2c0-pb10-pins { + pins =3D "PB10", "PB11"; + function =3D "i2c0"; + }; + + /omit-if-no-ref/ + i2c2_pb0_pins: i2c2-pb0-pins { + pins =3D "PB0", "PB1"; + function =3D "i2c2"; + }; + + /omit-if-no-ref/ + uart0_pb8_pins: uart0-pb8-pins { + pins =3D "PB8", "PB9"; + function =3D "uart0"; + }; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boo= t/dts/allwinner/sun20i-d1s.dtsi new file mode 100644 index 000000000000..8275630af977 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +#define SOC_PERIPHERAL_IRQ(nr) (nr + 16) + +#include "sunxi-d1s-t113.dtsi" + +/ { + cpus { + timebase-frequency =3D <24000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "thead,c906", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + clocks =3D <&ccu CLK_RISCV>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <32768>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <32768>; + mmu-type =3D "riscv,sv39"; + operating-points-v2 =3D <&opp_table_cpu>; + riscv,isa =3D "rv64imafdc"; + #cooling-cells =3D <2>; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; + + opp_table_cpu: opp-table-cpu { + compatible =3D "operating-points-v2"; + + opp-408000000 { + opp-hz =3D /bits/ 64 <408000000>; + opp-microvolt =3D <900000 900000 1100000>; + }; + + opp-1080000000 { + opp-hz =3D /bits/ 64 <1008000000>; + opp-microvolt =3D <900000 900000 1100000>; + }; + }; + + soc { + interrupt-parent =3D <&plic>; + + riscv_wdt: watchdog@6011000 { + compatible =3D "allwinner,sun20i-d1-wdt"; + reg =3D <0x6011000 0x20>; + interrupts =3D ; + clocks =3D <&dcxo>, <&rtc CLK_OSC32K>; + clock-names =3D "hosc", "losc"; + }; + + plic: interrupt-controller@10000000 { + compatible =3D "allwinner,sun20i-d1-plic", + "thead,c900-plic"; + reg =3D <0x10000000 0x4000000>; + interrupts-extended =3D <&cpu0_intc 11>, + <&cpu0_intc 9>; + interrupt-controller; + riscv,ndev =3D <175>; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi b/arch/riscv/= boot/dts/allwinner/sunxi-d1-t113.dtsi new file mode 100644 index 000000000000..b7156123df54 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +/ { + soc { + dsp_wdt: watchdog@1700400 { + compatible =3D "allwinner,sun20i-d1-wdt"; + reg =3D <0x1700400 0x20>; + interrupts =3D ; + clocks =3D <&dcxo>, <&rtc CLK_OSC32K>; + clock-names =3D "hosc", "losc"; + status =3D "reserved"; + }; + }; +}; diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv= /boot/dts/allwinner/sunxi-d1s-t113.dtsi new file mode 100644 index 000000000000..3723612b1fd8 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -0,0 +1,826 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + + dcxo: dcxo-clk { + compatible =3D "fixed-clock"; + clock-output-names =3D "dcxo"; + #clock-cells =3D <0>; + }; + + de: display-engine { + compatible =3D "allwinner,sun20i-d1-display-engine"; + allwinner,pipelines =3D <&mixer0>, <&mixer1>; + status =3D "disabled"; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + dma-noncoherent; + #address-cells =3D <1>; + #size-cells =3D <1>; + + pio: pinctrl@2000000 { + compatible =3D "allwinner,sun20i-d1-pinctrl"; + reg =3D <0x2000000 0x800>; + interrupts =3D , + , + , + , + , + ; + clocks =3D <&ccu CLK_APB0>, + <&dcxo>, + <&rtc CLK_OSC32K>; + clock-names =3D "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #gpio-cells =3D <3>; + #interrupt-cells =3D <3>; + + /omit-if-no-ref/ + clk_pg11_pin: clk-pg11-pin { + pins =3D "PG11"; + function =3D "clk"; + }; + + /omit-if-no-ref/ + dsi_4lane_pins: dsi-4lane-pins { + pins =3D "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", + "PD6", "PD7", "PD8", "PD9"; + drive-strength =3D <30>; + function =3D "dsi"; + }; + + /omit-if-no-ref/ + lcd_rgb666_pins: lcd-rgb666-pins { + pins =3D "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", + "PD18", "PD19", "PD20", "PD21"; + function =3D "lcd0"; + }; + + /omit-if-no-ref/ + mmc0_pins: mmc0-pins { + pins =3D "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function =3D "mmc0"; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins =3D "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; + function =3D "mmc1"; + }; + + /omit-if-no-ref/ + mmc2_pins: mmc2-pins { + pins =3D "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; + function =3D "mmc2"; + }; + + /omit-if-no-ref/ + rgmii_pe_pins: rgmii-pe-pins { + pins =3D "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9", + "PE11", "PE12", "PE13", "PE14", "PE15"; + function =3D "emac"; + }; + + /omit-if-no-ref/ + rmii_pe_pins: rmii-pe-pins { + pins =3D "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9"; + function =3D "emac"; + }; + + /omit-if-no-ref/ + uart1_pg6_pins: uart1-pg6-pins { + pins =3D "PG6", "PG7"; + function =3D "uart1"; + }; + + /omit-if-no-ref/ + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { + pins =3D "PG8", "PG9"; + function =3D "uart1"; + }; + + /omit-if-no-ref/ + uart3_pb_pins: uart3-pb-pins { + pins =3D "PB6", "PB7"; + function =3D "uart3"; + }; + }; + + ccu: clock-controller@2001000 { + compatible =3D "allwinner,sun20i-d1-ccu"; + reg =3D <0x2001000 0x1000>; + clocks =3D <&dcxo>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>; + clock-names =3D "hosc", "losc", "iosc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + dmic: dmic@2031000 { + compatible =3D "allwinner,sun20i-d1-dmic", + "allwinner,sun50i-h6-dmic"; + reg =3D <0x2031000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_DMIC>, + <&ccu CLK_DMIC>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_DMIC>; + dmas =3D <&dma 8>; + dma-names =3D "rx"; + status =3D "disabled"; + #sound-dai-cells =3D <0>; + }; + + i2s1: i2s@2033000 { + compatible =3D "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg =3D <0x2033000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2S1>, + <&ccu CLK_I2S1>; + clock-names =3D "apb", "mod"; + resets =3D <&ccu RST_BUS_I2S1>; + dmas =3D <&dma 4>, <&dma 4>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #sound-dai-cells =3D <0>; + }; + + i2s2: i2s@2034000 { + compatible =3D "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg =3D <0x2034000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2S2>, + <&ccu CLK_I2S2>; + clock-names =3D "apb", "mod"; + resets =3D <&ccu RST_BUS_I2S2>; + dmas =3D <&dma 5>, <&dma 5>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #sound-dai-cells =3D <0>; + }; + + timer: timer@2050000 { + compatible =3D "allwinner,sun20i-d1-timer", + "allwinner,sun8i-a23-timer"; + reg =3D <0x2050000 0xa0>; + interrupts =3D , + ; + clocks =3D <&dcxo>; + }; + + wdt: watchdog@20500a0 { + compatible =3D "allwinner,sun20i-d1-wdt-reset", + "allwinner,sun20i-d1-wdt"; + reg =3D <0x20500a0 0x20>; + interrupts =3D ; + clocks =3D <&dcxo>, <&rtc CLK_OSC32K>; + clock-names =3D "hosc", "losc"; + status =3D "reserved"; + }; + + uart0: serial@2500000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2500000 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_UART0>; + resets =3D <&ccu RST_BUS_UART0>; + dmas =3D <&dma 14>, <&dma 14>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart1: serial@2500400 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2500400 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_UART1>; + resets =3D <&ccu RST_BUS_UART1>; + dmas =3D <&dma 15>, <&dma 15>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart2: serial@2500800 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2500800 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_UART2>; + resets =3D <&ccu RST_BUS_UART2>; + dmas =3D <&dma 16>, <&dma 16>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart3: serial@2500c00 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2500c00 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_UART3>; + resets =3D <&ccu RST_BUS_UART3>; + dmas =3D <&dma 17>, <&dma 17>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart4: serial@2501000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2501000 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_UART4>; + resets =3D <&ccu RST_BUS_UART4>; + dmas =3D <&dma 18>, <&dma 18>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart5: serial@2501400 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2501400 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_UART5>; + resets =3D <&ccu RST_BUS_UART5>; + dmas =3D <&dma 19>, <&dma 19>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + i2c0: i2c@2502000 { + compatible =3D "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C0>; + resets =3D <&ccu RST_BUS_I2C0>; + dmas =3D <&dma 43>, <&dma 43>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c1: i2c@2502400 { + compatible =3D "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502400 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C1>; + resets =3D <&ccu RST_BUS_I2C1>; + dmas =3D <&dma 44>, <&dma 44>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c2: i2c@2502800 { + compatible =3D "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502800 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C2>; + resets =3D <&ccu RST_BUS_I2C2>; + dmas =3D <&dma 45>, <&dma 45>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c3: i2c@2502c00 { + compatible =3D "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502c00 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C3>; + resets =3D <&ccu RST_BUS_I2C3>; + dmas =3D <&dma 46>, <&dma 46>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + syscon: syscon@3000000 { + compatible =3D "allwinner,sun20i-d1-system-control"; + reg =3D <0x3000000 0x1000>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + dma: dma-controller@3002000 { + compatible =3D "allwinner,sun20i-d1-dma"; + reg =3D <0x3002000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names =3D "bus", "mbus"; + resets =3D <&ccu RST_BUS_DMA>; + dma-channels =3D <16>; + dma-requests =3D <48>; + #dma-cells =3D <1>; + }; + + sid: efuse@3006000 { + compatible =3D "allwinner,sun20i-d1-sid"; + reg =3D <0x3006000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + mbus: dram-controller@3102000 { + compatible =3D "allwinner,sun20i-d1-mbus"; + reg =3D <0x3102000 0x1000>, + <0x3103000 0x1000>; + reg-names =3D "mbus", "dram"; + interrupts =3D ; + clocks =3D <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names =3D "mbus", "dram", "bus"; + dma-ranges =3D <0 0x40000000 0x80000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + #interconnect-cells =3D <1>; + }; + + mmc0: mmc@4020000 { + compatible =3D "allwinner,sun20i-d1-mmc"; + reg =3D <0x4020000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC0>; + reset-names =3D "ahb"; + cap-sd-highspeed; + max-frequency =3D <150000000>; + no-mmc; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc1: mmc@4021000 { + compatible =3D "allwinner,sun20i-d1-mmc"; + reg =3D <0x4021000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC1>; + reset-names =3D "ahb"; + cap-sd-highspeed; + max-frequency =3D <150000000>; + no-mmc; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc2: mmc@4022000 { + compatible =3D "allwinner,sun20i-d1-emmc", + "allwinner,sun50i-a100-emmc"; + reg =3D <0x4022000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC2>; + reset-names =3D "ahb"; + cap-mmc-highspeed; + max-frequency =3D <150000000>; + mmc-ddr-1_8v; + mmc-ddr-3_3v; + no-sd; + no-sdio; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + usb_otg: usb@4100000 { + compatible =3D "allwinner,sun20i-d1-musb", + "allwinner,sun8i-a33-musb"; + reg =3D <0x4100000 0x400>; + interrupts =3D ; + interrupt-names =3D "mc"; + clocks =3D <&ccu CLK_BUS_OTG>; + resets =3D <&ccu RST_BUS_OTG>; + extcon =3D <&usbphy 0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + usbphy: phy@4100400 { + compatible =3D "allwinner,sun20i-d1-usb-phy"; + reg =3D <0x4100400 0x100>, + <0x4101800 0x100>, + <0x4200800 0x100>; + reg-names =3D "phy_ctrl", + "pmu0", + "pmu1"; + clocks =3D <&dcxo>, + <&dcxo>; + clock-names =3D "usb0_phy", + "usb1_phy"; + resets =3D <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names =3D "usb0_reset", + "usb1_reset"; + status =3D "disabled"; + #phy-cells =3D <1>; + }; + + ehci0: usb@4101000 { + compatible =3D "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg =3D <0x4101000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets =3D <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci0: usb@4101400 { + compatible =3D "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg =3D <0x4101400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets =3D <&ccu RST_BUS_OHCI0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ehci1: usb@4200000 { + compatible =3D "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg =3D <0x4200000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets =3D <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + phys =3D <&usbphy 1>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci1: usb@4200400 { + compatible =3D "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg =3D <0x4200400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets =3D <&ccu RST_BUS_OHCI1>; + phys =3D <&usbphy 1>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + emac: ethernet@4500000 { + compatible =3D "allwinner,sun20i-d1-emac", + "allwinner,sun50i-a64-emac"; + reg =3D <0x4500000 0x10000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clocks =3D <&ccu CLK_BUS_EMAC>; + clock-names =3D "stmmaceth"; + resets =3D <&ccu RST_BUS_EMAC>; + reset-names =3D "stmmaceth"; + syscon =3D <&syscon>; + status =3D "disabled"; + + mdio: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + display_clocks: clock-controller@5000000 { + compatible =3D "allwinner,sun20i-d1-de2-clk", + "allwinner,sun50i-h5-de2-clk"; + reg =3D <0x5000000 0x10000>; + clocks =3D <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_DE>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + mixer0: mixer@5100000 { + compatible =3D "allwinner,sun20i-d1-de2-mixer-0"; + reg =3D <0x5100000 0x100000>; + clocks =3D <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names =3D "bus", "mod"; + resets =3D <&display_clocks RST_MIXER0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mixer0_out: port@1 { + reg =3D <1>; + + mixer0_out_tcon_top_mixer0: endpoint { + remote-endpoint =3D <&tcon_top_mixer0_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@5200000 { + compatible =3D "allwinner,sun20i-d1-de2-mixer-1"; + reg =3D <0x5200000 0x100000>; + clocks =3D <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names =3D "bus", "mod"; + resets =3D <&display_clocks RST_MIXER1>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mixer1_out: port@1 { + reg =3D <1>; + + mixer1_out_tcon_top_mixer1: endpoint { + remote-endpoint =3D <&tcon_top_mixer1_in_mixer1>; + }; + }; + }; + }; + + dsi: dsi@5450000 { + compatible =3D "allwinner,sun20i-d1-mipi-dsi", + "allwinner,sun50i-a100-mipi-dsi"; + reg =3D <0x5450000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_MIPI_DSI>, + <&tcon_top CLK_TCON_TOP_DSI>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_MIPI_DSI>; + phys =3D <&dphy>; + phy-names =3D "dphy"; + status =3D "disabled"; + + port { + dsi_in_tcon_lcd0: endpoint { + remote-endpoint =3D <&tcon_lcd0_out_dsi>; + }; + }; + }; + + dphy: phy@5451000 { + compatible =3D "allwinner,sun20i-d1-mipi-dphy", + "allwinner,sun50i-a100-mipi-dphy"; + reg =3D <0x5451000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_MIPI_DSI>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_MIPI_DSI>; + #phy-cells =3D <0>; + }; + + tcon_top: tcon-top@5460000 { + compatible =3D "allwinner,sun20i-d1-tcon-top"; + reg =3D <0x5460000 0x1000>; + clocks =3D <&ccu CLK_BUS_DPSS_TOP>, + <&ccu CLK_TCON_TV>, + <&ccu CLK_TVE>, + <&ccu CLK_TCON_LCD0>; + clock-names =3D "bus", "tcon-tv0", "tve0", "dsi"; + clock-output-names =3D "tcon-top-tv0", "tcon-top-dsi"; + resets =3D <&ccu RST_BUS_DPSS_TOP>; + #clock-cells =3D <1>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer0_in: port@0 { + reg =3D <0>; + + tcon_top_mixer0_in_mixer0: endpoint { + remote-endpoint =3D <&mixer0_out_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer0_out: port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&tcon_lcd0_in_tcon_top_mixer0>; + }; + + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { + reg =3D <2>; + remote-endpoint =3D <&tcon_tv0_in_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer1_in: port@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer1_in_mixer1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&mixer1_out_tcon_top_mixer1>; + }; + }; + + tcon_top_mixer1_out: port@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&tcon_lcd0_in_tcon_top_mixer1>; + }; + + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { + reg =3D <2>; + remote-endpoint =3D <&tcon_tv0_in_tcon_top_mixer1>; + }; + }; + + tcon_top_hdmi_in: port@4 { + reg =3D <4>; + + tcon_top_hdmi_in_tcon_tv0: endpoint { + remote-endpoint =3D <&tcon_tv0_out_tcon_top_hdmi>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg =3D <5>; + }; + }; + }; + + tcon_lcd0: lcd-controller@5461000 { + compatible =3D "allwinner,sun20i-d1-tcon-lcd"; + reg =3D <0x5461000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_TCON_LCD0>, + <&ccu CLK_TCON_LCD0>; + clock-names =3D "ahb", "tcon-ch0"; + clock-output-names =3D "tcon-pixel-clock"; + resets =3D <&ccu RST_BUS_TCON_LCD0>, + <&ccu RST_BUS_LVDS0>; + reset-names =3D "lcd", "lvds"; + #clock-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_lcd0_in: port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&tcon_top_mixer0_out_tcon_lcd0>; + }; + + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&tcon_top_mixer1_out_tcon_lcd0>; + }; + }; + + tcon_lcd0_out: port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_lcd0_out_dsi: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&dsi_in_tcon_lcd0>; + }; + }; + }; + }; + + tcon_tv0: lcd-controller@5470000 { + compatible =3D "allwinner,sun20i-d1-tcon-tv"; + reg =3D <0x5470000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_TCON_TV>, + <&tcon_top CLK_TCON_TOP_TV0>; + clock-names =3D "ahb", "tcon-ch1"; + resets =3D <&ccu RST_BUS_TCON_TV>; + reset-names =3D "lcd"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_tv0_in: port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_tv0_in_tcon_top_mixer0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&tcon_top_mixer0_out_tcon_tv0>; + }; + + tcon_tv0_in_tcon_top_mixer1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&tcon_top_mixer1_out_tcon_tv0>; + }; + }; + + tcon_tv0_out: port@1 { + reg =3D <1>; + + tcon_tv0_out_tcon_top_hdmi: endpoint { + remote-endpoint =3D <&tcon_top_hdmi_in_tcon_tv0>; + }; + }; + }; + }; + + r_ccu: clock-controller@7010000 { + compatible =3D "allwinner,sun20i-d1-r-ccu"; + reg =3D <0x7010000 0x400>; + clocks =3D <&dcxo>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_PERIPH0_DIV3>; + clock-names =3D "hosc", "losc", "iosc", "pll-periph"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + rtc: rtc@7090000 { + compatible =3D "allwinner,sun20i-d1-rtc", + "allwinner,sun50i-r329-rtc"; + reg =3D <0x7090000 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_BUS_R_RTC>, + <&dcxo>, + <&r_ccu CLK_R_AHB>; + clock-names =3D "bus", "hosc", "ahb"; + #clock-cells =3D <1>; + }; + }; +}; --=20 2.37.4