From nobody Sun Dec 22 17:55:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CBFFC05027 for ; Thu, 26 Jan 2023 04:57:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235341AbjAZE5u (ORCPT ); Wed, 25 Jan 2023 23:57:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229446AbjAZE5m (ORCPT ); Wed, 25 Jan 2023 23:57:42 -0500 Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A75D552BF; Wed, 25 Jan 2023 20:57:41 -0800 (PST) Received: from compute6.internal (compute6.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id 188255C01B6; Wed, 25 Jan 2023 23:57:39 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute6.internal (MEProxy); Wed, 25 Jan 2023 23:57:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; t=1674709059; x=1674795459; bh=X9 s6cjs86up+hYIsx64vzFJpoNRPbaCk4kY0RDMfADM=; b=ZdfM3FHeaYvIoHcQHq Mu1XGs6brJrMAo8pzIvFqLwScLYzcIGA4/oKuganif+5zjOxXSlQ7kuIFKZ8avYT EfmX596NVkSAIdcWTDCAjqfuE9/XzN7SZbyCkCt5oIhYNKn5wjtq2kwLdUimeCHa 1eWgUjERUxTu1YLjXZXfcm18LePGJVLjH6JGfHIMIqPUbbzuMeluTtyEjwPGZ6Ej gu9fN2dKLpqCBdK69J+jt7bHyPgwqkfDbNZk0EHa9qoYtHBWn0ZlJU8mCf/l+zvv UK5D94FncKy1GfcVXxk/aB5M0/N2XxnTOLBEcZzEN0TCjdZmvas3EiHmv9IeSWav okEw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; t=1674709059; x=1674795459; bh=X9s6cjs86up+h YIsx64vzFJpoNRPbaCk4kY0RDMfADM=; b=aMnaHHNqYI09i7aWVOdETtUjh0iXl o82oN73/s9VaKfU4CxNbz0a/OfjJoYNTSfDCBnSNVLbzEl4HYGZb2+2KtSlJuDCg lCg+Q3+v5acB+D2jHnCDa/u7I1hVip8VfnXbaPMm0+abg63d/VCcsghXUN59sdeF 2xk0i/wF8enIDLMibiEi2Ey8bsEAem81EHDJ80BZKVr3eotubyd0J1Lu5J/c0TGa muRgAVintA06SY7a4EKMh7hfDyGZqfWxscYY/n5UdFlSd1BS9mjU9L+KDZZqq4wM uHJUZaNDHLB24KEqKGkbsJnOGCsTYDC1hILNlYPFm0vC9Rs+K4rPKffvw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedruddvfedgjeehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 25 Jan 2023 23:57:37 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev Cc: linux-riscv@lists.infradead.org, Heiko Stuebner , Palmer Dabbelt , Conor Dooley , Jisheng Zhang , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andre Przywara , Rob Herring , linux-arm-kernel@lists.infradead.org, Samuel Holland , Guo Ren Subject: [PATCH v5 01/11] MAINTAINERS: Match the sun20i family of Allwinner SoCs Date: Wed, 25 Jan 2023 22:57:28 -0600 Message-Id: <20230126045738.47903-2-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126045738.47903-1-samuel@sholland.org> References: <20230126045738.47903-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allwinner sunxi SoCs with a RISC-V CPU use the sun20i designator. Match that pattern in addition to the designators for 32 and 64-bit ARM SoCs. Acked-by: Jernej Skrabec Reviewed-by: Guo Ren Reviewed-by: Heiko Stuebner Signed-off-by: Samuel Holland Acked-by: Conor Dooley --- (no changes since v1) MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 3b0148001f92..2600c85bdfd5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1887,7 +1887,7 @@ F: drivers/pinctrl/sunxi/ F: drivers/soc/sunxi/ N: allwinner N: sun[x456789]i -N: sun50i +N: sun[25]0i =20 ARM/Amlogic Meson SoC CLOCK FRAMEWORK M: Neil Armstrong --=20 2.37.4 From nobody Sun Dec 22 17:55:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2070C61DA0 for ; Thu, 26 Jan 2023 04:57:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231129AbjAZE5q (ORCPT ); Wed, 25 Jan 2023 23:57:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229475AbjAZE5m (ORCPT ); Wed, 25 Jan 2023 23:57:42 -0500 Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A888561B2; Wed, 25 Jan 2023 20:57:41 -0800 (PST) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id 7001D5C0568; Wed, 25 Jan 2023 23:57:40 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Wed, 25 Jan 2023 23:57:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; t=1674709060; x=1674795460; bh=f3 oasT/IpT0I6FIdvaYChRtQISkb5cTVuFVOSELrKsg=; b=Fi2x6BtbpdsY9nDuwz eC3X/KHKds3VnAHYxcGGlNHeSd9HxQsKIu0gzDD26pnMKHdZ/LWJjZO1lDyZ1MNT T5T3TZNQCEuZfO4GAVXPw77ARCREyWQWQOPlGeiSjTjUsKNibULBZgrVsxB7g4Wj dAHfqIrNJIFOXr8jM6eaA00XECAGOTEAiWLtrvDmb67f7GqixbwcqE1YGCOkxbg2 6tnmvLnDcOSz6MeywPh30TyxoXg9GvDv+f3XmlmDg8CfSyzMr4hqpISAKXGQdJ6b XdG7wyirB/yVa0ZWcFpZo/GsnKv+wrdSbB+cDQ+YuC3eqWKoJIV/tHYyxgo48GXq Odew== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; t=1674709060; x=1674795460; bh=f3oasT/IpT0I6 FIdvaYChRtQISkb5cTVuFVOSELrKsg=; b=HD1684ckEAu5yS6v8C+GdqwVY0fQr LLADtxp4U28bqw9nVuqfN+fZRQ5Ev/pkOwfTfacBXGsjEXv4flzI/3iGoIVlRRj1 WvztxU7sONa0LIY1rKBFuijVEB+UfRqVOXw7CGrQq6j2R+sQ3RIKceFGq27Thx3S AWFQhzetSygtk4y+g/CXOCqAJAp7opFJB2A/rbG194UXw/LBSGITQlqWes7zJCIm iua2iO1bnju8GZUMPULdyzfLgGYmWDUp060C3eg5aQ4BDYyhyiGfFGjzO2fblYBT P4GXXXKJx8eGo4gLfatywBv3sJgz/ukP1Ug3t1Z93AQZXYaCJzQp/Kskg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedruddvfedgjeehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne gfrhhlucfvnfffucdljedmnecujfgurhephffvvefufffkofgjfhgggfestdekredtredt tdenucfhrhhomhepufgrmhhuvghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholh hlrghnugdrohhrgheqnecuggftrfgrthhtvghrnhepleevtddvvdevieekieffjefggfeu ieetieelveelhfeukeejvddvgfeiveekleefnecuffhomhgrihhnpegtlhhotghkfihorh hkphhirdgtohhmpdhmrghnghhophhirdgttgenucevlhhushhtvghrufhiiigvpedtnecu rfgrrhgrmhepmhgrihhlfhhrohhmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 25 Jan 2023 23:57:39 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev Cc: linux-riscv@lists.infradead.org, Heiko Stuebner , Palmer Dabbelt , Conor Dooley , Jisheng Zhang , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andre Przywara , Rob Herring , linux-arm-kernel@lists.infradead.org, Samuel Holland , Palmer Dabbelt , Rob Herring , Guo Ren Subject: [PATCH v5 02/11] dt-bindings: vendor-prefixes: Add Allwinner D1/D1s board vendors Date: Wed, 25 Jan 2023 22:57:29 -0600 Message-Id: <20230126045738.47903-3-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126045738.47903-1-samuel@sholland.org> References: <20230126045738.47903-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some boards using the Allwinner D1 or D1s SoC are made by vendors not previously documented. Clockwork Tech LLC (https://www.clockworkpi.com/) manufactures the ClockworkPi and DevTerm boards. Beijing Widora Technology Co., Ltd. (https://mangopi.cc/) manufactures the MangoPi family of boards. Acked-by: Palmer Dabbelt Acked-by: Rob Herring Reviewed-by: Guo Ren Reviewed-by: Heiko Stuebner Signed-off-by: Samuel Holland Acked-by: Conor Dooley --- (no changes since v4) Changes in v4: - Rebase on v6.2-rc1 + soc2arch-immutable Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index eac00f1c770e..b7055a43c6c4 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -264,6 +264,8 @@ patternProperties: description: Cirrus Logic, Inc. "^cisco,.*": description: Cisco Systems, Inc. + "^clockwork,.*": + description: Clockwork Tech LLC "^cloos,.*": description: Carl Cloos Schweisstechnik GmbH. "^cloudengines,.*": @@ -1448,6 +1450,8 @@ patternProperties: description: Shenzhen whwave Electronics, Inc. "^wi2wi,.*": description: Wi2Wi, Inc. + "^widora,.*": + description: Beijing Widora Technology Co., Ltd. "^wiligear,.*": description: Wiligear, Ltd. "^willsemi,.*": --=20 2.37.4 From nobody Sun Dec 22 17:55:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49745C05027 for ; Thu, 26 Jan 2023 04:57:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235476AbjAZE54 (ORCPT ); Wed, 25 Jan 2023 23:57:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230244AbjAZE5n (ORCPT ); Wed, 25 Jan 2023 23:57:43 -0500 Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2CD95689E; Wed, 25 Jan 2023 20:57:42 -0800 (PST) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id 1EEF15C01A7; Wed, 25 Jan 2023 23:57:42 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Wed, 25 Jan 2023 23:57:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; t=1674709062; x=1674795462; bh=1I mKfp6mi3k5y3IxQlr3G7vHr9aqIhKTT53gvo+gyWE=; b=hhcBO5594PxuoNyFDW H69ldQx9OIrTw1o6Prp/uDZzoBJvVa9R/X+xpknKnTQmH06Hg5nmTI4Va3sWkIxK fTZ/R37r9EpDbR79rbIPMINoWMITMguqRJErOYim5xew5JxntYawld9jV4Fy8Igb b8q2BRieftj1/E+bARukzf8asV4aj3XFAKb39dtWB5gv+9qcu4FTEG3EtOFIa3ZN CjAExxzj7nw724fmJdYW6UqiXW1AALsauJ3BDTIU9F24nDauqM3irW2BGQPAj5f8 eAo3WOeO0modqrrSGHgSIf3yL4AefqT3gf97QFtLkrEkGOAVixso7VtwTTxalzjH zUnw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; t=1674709062; x=1674795462; bh=1ImKfp6mi3k5y 3IxQlr3G7vHr9aqIhKTT53gvo+gyWE=; b=KvFit1lrT4uVUKDgzJ6l39Mthrz+4 hsCEydgQOJcN0vaTjGue/KEzVb+piFgLnFLbBqTllzlucGWfZiJK0byye9NVdK8v ON1E2IkXxZNhnhCvDQipKm3E4B8jmPAyaSA4p2whn/GkGP1dQmM4jTmSKSm/1Dd4 CL+pPqNKijDMM9uMJMLED/zi8S2gnzcNeJVCW9dq91vYd/XT7JEnlM3e4V9wP2+m wFp41ou8dSmuD8ShgGaelXfUtpsQdLrM/g/Ri8u/sy2GYHaHVeDra1/SdaXabdJI sZh1zcccrLPLa7cZMtSwvllHjM29gSHoI/T7y2GiKfnTdS+ENfnGrVmJg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedruddvfedgjeehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepgffhvefhgfehjeehgfekheeuffegheffjeegheeuudeufeffhffh ueeihfeufffhnecuffhomhgrihhnpeguvghvihgtvghtrhgvvgdrohhrghenucevlhhush htvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehsrghmuhgvlhesshhh ohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 25 Jan 2023 23:57:40 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev Cc: linux-riscv@lists.infradead.org, Heiko Stuebner , Palmer Dabbelt , Conor Dooley , Jisheng Zhang , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andre Przywara , Rob Herring , linux-arm-kernel@lists.infradead.org, Samuel Holland , Palmer Dabbelt , Rob Herring , Conor Dooley , Guo Ren , Heiko Stuebner Subject: [PATCH v5 03/11] dt-bindings: riscv: Add Allwinner D1/D1s board compatibles Date: Wed, 25 Jan 2023 22:57:30 -0600 Message-Id: <20230126045738.47903-4-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126045738.47903-1-samuel@sholland.org> References: <20230126045738.47903-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Several SoMs and boards are available that feature the Allwinner D1 or D1s SoC. Document their compatible strings. Acked-by: Palmer Dabbelt Acked-by: Rob Herring Reviewed-by: Conor Dooley Reviewed-by: Guo Ren Reviewed-by: Heiko Stuebner Signed-off-by: Samuel Holland Acked-by: Conor Dooley --- (no changes since v2) Changes in v2: - Add MangoPi MQ (non-Pro) board .../devicetree/bindings/riscv/sunxi.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml diff --git a/Documentation/devicetree/bindings/riscv/sunxi.yaml b/Documenta= tion/devicetree/bindings/riscv/sunxi.yaml new file mode 100644 index 000000000000..9edb5e5992b1 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sunxi.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sunxi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner RISC-V SoC-based boards + +maintainers: + - Chen-Yu Tsai + - Jernej Skrabec + - Samuel Holland + +description: + Allwinner RISC-V SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Dongshan Nezha STU SoM + items: + - const: 100ask,dongshan-nezha-stu + - const: allwinner,sun20i-d1 + + - description: D1 Nezha board + items: + - const: allwinner,d1-nezha + - const: allwinner,sun20i-d1 + + - description: ClockworkPi R-01 SoM and v3.14 board + items: + - const: clockwork,r-01-clockworkpi-v3.14 + - const: allwinner,sun20i-d1 + + - description: ClockworkPi R-01 SoM, v3.14 board, and DevTerm expans= ion + items: + - const: clockwork,r-01-devterm-v3.14 + - const: clockwork,r-01-clockworkpi-v3.14 + - const: allwinner,sun20i-d1 + + - description: Lichee RV SoM + items: + - const: sipeed,lichee-rv + - const: allwinner,sun20i-d1 + + - description: Carrier boards for the Lichee RV SoM + items: + - enum: + - sipeed,lichee-rv-86-panel-480p + - sipeed,lichee-rv-86-panel-720p + - sipeed,lichee-rv-dock + - const: sipeed,lichee-rv + - const: allwinner,sun20i-d1 + + - description: MangoPi MQ board + items: + - const: widora,mangopi-mq + - const: allwinner,sun20i-d1s + + - description: MangoPi MQ Pro board + items: + - const: widora,mangopi-mq-pro + - const: allwinner,sun20i-d1 + +additionalProperties: true + +... --=20 2.37.4 From nobody Sun Dec 22 17:55:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99444C05027 for ; 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Wed, 25 Jan 2023 23:57:42 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev Cc: linux-riscv@lists.infradead.org, Heiko Stuebner , Palmer Dabbelt , Conor Dooley , Jisheng Zhang , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andre Przywara , Rob Herring , linux-arm-kernel@lists.infradead.org, Samuel Holland , Palmer Dabbelt , Conor Dooley , Heiko Stuebner Subject: [PATCH v5 04/11] riscv: dts: allwinner: Add the D1/D1s SoC devicetree Date: Wed, 25 Jan 2023 22:57:31 -0600 Message-Id: <20230126045738.47903-5-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126045738.47903-1-samuel@sholland.org> References: <20230126045738.47903-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based on a single die, or at a pair of dies derived from the same design. D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP variants. Because the original design supported both ARM and RISC-V CPUs, some peripherals are duplicated. In addition, all variants except D1s contain a HiFi 4 DSP with its own set of peripherals. The devicetrees are organized to minimize duplication: - Common perhiperals are described in sunxi-d1s-t113.dtsi - DSP-related peripherals are described in sunxi-d1-t113.dtsi - RISC-V specific hardware is described in sun20i-d1s.dtsi - Functionality unique to the D1 variant is described in sun20i-d1.dtsi The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC. Acked-by: Jernej Skrabec Acked-by: Palmer Dabbelt Reviewed-by: Andre Przywara Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Signed-off-by: Samuel Holland Acked-by: Conor Dooley --- Changes in v5: - Drop system LDOs because the binding is still not merged Changes in v3: - Drop dummy DCXO clock-frequency property - Decrease the PLIC's riscv,ndev property to 175 - Fix `make W=3D1 dtbs` warnings (unnecessary #address/#size-cells) Changes in v2: - Split into separate files for sharing with D1s/R528/T113 - Use SOC_PERIPHERAL_IRQ macro for interrupts - Rename osc24M to dcxo and move the frequency to the board DTs - Drop analog LDOs due to the missing binding - Correct tcon_top DSI clock reference - Add DMIC, DSI controller, and DPHY (bindings are in linux-next) - Add CPU OPP table arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 66 ++ arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 76 ++ .../boot/dts/allwinner/sunxi-d1-t113.dtsi | 15 + .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 826 ++++++++++++++++++ 4 files changed, 983 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot= /dts/allwinner/sun20i-d1.dtsi new file mode 100644 index 000000000000..97e7cbb32597 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +#include "sun20i-d1s.dtsi" +#include "sunxi-d1-t113.dtsi" + +/ { + soc { + lradc: keys@2009800 { + compatible =3D "allwinner,sun20i-d1-lradc", + "allwinner,sun50i-r329-lradc"; + reg =3D <0x2009800 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_LRADC>; + resets =3D <&ccu RST_BUS_LRADC>; + status =3D "disabled"; + }; + + i2s0: i2s@2032000 { + compatible =3D "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg =3D <0x2032000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2S0>, + <&ccu CLK_I2S0>; + clock-names =3D "apb", "mod"; + resets =3D <&ccu RST_BUS_I2S0>; + dmas =3D <&dma 3>, <&dma 3>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #sound-dai-cells =3D <0>; + }; + }; +}; + +&pio { + /omit-if-no-ref/ + dmic_pb11_d0_pin: dmic-pb11-d0-pin { + pins =3D "PB11"; + function =3D "dmic"; + }; + + /omit-if-no-ref/ + dmic_pe17_clk_pin: dmic-pe17-clk-pin { + pins =3D "PE17"; + function =3D "dmic"; + }; + + /omit-if-no-ref/ + i2c0_pb10_pins: i2c0-pb10-pins { + pins =3D "PB10", "PB11"; + function =3D "i2c0"; + }; + + /omit-if-no-ref/ + i2c2_pb0_pins: i2c2-pb0-pins { + pins =3D "PB0", "PB1"; + function =3D "i2c2"; + }; + + /omit-if-no-ref/ + uart0_pb8_pins: uart0-pb8-pins { + pins =3D "PB8", "PB9"; + function =3D "uart0"; + }; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boo= t/dts/allwinner/sun20i-d1s.dtsi new file mode 100644 index 000000000000..8275630af977 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +#define SOC_PERIPHERAL_IRQ(nr) (nr + 16) + +#include "sunxi-d1s-t113.dtsi" + +/ { + cpus { + timebase-frequency =3D <24000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "thead,c906", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + clocks =3D <&ccu CLK_RISCV>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <32768>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <32768>; + mmu-type =3D "riscv,sv39"; + operating-points-v2 =3D <&opp_table_cpu>; + riscv,isa =3D "rv64imafdc"; + #cooling-cells =3D <2>; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; + + opp_table_cpu: opp-table-cpu { + compatible =3D "operating-points-v2"; + + opp-408000000 { + opp-hz =3D /bits/ 64 <408000000>; + opp-microvolt =3D <900000 900000 1100000>; + }; + + opp-1080000000 { + opp-hz =3D /bits/ 64 <1008000000>; + opp-microvolt =3D <900000 900000 1100000>; + }; + }; + + soc { + interrupt-parent =3D <&plic>; + + riscv_wdt: watchdog@6011000 { + compatible =3D "allwinner,sun20i-d1-wdt"; + reg =3D <0x6011000 0x20>; + interrupts =3D ; + clocks =3D <&dcxo>, <&rtc CLK_OSC32K>; + clock-names =3D "hosc", "losc"; + }; + + plic: interrupt-controller@10000000 { + compatible =3D "allwinner,sun20i-d1-plic", + "thead,c900-plic"; + reg =3D <0x10000000 0x4000000>; + interrupts-extended =3D <&cpu0_intc 11>, + <&cpu0_intc 9>; + interrupt-controller; + riscv,ndev =3D <175>; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi b/arch/riscv/= boot/dts/allwinner/sunxi-d1-t113.dtsi new file mode 100644 index 000000000000..b7156123df54 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +/ { + soc { + dsp_wdt: watchdog@1700400 { + compatible =3D "allwinner,sun20i-d1-wdt"; + reg =3D <0x1700400 0x20>; + interrupts =3D ; + clocks =3D <&dcxo>, <&rtc CLK_OSC32K>; + clock-names =3D "hosc", "losc"; + status =3D "reserved"; + }; + }; +}; diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv= /boot/dts/allwinner/sunxi-d1s-t113.dtsi new file mode 100644 index 000000000000..3723612b1fd8 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -0,0 +1,826 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + + dcxo: dcxo-clk { + compatible =3D "fixed-clock"; + clock-output-names =3D "dcxo"; + #clock-cells =3D <0>; + }; + + de: display-engine { + compatible =3D "allwinner,sun20i-d1-display-engine"; + allwinner,pipelines =3D <&mixer0>, <&mixer1>; + status =3D "disabled"; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + dma-noncoherent; + #address-cells =3D <1>; + #size-cells =3D <1>; + + pio: pinctrl@2000000 { + compatible =3D "allwinner,sun20i-d1-pinctrl"; + reg =3D <0x2000000 0x800>; + interrupts =3D , + , + , + , + , + ; + clocks =3D <&ccu CLK_APB0>, + <&dcxo>, + <&rtc CLK_OSC32K>; + clock-names =3D "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #gpio-cells =3D <3>; + #interrupt-cells =3D <3>; + + /omit-if-no-ref/ + clk_pg11_pin: clk-pg11-pin { + pins =3D "PG11"; + function =3D "clk"; + }; + + /omit-if-no-ref/ + dsi_4lane_pins: dsi-4lane-pins { + pins =3D "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", + "PD6", "PD7", "PD8", "PD9"; + drive-strength =3D <30>; + function =3D "dsi"; + }; + + /omit-if-no-ref/ + lcd_rgb666_pins: lcd-rgb666-pins { + pins =3D "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", + "PD18", "PD19", "PD20", "PD21"; + function =3D "lcd0"; + }; + + /omit-if-no-ref/ + mmc0_pins: mmc0-pins { + pins =3D "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function =3D "mmc0"; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins =3D "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; + function =3D "mmc1"; + }; + + /omit-if-no-ref/ + mmc2_pins: mmc2-pins { + pins =3D "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; + function =3D "mmc2"; + }; + + /omit-if-no-ref/ + rgmii_pe_pins: rgmii-pe-pins { + pins =3D "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9", + "PE11", "PE12", "PE13", "PE14", "PE15"; + function =3D "emac"; + }; + + /omit-if-no-ref/ + rmii_pe_pins: rmii-pe-pins { + pins =3D "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9"; + function =3D "emac"; + }; + + /omit-if-no-ref/ + uart1_pg6_pins: uart1-pg6-pins { + pins =3D "PG6", "PG7"; + function =3D "uart1"; + }; + + /omit-if-no-ref/ + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { + pins =3D "PG8", "PG9"; + function =3D "uart1"; + }; + + /omit-if-no-ref/ + uart3_pb_pins: uart3-pb-pins { + pins =3D "PB6", "PB7"; + function =3D "uart3"; + }; + }; + + ccu: clock-controller@2001000 { + compatible =3D "allwinner,sun20i-d1-ccu"; + reg =3D <0x2001000 0x1000>; + clocks =3D <&dcxo>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>; + clock-names =3D "hosc", "losc", "iosc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + dmic: dmic@2031000 { + compatible =3D "allwinner,sun20i-d1-dmic", + "allwinner,sun50i-h6-dmic"; + reg =3D <0x2031000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_DMIC>, + <&ccu CLK_DMIC>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_DMIC>; + dmas =3D <&dma 8>; + dma-names =3D "rx"; + status =3D "disabled"; + #sound-dai-cells =3D <0>; + }; + + i2s1: i2s@2033000 { + compatible =3D "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg =3D <0x2033000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2S1>, + <&ccu CLK_I2S1>; + clock-names =3D "apb", "mod"; + resets =3D <&ccu RST_BUS_I2S1>; + dmas =3D <&dma 4>, <&dma 4>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #sound-dai-cells =3D <0>; + }; + + i2s2: i2s@2034000 { + compatible =3D "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg =3D <0x2034000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2S2>, + <&ccu CLK_I2S2>; + clock-names =3D "apb", "mod"; + resets =3D <&ccu RST_BUS_I2S2>; + dmas =3D <&dma 5>, <&dma 5>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #sound-dai-cells =3D <0>; + }; + + timer: timer@2050000 { + compatible =3D "allwinner,sun20i-d1-timer", + "allwinner,sun8i-a23-timer"; + reg =3D <0x2050000 0xa0>; + interrupts =3D , + ; + clocks =3D <&dcxo>; + }; + + wdt: watchdog@20500a0 { + compatible =3D "allwinner,sun20i-d1-wdt-reset", + "allwinner,sun20i-d1-wdt"; + reg =3D <0x20500a0 0x20>; + interrupts =3D ; + clocks =3D <&dcxo>, <&rtc CLK_OSC32K>; + clock-names =3D "hosc", "losc"; + status =3D "reserved"; + }; + + uart0: serial@2500000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2500000 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_UART0>; + resets =3D <&ccu RST_BUS_UART0>; + dmas =3D <&dma 14>, <&dma 14>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart1: serial@2500400 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2500400 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_UART1>; + resets =3D <&ccu RST_BUS_UART1>; + dmas =3D <&dma 15>, <&dma 15>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart2: serial@2500800 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2500800 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_UART2>; + resets =3D <&ccu RST_BUS_UART2>; + dmas =3D <&dma 16>, <&dma 16>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart3: serial@2500c00 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2500c00 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_UART3>; + resets =3D <&ccu RST_BUS_UART3>; + dmas =3D <&dma 17>, <&dma 17>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart4: serial@2501000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2501000 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_UART4>; + resets =3D <&ccu RST_BUS_UART4>; + dmas =3D <&dma 18>, <&dma 18>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart5: serial@2501400 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2501400 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_UART5>; + resets =3D <&ccu RST_BUS_UART5>; + dmas =3D <&dma 19>, <&dma 19>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + i2c0: i2c@2502000 { + compatible =3D "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C0>; + resets =3D <&ccu RST_BUS_I2C0>; + dmas =3D <&dma 43>, <&dma 43>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c1: i2c@2502400 { + compatible =3D "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502400 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C1>; + resets =3D <&ccu RST_BUS_I2C1>; + dmas =3D <&dma 44>, <&dma 44>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c2: i2c@2502800 { + compatible =3D "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502800 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C2>; + resets =3D <&ccu RST_BUS_I2C2>; + dmas =3D <&dma 45>, <&dma 45>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c3: i2c@2502c00 { + compatible =3D "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502c00 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C3>; + resets =3D <&ccu RST_BUS_I2C3>; + dmas =3D <&dma 46>, <&dma 46>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + syscon: syscon@3000000 { + compatible =3D "allwinner,sun20i-d1-system-control"; + reg =3D <0x3000000 0x1000>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + dma: dma-controller@3002000 { + compatible =3D "allwinner,sun20i-d1-dma"; + reg =3D <0x3002000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names =3D "bus", "mbus"; + resets =3D <&ccu RST_BUS_DMA>; + dma-channels =3D <16>; + dma-requests =3D <48>; + #dma-cells =3D <1>; + }; + + sid: efuse@3006000 { + compatible =3D "allwinner,sun20i-d1-sid"; + reg =3D <0x3006000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + mbus: dram-controller@3102000 { + compatible =3D "allwinner,sun20i-d1-mbus"; + reg =3D <0x3102000 0x1000>, + <0x3103000 0x1000>; + reg-names =3D "mbus", "dram"; + interrupts =3D ; + clocks =3D <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names =3D "mbus", "dram", "bus"; + dma-ranges =3D <0 0x40000000 0x80000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + #interconnect-cells =3D <1>; + }; + + mmc0: mmc@4020000 { + compatible =3D "allwinner,sun20i-d1-mmc"; + reg =3D <0x4020000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC0>; + reset-names =3D "ahb"; + cap-sd-highspeed; + max-frequency =3D <150000000>; + no-mmc; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc1: mmc@4021000 { + compatible =3D "allwinner,sun20i-d1-mmc"; + reg =3D <0x4021000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC1>; + reset-names =3D "ahb"; + cap-sd-highspeed; + max-frequency =3D <150000000>; + no-mmc; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc2: mmc@4022000 { + compatible =3D "allwinner,sun20i-d1-emmc", + "allwinner,sun50i-a100-emmc"; + reg =3D <0x4022000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC2>; + reset-names =3D "ahb"; + cap-mmc-highspeed; + max-frequency =3D <150000000>; + mmc-ddr-1_8v; + mmc-ddr-3_3v; + no-sd; + no-sdio; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + usb_otg: usb@4100000 { + compatible =3D "allwinner,sun20i-d1-musb", + "allwinner,sun8i-a33-musb"; + reg =3D <0x4100000 0x400>; + interrupts =3D ; + interrupt-names =3D "mc"; + clocks =3D <&ccu CLK_BUS_OTG>; + resets =3D <&ccu RST_BUS_OTG>; + extcon =3D <&usbphy 0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + usbphy: phy@4100400 { + compatible =3D "allwinner,sun20i-d1-usb-phy"; + reg =3D <0x4100400 0x100>, + <0x4101800 0x100>, + <0x4200800 0x100>; + reg-names =3D "phy_ctrl", + "pmu0", + "pmu1"; + clocks =3D <&dcxo>, + <&dcxo>; + clock-names =3D "usb0_phy", + "usb1_phy"; + resets =3D <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names =3D "usb0_reset", + "usb1_reset"; + status =3D "disabled"; + #phy-cells =3D <1>; + }; + + ehci0: usb@4101000 { + compatible =3D "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg =3D <0x4101000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets =3D <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci0: usb@4101400 { + compatible =3D "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg =3D <0x4101400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets =3D <&ccu RST_BUS_OHCI0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ehci1: usb@4200000 { + compatible =3D "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg =3D <0x4200000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets =3D <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + phys =3D <&usbphy 1>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci1: usb@4200400 { + compatible =3D "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg =3D <0x4200400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets =3D <&ccu RST_BUS_OHCI1>; + phys =3D <&usbphy 1>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + emac: ethernet@4500000 { + compatible =3D "allwinner,sun20i-d1-emac", + "allwinner,sun50i-a64-emac"; + reg =3D <0x4500000 0x10000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clocks =3D <&ccu CLK_BUS_EMAC>; + clock-names =3D "stmmaceth"; + resets =3D <&ccu RST_BUS_EMAC>; + reset-names =3D "stmmaceth"; + syscon =3D <&syscon>; + status =3D "disabled"; + + mdio: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + display_clocks: clock-controller@5000000 { + compatible =3D "allwinner,sun20i-d1-de2-clk", + "allwinner,sun50i-h5-de2-clk"; + reg =3D <0x5000000 0x10000>; + clocks =3D <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_DE>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + mixer0: mixer@5100000 { + compatible =3D "allwinner,sun20i-d1-de2-mixer-0"; + reg =3D <0x5100000 0x100000>; + clocks =3D <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names =3D "bus", "mod"; + resets =3D <&display_clocks RST_MIXER0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mixer0_out: port@1 { + reg =3D <1>; + + mixer0_out_tcon_top_mixer0: endpoint { + remote-endpoint =3D <&tcon_top_mixer0_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@5200000 { + compatible =3D "allwinner,sun20i-d1-de2-mixer-1"; + reg =3D <0x5200000 0x100000>; + clocks =3D <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names =3D "bus", "mod"; + resets =3D <&display_clocks RST_MIXER1>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mixer1_out: port@1 { + reg =3D <1>; + + mixer1_out_tcon_top_mixer1: endpoint { + remote-endpoint =3D <&tcon_top_mixer1_in_mixer1>; + }; + }; + }; + }; + + dsi: dsi@5450000 { + compatible =3D "allwinner,sun20i-d1-mipi-dsi", + "allwinner,sun50i-a100-mipi-dsi"; + reg =3D <0x5450000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_MIPI_DSI>, + <&tcon_top CLK_TCON_TOP_DSI>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_MIPI_DSI>; + phys =3D <&dphy>; + phy-names =3D "dphy"; + status =3D "disabled"; + + port { + dsi_in_tcon_lcd0: endpoint { + remote-endpoint =3D <&tcon_lcd0_out_dsi>; + }; + }; + }; + + dphy: phy@5451000 { + compatible =3D "allwinner,sun20i-d1-mipi-dphy", + "allwinner,sun50i-a100-mipi-dphy"; + reg =3D <0x5451000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_MIPI_DSI>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_MIPI_DSI>; + #phy-cells =3D <0>; + }; + + tcon_top: tcon-top@5460000 { + compatible =3D "allwinner,sun20i-d1-tcon-top"; + reg =3D <0x5460000 0x1000>; + clocks =3D <&ccu CLK_BUS_DPSS_TOP>, + <&ccu CLK_TCON_TV>, + <&ccu CLK_TVE>, + <&ccu CLK_TCON_LCD0>; + clock-names =3D "bus", "tcon-tv0", "tve0", "dsi"; + clock-output-names =3D "tcon-top-tv0", "tcon-top-dsi"; + resets =3D <&ccu RST_BUS_DPSS_TOP>; + #clock-cells =3D <1>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer0_in: port@0 { + reg =3D <0>; + + tcon_top_mixer0_in_mixer0: endpoint { + remote-endpoint =3D <&mixer0_out_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer0_out: port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&tcon_lcd0_in_tcon_top_mixer0>; + }; + + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { + reg =3D <2>; + remote-endpoint =3D <&tcon_tv0_in_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer1_in: port@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer1_in_mixer1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&mixer1_out_tcon_top_mixer1>; + }; + }; + + tcon_top_mixer1_out: port@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&tcon_lcd0_in_tcon_top_mixer1>; + }; + + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { + reg =3D <2>; + remote-endpoint =3D <&tcon_tv0_in_tcon_top_mixer1>; + }; + }; + + tcon_top_hdmi_in: port@4 { + reg =3D <4>; + + tcon_top_hdmi_in_tcon_tv0: endpoint { + remote-endpoint =3D <&tcon_tv0_out_tcon_top_hdmi>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg =3D <5>; + }; + }; + }; + + tcon_lcd0: lcd-controller@5461000 { + compatible =3D "allwinner,sun20i-d1-tcon-lcd"; + reg =3D <0x5461000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_TCON_LCD0>, + <&ccu CLK_TCON_LCD0>; + clock-names =3D "ahb", "tcon-ch0"; + clock-output-names =3D "tcon-pixel-clock"; + resets =3D <&ccu RST_BUS_TCON_LCD0>, + <&ccu RST_BUS_LVDS0>; + reset-names =3D "lcd", "lvds"; + #clock-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_lcd0_in: port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&tcon_top_mixer0_out_tcon_lcd0>; + }; + + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&tcon_top_mixer1_out_tcon_lcd0>; + }; + }; + + tcon_lcd0_out: port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_lcd0_out_dsi: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&dsi_in_tcon_lcd0>; + }; + }; + }; + }; + + tcon_tv0: lcd-controller@5470000 { + compatible =3D "allwinner,sun20i-d1-tcon-tv"; + reg =3D <0x5470000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_TCON_TV>, + <&tcon_top CLK_TCON_TOP_TV0>; + clock-names =3D "ahb", "tcon-ch1"; + resets =3D <&ccu RST_BUS_TCON_TV>; + reset-names =3D "lcd"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_tv0_in: port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_tv0_in_tcon_top_mixer0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&tcon_top_mixer0_out_tcon_tv0>; + }; + + tcon_tv0_in_tcon_top_mixer1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&tcon_top_mixer1_out_tcon_tv0>; + }; + }; + + tcon_tv0_out: port@1 { + reg =3D <1>; + + tcon_tv0_out_tcon_top_hdmi: endpoint { + remote-endpoint =3D <&tcon_top_hdmi_in_tcon_tv0>; + }; + }; + }; + }; + + r_ccu: clock-controller@7010000 { + compatible =3D "allwinner,sun20i-d1-r-ccu"; + reg =3D <0x7010000 0x400>; + clocks =3D <&dcxo>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_PERIPH0_DIV3>; + clock-names =3D "hosc", "losc", "iosc", "pll-periph"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + rtc: rtc@7090000 { + compatible =3D "allwinner,sun20i-d1-rtc", + "allwinner,sun50i-r329-rtc"; + reg =3D <0x7090000 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_BUS_R_RTC>, + <&dcxo>, + <&r_ccu CLK_R_AHB>; + clock-names =3D "bus", "hosc", "ahb"; + #clock-cells =3D <1>; + }; + }; +}; --=20 2.37.4 From nobody Sun Dec 22 17:55:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 362A8C61D9D for ; Thu, 26 Jan 2023 04:58:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236013AbjAZE6I (ORCPT ); Wed, 25 Jan 2023 23:58:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234668AbjAZE5s (ORCPT ); Wed, 25 Jan 2023 23:57:48 -0500 Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B5651BD8; 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Wed, 25 Jan 2023 23:57:43 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev Cc: linux-riscv@lists.infradead.org, Heiko Stuebner , Palmer Dabbelt , Conor Dooley , Jisheng Zhang , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andre Przywara , Rob Herring , linux-arm-kernel@lists.infradead.org, Samuel Holland , Palmer Dabbelt , Guo Ren Subject: [PATCH v5 05/11] riscv: dts: allwinner: Add MangoPi MQ devicetree Date: Wed, 25 Jan 2023 22:57:32 -0600 Message-Id: <20230126045738.47903-6-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126045738.47903-1-samuel@sholland.org> References: <20230126045738.47903-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The MangoPi MQ is a tiny SBC built around the Allwinner D1s. Its onboard peripherals include two USB Type-C ports (1 device, 1 host) and RTL8189FTV WLAN. A MangoPi MQ-R variant of the board also exists. The MQ-R has a different form factor, but the onboard peripherals are the same. Most D1 and D1s boards use a similar power tree, with the 1.8V rail powered by the SoC's internal LDOA, analog domains powered by ALDO, and the rest of the board powered by always-on fixed regulators. To avoid duplication, factor out the regulator information that is common across boards. The board also exposes GPIO Port E via a FPC connector, which can support either a camera or an RMII Ethernet PHY. The additional regulators supply that connector. Acked-by: Jernej Skrabec Acked-by: Palmer Dabbelt Reviewed-by: Guo Ren Signed-off-by: Samuel Holland Acked-by: Conor Dooley --- Changes in v5: - Drop the configuration for LDOA and LDOB Changes in v3: - Drop mmc aliases - Change LED_FUNCTION_BACKLIGHT to LED_FUNCTION_STATUS (the backlight regulator is disconnected by default, so this is a standalone LED) Changes in v2: - New patch for v2 arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/allwinner/Makefile | 2 + .../allwinner/sun20i-common-regulators.dtsi | 28 ++++ .../dts/allwinner/sun20i-d1s-mangopi-mq.dts | 128 ++++++++++++++++++ 4 files changed, 159 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/Makefile create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-common-regulators.= dtsi create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 0c97d673b775..f0d9f89054f8 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +subdir-y +=3D allwinner subdir-y +=3D sifive subdir-y +=3D starfive subdir-y +=3D canaan diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/a= llwinner/Makefile new file mode 100644 index 000000000000..2f2792594f7d --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1s-mangopi-mq.dtb diff --git a/arch/riscv/boot/dts/allwinner/sun20i-common-regulators.dtsi b/= arch/riscv/boot/dts/allwinner/sun20i-common-regulators.dtsi new file mode 100644 index 000000000000..9b03fca2444c --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-common-regulators.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +/ { + reg_vcc: vcc { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + reg_vcc_3v3: vcc-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <®_vcc>; + }; +}; + +&pio { + vcc-pb-supply =3D <®_vcc_3v3>; + vcc-pc-supply =3D <®_vcc_3v3>; + vcc-pd-supply =3D <®_vcc_3v3>; + vcc-pe-supply =3D <®_vcc_3v3>; + vcc-pf-supply =3D <®_vcc_3v3>; + vcc-pg-supply =3D <®_vcc_3v3>; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dts b/arch= /riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dts new file mode 100644 index 000000000000..e6d924f671fd --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +#include +#include + +/dts-v1/; + +#include "sun20i-d1s.dtsi" +#include "sun20i-common-regulators.dtsi" + +/ { + model =3D "MangoPi MQ"; + compatible =3D "widora,mangopi-mq", "allwinner,sun20i-d1s"; + + aliases { + ethernet0 =3D &rtl8189ftv; + serial3 =3D &uart3; + }; + + chosen { + stdout-path =3D "serial3:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */ + }; + }; + + reg_avdd2v8: avdd2v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "avdd2v8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <®_vcc_3v3>; + }; + + reg_dvdd: dvdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "dvdd"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <®_vcc_3v3>; + }; + + reg_vcc_core: vcc-core { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-core"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + vin-supply =3D <®_vcc>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&cpu0 { + cpu-supply =3D <®_vcc_core>; +}; + +&dcxo { + clock-frequency =3D <24000000>; +}; + +&ehci1 { + status =3D "okay"; +}; + +&mmc0 { + bus-width =3D <4>; + cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + disable-wp; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + rtl8189ftv: wifi@1 { + reg =3D <1>; + interrupt-parent =3D <&pio>; + interrupts =3D <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */ + interrupt-names =3D "host-wake"; + }; +}; + +&ohci1 { + status =3D "okay"; +}; + +&pio { + vcc-pe-supply =3D <®_avdd2v8>; +}; + +&uart3 { + pinctrl-0 =3D <&uart3_pb_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&usb_otg { + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usbphy { + usb1_vbus-supply =3D <®_vcc>; + status =3D "okay"; +}; --=20 2.37.4 From nobody Sun Dec 22 17:55:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3920C54E94 for ; Thu, 26 Jan 2023 04:58:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236037AbjAZE6N (ORCPT ); Wed, 25 Jan 2023 23:58:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235298AbjAZE5t (ORCPT ); Wed, 25 Jan 2023 23:57:49 -0500 Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E3B84C25; Wed, 25 Jan 2023 20:57:46 -0800 (PST) Received: from compute6.internal (compute6.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id E62985C01A4; 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Wed, 25 Jan 2023 23:57:44 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev Cc: linux-riscv@lists.infradead.org, Heiko Stuebner , Palmer Dabbelt , Conor Dooley , Jisheng Zhang , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andre Przywara , Rob Herring , linux-arm-kernel@lists.infradead.org, Samuel Holland , Palmer Dabbelt , Guo Ren , Conor Dooley Subject: [PATCH v5 06/11] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree Date: Wed, 25 Jan 2023 22:57:33 -0600 Message-Id: <20230126045738.47903-7-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126045738.47903-1-samuel@sholland.org> References: <20230126045738.47903-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" "D1 Nezha" is Allwinner's first-party development board for the D1 SoC. It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio, HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports, plus low-speed I/O from the SoC and a GPIO expander chip. Acked-by: Jernej Skrabec Acked-by: Palmer Dabbelt Reviewed-by: Guo Ren Reviewed-by: Heiko Stuebner Tested-by: Conor Dooley Tested-by: Heiko Stuebner Signed-off-by: Samuel Holland Acked-by: Conor Dooley --- (no changes since v3) Changes in v3: - Drop mmc alias Changes in v2: - Common regulators moved to MangoPi MQ patch, removed analog LDOs - Removed LRADC (depends on analog LDOs) - Added XR829 host-wake interrupt arch/riscv/boot/dts/allwinner/Makefile | 1 + .../boot/dts/allwinner/sun20i-d1-nezha.dts | 166 ++++++++++++++++++ 2 files changed, 167 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/a= llwinner/Makefile index 2f2792594f7d..277e59d1c907 100644 --- a/arch/riscv/boot/dts/allwinner/Makefile +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-nezha.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1s-mangopi-mq.dtb diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv= /boot/dts/allwinner/sun20i-d1-nezha.dts new file mode 100644 index 000000000000..a0769185be97 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +#include +#include + +/dts-v1/; + +#include "sun20i-d1.dtsi" +#include "sun20i-common-regulators.dtsi" + +/ { + model =3D "Allwinner D1 Nezha"; + compatible =3D "allwinner,d1-nezha", "allwinner,sun20i-d1"; + + aliases { + ethernet0 =3D &emac; + ethernet1 =3D &xr829; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + reg_usbvbus: usbvbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usbvbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ + enable-active-high; + vin-supply =3D <®_vcc>; + }; + + /* + * This regulator is PWM-controlled, but the PWM controller is not + * yet supported, so fix the regulator to its default voltage. + */ + reg_vdd_cpu: vdd-cpu { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd-cpu"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <®_vcc>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&cpu0 { + cpu-supply =3D <®_vdd_cpu>; +}; + +&dcxo { + clock-frequency =3D <24000000>; +}; + +&ehci0 { + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&emac { + pinctrl-0 =3D <&rgmii_pe_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&ext_rgmii_phy>; + phy-mode =3D "rgmii-id"; + phy-supply =3D <®_vcc_3v3>; + status =3D "okay"; +}; + +&i2c2 { + pinctrl-0 =3D <&i2c2_pb0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + pcf8574a: gpio@38 { + compatible =3D "nxp,pcf8574a"; + reg =3D <0x38>; + interrupt-parent =3D <&pio>; + interrupts =3D <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */ + interrupt-controller; + gpio-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + }; +}; + +&mmc0 { + bus-width =3D <4>; + cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + disable-wp; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + xr829: wifi@1 { + reg =3D <1>; + interrupt-parent =3D <&pio>; + interrupts =3D <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */ + interrupt-names =3D "host-wake"; + }; +}; + +&ohci0 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pb8_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-0 =3D <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + /* XR829 bluetooth is connected here */ +}; + +&usb_otg { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&usbphy { + usb0_id_det-gpios =3D <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */ + usb0_vbus_det-gpios =3D <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + usb0_vbus-supply =3D <®_usbvbus>; + usb1_vbus-supply =3D <®_vcc>; + status =3D "okay"; +}; --=20 2.37.4 From nobody Sun Dec 22 17:55:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65274C05027 for ; Thu, 26 Jan 2023 04:58:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236086AbjAZE6P (ORCPT ); Wed, 25 Jan 2023 23:58:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235602AbjAZE5y (ORCPT ); Wed, 25 Jan 2023 23:57:54 -0500 Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99F8E61B9; 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Wed, 25 Jan 2023 23:57:46 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev Cc: linux-riscv@lists.infradead.org, Heiko Stuebner , Palmer Dabbelt , Conor Dooley , Jisheng Zhang , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andre Przywara , Rob Herring , linux-arm-kernel@lists.infradead.org, Samuel Holland , Palmer Dabbelt Subject: [PATCH v5 07/11] riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees Date: Wed, 25 Jan 2023 22:57:34 -0600 Message-Id: <20230126045738.47903-8-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126045738.47903-1-samuel@sholland.org> References: <20230126045738.47903-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Sipeed manufactures a "Lichee RV" system-on-module, which provides a minimal working system on its own, as well as a few carrier boards. The "Dock" board provides audio, USB, and WiFi. The "86 Panel" additionally provides 100M Ethernet and a built-in display panel. The 86 Panel repurposes the USB ID and VBUS detection GPIOs for its RGB panel interface, since the USB OTG port is inaccessible inside the case. Co-developed-by: Jisheng Zhang Signed-off-by: Jisheng Zhang Acked-by: Jernej Skrabec Acked-by: Palmer Dabbelt Signed-off-by: Samuel Holland Acked-by: Conor Dooley --- (no changes since v3) Changes in v3: - Fix `make W=3D1 dtbs` warnings (missing reg properties) - Drop mmc alias Changes in v2: - Added DMIC sound card to Lichee RV dock and Lichee RV 86 Panel - Removed LRADC (depends on analog LDOs) arch/riscv/boot/dts/allwinner/Makefile | 4 + .../sun20i-d1-lichee-rv-86-panel-480p.dts | 29 +++++ .../sun20i-d1-lichee-rv-86-panel-720p.dts | 10 ++ .../sun20i-d1-lichee-rv-86-panel.dtsi | 119 ++++++++++++++++++ .../allwinner/sun20i-d1-lichee-rv-dock.dts | 97 ++++++++++++++ .../dts/allwinner/sun20i-d1-lichee-rv.dts | 87 +++++++++++++ 6 files changed, 346 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-pa= nel-480p.dts create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-pa= nel-720p.dts create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-pa= nel.dtsi create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.= dts create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/a= llwinner/Makefile index 277e59d1c907..f1c70b9dc9bf 100644 --- a/arch/riscv/boot/dts/allwinner/Makefile +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -1,3 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-480p.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-720p.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-dock.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-nezha.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1s-mangopi-mq.dtb diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480= p.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts new file mode 100644 index 000000000000..4df8ffb71561 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +#include "sun20i-d1-lichee-rv-86-panel.dtsi" + +/ { + model =3D "Sipeed Lichee RV 86 Panel (480p)"; + compatible =3D "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv", + "allwinner,sun20i-d1"; +}; + +&i2c2 { + pinctrl-0 =3D <&i2c2_pb0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + touchscreen@48 { + compatible =3D "focaltech,ft6236"; + reg =3D <0x48>; + interrupt-parent =3D <&pio>; + interrupts =3D <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */ + iovcc-supply =3D <®_vcc_3v3>; + reset-gpios =3D <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */ + touchscreen-size-x =3D <480>; + touchscreen-size-y =3D <480>; + vcc-supply =3D <®_vcc_3v3>; + wakeup-source; + }; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720= p.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts new file mode 100644 index 000000000000..1874fc05359f --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +#include "sun20i-d1-lichee-rv-86-panel.dtsi" + +/ { + model =3D "Sipeed Lichee RV 86 Panel (720p)"; + compatible =3D "sipeed,lichee-rv-86-panel-720p", "sipeed,lichee-rv", + "allwinner,sun20i-d1"; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dts= i b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi new file mode 100644 index 000000000000..6cc7dd0c1ae2 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +#include "sun20i-d1-lichee-rv.dts" + +/ { + aliases { + ethernet0 =3D &emac; + ethernet1 =3D &xr829; + }; + + dmic_codec: dmic-codec { + compatible =3D "dmic-codec"; + num-channels =3D <2>; + #sound-dai-cells =3D <0>; + }; + + dmic-sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "DMIC"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + simple-audio-card,dai-link@0 { + reg =3D <0>; + format =3D "pdm"; + frame-master =3D <&link0_cpu>; + bitclock-master =3D <&link0_cpu>; + + link0_cpu: cpu { + sound-dai =3D <&dmic>; + }; + + link0_codec: codec { + sound-dai =3D <&dmic_codec>; + }; + }; + }; + + /* PC1 is repurposed as BT_WAKE_AP */ + /delete-node/ leds; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&ccu CLK_FANOUT1>; + clock-names =3D "ext_clock"; + reset-gpios =3D <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + assigned-clocks =3D <&ccu CLK_FANOUT1>; + assigned-clock-rates =3D <32768>; + pinctrl-0 =3D <&clk_pg11_pin>; + pinctrl-names =3D "default"; + }; +}; + +&dmic { + pinctrl-0 =3D <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&emac { + pinctrl-0 =3D <&rmii_pe_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&ext_rmii_phy>; + phy-mode =3D "rmii"; + phy-supply =3D <®_vcc_3v3>; + status =3D "okay"; +}; + +&mdio { + ext_rmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */ + }; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + xr829: wifi@1 { + reg =3D <1>; + }; +}; + +&ohci1 { + status =3D "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-0 =3D <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + /* XR829 bluetooth is connected here */ +}; + +&usb_otg { + status =3D "disabled"; +}; + +&usbphy { + /* PD20 and PD21 are repurposed for the LCD panel */ + /delete-property/ usb0_id_det-gpios; + /delete-property/ usb0_vbus_det-gpios; + usb1_vbus-supply =3D <®_vcc>; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts b/a= rch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts new file mode 100644 index 000000000000..52b91e1affed --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Jisheng Zhang +// Copyright (C) 2022 Samuel Holland + +#include + +#include "sun20i-d1-lichee-rv.dts" + +/ { + model =3D "Sipeed Lichee RV Dock"; + compatible =3D "sipeed,lichee-rv-dock", "sipeed,lichee-rv", + "allwinner,sun20i-d1"; + + aliases { + ethernet1 =3D &rtl8723ds; + }; + + dmic_codec: dmic-codec { + compatible =3D "dmic-codec"; + num-channels =3D <2>; + #sound-dai-cells =3D <0>; + }; + + dmic-sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "DMIC"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + simple-audio-card,dai-link@0 { + reg =3D <0>; + format =3D "pdm"; + frame-master =3D <&link0_cpu>; + bitclock-master =3D <&link0_cpu>; + + link0_cpu: cpu { + sound-dai =3D <&dmic>; + }; + + link0_codec: codec { + sound-dai =3D <&dmic_codec>; + }; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&dmic { + pinctrl-0 =3D <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + rtl8723ds: wifi@1 { + reg =3D <1>; + }; +}; + +&ohci1 { + status =3D "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-0 =3D <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + bluetooth { + compatible =3D "realtek,rtl8723ds-bt"; + device-wake-gpios =3D <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG16 */ + enable-gpios =3D <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */ + host-wake-gpios =3D <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */ + }; +}; + +&usbphy { + usb1_vbus-supply =3D <®_vcc>; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts b/arch/r= iscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts new file mode 100644 index 000000000000..d60a0562a8b1 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Jisheng Zhang +// Copyright (C) 2022 Samuel Holland + +#include +#include + +/dts-v1/; + +#include "sun20i-d1.dtsi" +#include "sun20i-common-regulators.dtsi" + +/ { + model =3D "Sipeed Lichee RV"; + compatible =3D "sipeed,lichee-rv", "allwinner,sun20i-d1"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */ + }; + }; + + reg_vdd_cpu: vdd-cpu { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd-cpu"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + vin-supply =3D <®_vcc>; + }; +}; + +&cpu0 { + cpu-supply =3D <®_vdd_cpu>; +}; + +&dcxo { + clock-frequency =3D <24000000>; +}; + +&ehci0 { + status =3D "okay"; +}; + +&mmc0 { + broken-cd; + bus-width =3D <4>; + disable-wp; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&ohci0 { + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pb8_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&usb_otg { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&usbphy { + usb0_id_det-gpios =3D <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */ + usb0_vbus_det-gpios =3D <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + usb0_vbus-supply =3D <®_vcc>; + status =3D "okay"; +}; --=20 2.37.4 From nobody Sun Dec 22 17:55:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F7D9C05027 for ; Thu, 26 Jan 2023 04:58:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236146AbjAZE6W (ORCPT ); Wed, 25 Jan 2023 23:58:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235664AbjAZE5y (ORCPT ); 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Wed, 25 Jan 2023 23:57:47 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev Cc: linux-riscv@lists.infradead.org, Heiko Stuebner , Palmer Dabbelt , Conor Dooley , Jisheng Zhang , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andre Przywara , Rob Herring , linux-arm-kernel@lists.infradead.org, Samuel Holland , Palmer Dabbelt , Guo Ren Subject: [PATCH v5 08/11] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree Date: Wed, 25 Jan 2023 22:57:35 -0600 Message-Id: <20230126045738.47903-9-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126045738.47903-1-samuel@sholland.org> References: <20230126045738.47903-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The MangoPi MQ Pro is a tiny SBC with a layout compatible to the Raspberry Pi Zero. It includes the Allwinner D1 SoC, 512M or 1G of DDR3, and an RTL8723DS-based WiFi/Bluetooth module. The board also exposes GPIO Port E via a connector on the end of the board, which can support either a camera or an RMII Ethernet PHY. The additional regulators supply that connector. Acked-by: Jernej Skrabec Acked-by: Palmer Dabbelt Reviewed-by: Guo Ren Signed-off-by: Samuel Holland Acked-by: Conor Dooley --- (no changes since v3) Changes in v3: - Drop mmc alias - Change LED_FUNCTION_BACKLIGHT to LED_FUNCTION_STATUS (the backlight regulator is disconnected by default, so this is a standalone LED) Changes in v2: - Added LED (GPIO shared between onboard LED and backlight regulator) arch/riscv/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun20i-d1-mangopi-mq-pro.dts | 142 ++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.= dts diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/a= llwinner/Makefile index f1c70b9dc9bf..2ed586fafaea 100644 --- a/arch/riscv/boot/dts/allwinner/Makefile +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-= 480p.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-720p.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-dock.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-mangopi-mq-pro.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-nezha.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1s-mangopi-mq.dtb diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts b/a= rch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts new file mode 100644 index 000000000000..f2e07043afb3 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +#include +#include + +/dts-v1/; + +#include "sun20i-d1.dtsi" +#include "sun20i-common-regulators.dtsi" + +/ { + model =3D "MangoPi MQ Pro"; + compatible =3D "widora,mangopi-mq-pro", "allwinner,sun20i-d1"; + + aliases { + ethernet0 =3D &rtl8723ds; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */ + }; + }; + + reg_avdd2v8: avdd2v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "avdd2v8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <®_vcc_3v3>; + }; + + reg_dvdd: dvdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "dvdd"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <®_vcc_3v3>; + }; + + reg_vdd_cpu: vdd-cpu { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd-cpu"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <®_vcc>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */ + }; +}; + +&cpu0 { + cpu-supply =3D <®_vdd_cpu>; +}; + +&dcxo { + clock-frequency =3D <24000000>; +}; + +&ehci1 { + status =3D "okay"; +}; + +&mmc0 { + bus-width =3D <4>; + cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + disable-wp; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + rtl8723ds: wifi@1 { + reg =3D <1>; + interrupt-parent =3D <&pio>; + interrupts =3D <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */ + interrupt-names =3D "host-wake"; + }; +}; + +&ohci1 { + status =3D "okay"; +}; + +&pio { + vcc-pe-supply =3D <®_avdd2v8>; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pb8_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-0 =3D <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + bluetooth { + compatible =3D "realtek,rtl8723ds-bt"; + device-wake-gpios =3D <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */ + enable-gpios =3D <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */ + host-wake-gpios =3D <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */ + }; +}; + +&usb_otg { + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usbphy { + usb1_vbus-supply =3D <®_vcc>; + status =3D "okay"; +}; --=20 2.37.4 From nobody Sun Dec 22 17:55:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07DE1C05027 for ; Thu, 26 Jan 2023 04:58:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236115AbjAZE6T (ORCPT ); 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Wed, 25 Jan 2023 23:57:48 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev Cc: linux-riscv@lists.infradead.org, Heiko Stuebner , Palmer Dabbelt , Conor Dooley , Jisheng Zhang , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andre Przywara , Rob Herring , linux-arm-kernel@lists.infradead.org, Samuel Holland , Palmer Dabbelt , Guo Ren Subject: [PATCH v5 09/11] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree Date: Wed, 25 Jan 2023 22:57:36 -0600 Message-Id: <20230126045738.47903-10-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126045738.47903-1-samuel@sholland.org> References: <20230126045738.47903-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The 100ask Dongshan Nezha STU is a system-on-module that can be used standalone or with a carrier board. The SoM provides gigabit Ethernet, HDMI, a USB peripheral port, and WiFi/Bluetooth via an RTL8723DS chip. The "DIY" carrier board exposes almost every pin from the D1 SoC to 0.1" headers, but contains no digital circuitry, so it does not have its own devicetree. Acked-by: Jernej Skrabec Acked-by: Palmer Dabbelt Reviewed-by: Guo Ren Signed-off-by: Samuel Holland Acked-by: Conor Dooley --- (no changes since v3) Changes in v3: - Drop mmc alias arch/riscv/boot/dts/allwinner/Makefile | 1 + .../sun20i-d1-dongshan-nezha-stu.dts | 117 ++++++++++++++++++ 2 files changed, 118 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-= stu.dts diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/a= llwinner/Makefile index 2ed586fafaea..87f70b1af6b4 100644 --- a/arch/riscv/boot/dts/allwinner/Makefile +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-dongshan-nezha-stu.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-480p.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-720p.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-dock.dtb diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts= b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts new file mode 100644 index 000000000000..8785de3c9224 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +#include +#include + +/dts-v1/; + +#include "sun20i-d1.dtsi" +#include "sun20i-common-regulators.dtsi" + +/ { + model =3D "Dongshan Nezha STU"; + compatible =3D "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1"; + + aliases { + ethernet0 =3D &emac; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */ + }; + }; + + reg_usbvbus: usbvbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usbvbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ + enable-active-high; + vin-supply =3D <®_vcc>; + }; + + /* + * This regulator is PWM-controlled, but the PWM controller is not + * yet supported, so fix the regulator to its default voltage. + */ + reg_vdd_cpu: vdd-cpu { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd-cpu"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <®_vcc>; + }; +}; + +&cpu0 { + cpu-supply =3D <®_vdd_cpu>; +}; + +&dcxo { + clock-frequency =3D <24000000>; +}; + +&ehci0 { + status =3D "okay"; +}; + +&emac { + pinctrl-0 =3D <&rgmii_pe_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&ext_rgmii_phy>; + phy-mode =3D "rgmii-id"; + phy-supply =3D <®_vcc_3v3>; + status =3D "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + }; +}; + +&mmc0 { + broken-cd; + bus-width =3D <4>; + disable-wp; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&ohci0 { + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pb8_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&usb_otg { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&usbphy { + usb0_id_det-gpios =3D <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */ + usb0_vbus_det-gpios =3D <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + usb0_vbus-supply =3D <®_usbvbus>; + status =3D "okay"; +}; --=20 2.37.4 From nobody Sun Dec 22 17:55:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A290AC61D97 for ; Thu, 26 Jan 2023 04:58:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236179AbjAZE60 (ORCPT ); Wed, 25 Jan 2023 23:58:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235506AbjAZE55 (ORCPT ); Wed, 25 Jan 2023 23:57:57 -0500 Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C536CA16; Wed, 25 Jan 2023 20:57:51 -0800 (PST) Received: from compute6.internal (compute6.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id BC2AD5C01B6; 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Wed, 25 Jan 2023 23:57:49 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev Cc: linux-riscv@lists.infradead.org, Heiko Stuebner , Palmer Dabbelt , Conor Dooley , Jisheng Zhang , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andre Przywara , Rob Herring , linux-arm-kernel@lists.infradead.org, Samuel Holland , Conor Dooley , Palmer Dabbelt , Guo Ren Subject: [PATCH v5 10/11] riscv: Add the Allwinner SoC family Kconfig option Date: Wed, 25 Jan 2023 22:57:37 -0600 Message-Id: <20230126045738.47903-11-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126045738.47903-1-samuel@sholland.org> References: <20230126045738.47903-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allwinner manufactures the sunxi family of application processors. This includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8 SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs. The first SoC in the sun20i series is D1, containing a single T-HEAD C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM. Most peripherals are shared across the entire chip family. In fact, the ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible with the D1s. This means many existing device drivers can be reused. To facilitate this reuse, name the symbol ARCH_SUNXI, since that is what the existing drivers have as their dependency. Acked-by: Conor Dooley Acked-by: Palmer Dabbelt Reviewed-by: Guo Ren Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Signed-off-by: Samuel Holland --- (no changes since v4) Changes in v4: - Drop the now-redundant 'select SIFIVE_PLIC' - Rebase on v6.2-rc1 + soc2arch-immutable Changes in v3: - ARCH_SUNXI depends on MMU && !XIP_KERNEL Changes in v2: - Sort Kconfig as if we had done s/SOC_/ARCH_/ for future-proofing arch/riscv/Kconfig.socs | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 659140309157..1cf69f958f10 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -32,6 +32,15 @@ config SOC_STARFIVE help This enables support for StarFive SoC platform hardware. =20 +config ARCH_SUNXI + bool "Allwinner sun20i SoCs" + depends on MMU && !XIP_KERNEL + select ERRATA_THEAD + select SUN4I_TIMER + help + This enables support for Allwinner sun20i platform hardware, + including boards based on the D1 and D1s SoCs. + config ARCH_VIRT def_bool SOC_VIRT =20 --=20 2.37.4 From nobody Sun Dec 22 17:55:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 085C6C61D97 for ; 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Wed, 25 Jan 2023 23:57:51 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev Cc: linux-riscv@lists.infradead.org, Heiko Stuebner , Palmer Dabbelt , Conor Dooley , Jisheng Zhang , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andre Przywara , Rob Herring , linux-arm-kernel@lists.infradead.org, Samuel Holland , Conor Dooley , Palmer Dabbelt , Guo Ren , Heiko Stuebner Subject: [PATCH v5 11/11] riscv: defconfig: Enable the Allwinner D1 platform and drivers Date: Wed, 25 Jan 2023 22:57:38 -0600 Message-Id: <20230126045738.47903-12-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126045738.47903-1-samuel@sholland.org> References: <20230126045738.47903-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that several D1-based boards are supported, enable the platform in our defconfig. Build in the drivers which are necessary to boot, such as the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash), and watchdog (which may be left enabled by the bootloader). Other common onboard peripherals are enabled as modules. Acked-by: Conor Dooley Acked-by: Palmer Dabbelt Reviewed-by: Guo Ren Reviewed-by: Heiko Stuebner Signed-off-by: Samuel Holland --- (no changes since v4) Changes in v4: - Rebase on v6.2-rc1 + soc2arch-immutable arch/riscv/configs/defconfig | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 128dcf4c0814..d98d6e90b2b8 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -29,6 +29,7 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=3Dy CONFIG_ARCH_RENESAS=3Dy CONFIG_SOC_SIFIVE=3Dy CONFIG_SOC_STARFIVE=3Dy +CONFIG_ARCH_SUNXI=3Dy CONFIG_SOC_VIRT=3Dy CONFIG_SMP=3Dy CONFIG_HOTPLUG_CPU=3Dy @@ -120,8 +121,10 @@ CONFIG_VIRTIO_NET=3Dy CONFIG_MACB=3Dy CONFIG_E1000E=3Dy CONFIG_R8169=3Dy +CONFIG_STMMAC_ETH=3Dm CONFIG_MICROSEMI_PHY=3Dy CONFIG_INPUT_MOUSEDEV=3Dy +CONFIG_KEYBOARD_SUN4I_LRADC=3Dm CONFIG_SERIAL_8250=3Dy CONFIG_SERIAL_8250_CONSOLE=3Dy CONFIG_SERIAL_8250_DW=3Dy @@ -130,14 +133,20 @@ CONFIG_SERIAL_SH_SCI=3Dy CONFIG_VIRTIO_CONSOLE=3Dy CONFIG_HW_RANDOM=3Dy CONFIG_HW_RANDOM_VIRTIO=3Dy +CONFIG_I2C_MV64XXX=3Dm CONFIG_SPI=3Dy CONFIG_SPI_SIFIVE=3Dy +CONFIG_SPI_SUN6I=3Dy # CONFIG_PTP_1588_CLOCK is not set -CONFIG_GPIOLIB=3Dy CONFIG_GPIO_SIFIVE=3Dy +CONFIG_WATCHDOG=3Dy +CONFIG_SUNXI_WATCHDOG=3Dy +CONFIG_REGULATOR=3Dy +CONFIG_REGULATOR_FIXED_VOLTAGE=3Dy CONFIG_DRM=3Dm CONFIG_DRM_RADEON=3Dm CONFIG_DRM_NOUVEAU=3Dm +CONFIG_DRM_SUN4I=3Dm CONFIG_DRM_VIRTIO_GPU=3Dm CONFIG_FB=3Dy CONFIG_FRAMEBUFFER_CONSOLE=3Dy @@ -150,21 +159,32 @@ CONFIG_USB_OHCI_HCD=3Dy CONFIG_USB_OHCI_HCD_PLATFORM=3Dy CONFIG_USB_STORAGE=3Dy CONFIG_USB_UAS=3Dy +CONFIG_USB_MUSB_HDRC=3Dm +CONFIG_USB_MUSB_SUNXI=3Dm +CONFIG_NOP_USB_XCEIV=3Dm CONFIG_MMC=3Dy CONFIG_MMC_SDHCI=3Dy CONFIG_MMC_SDHCI_PLTFM=3Dy CONFIG_MMC_SDHCI_CADENCE=3Dy CONFIG_MMC_SPI=3Dy +CONFIG_MMC_SUNXI=3Dy CONFIG_RTC_CLASS=3Dy +CONFIG_RTC_DRV_SUN6I=3Dy +CONFIG_DMADEVICES=3Dy +CONFIG_DMA_SUN6I=3Dm CONFIG_VIRTIO_PCI=3Dy CONFIG_VIRTIO_BALLOON=3Dy CONFIG_VIRTIO_INPUT=3Dy CONFIG_VIRTIO_MMIO=3Dy +CONFIG_SUN8I_DE2_CCU=3Dm +CONFIG_SUN50I_IOMMU=3Dy CONFIG_RPMSG_CHAR=3Dy CONFIG_RPMSG_CTRL=3Dy CONFIG_RPMSG_VIRTIO=3Dy CONFIG_ARCH_R9A07G043=3Dy +CONFIG_PHY_SUN4I_USB=3Dm CONFIG_LIBNVDIMM=3Dy +CONFIG_NVMEM_SUNXI_SID=3Dy CONFIG_EXT4_FS=3Dy CONFIG_EXT4_FS_POSIX_ACL=3Dy CONFIG_EXT4_FS_SECURITY=3Dy --=20 2.37.4