From nobody Wed Nov 13 07:50:39 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C3E5C27C76 for ; Wed, 25 Jan 2023 14:36:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235741AbjAYOgY (ORCPT ); Wed, 25 Jan 2023 09:36:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235793AbjAYOf5 (ORCPT ); Wed, 25 Jan 2023 09:35:57 -0500 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39B9059275 for ; Wed, 25 Jan 2023 06:35:28 -0800 (PST) Received: by mail-ej1-x631.google.com with SMTP id mp20so48111056ejc.7 for ; Wed, 25 Jan 2023 06:35:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=a+hdoITDtYQdRah2TmgE8D0Rqy5YhdMJSbiS7Eipx1Q=; b=SHnHfos/l3FQGYctapeGDvlA0F6o8EpKc3T3n7XRDf3LRc514rHbW4vVTZa7B29eZu JEkvi6QCtW3hPIOySROOFCgOCG10ePfpee9rEO4JF0BnjHIEEocHyKLSXXwwb0EF55Vw 0TRQF01xNSYOlB2SMxF/wUnjnptfpYnK6i4A5Yf/1gEXveSkL/DiiBYqgZBTb2SzRAny AV1rUFOAv9A1f2r4gq8b/mE58/zaq1A/aym700hzpw+D3Xp7sPRSft/AFq6mejfJvmze 6Erh2ZNmBiEgJQrNIVPQHuRUXnEC/y3wmo4gbgYGcPSRc69LSsQVQnWPE/M73lQg+Wce iEig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a+hdoITDtYQdRah2TmgE8D0Rqy5YhdMJSbiS7Eipx1Q=; b=sl6yHALA8qGph4dfVOKTHGh625DCyxSofTZ1ARrVeARNd3xhMXFAkS/Ce2A0EbzLdj zCpHUp+VjGDUuFpmZ5+yggxr76xsRJddnMeq+gNnrFBCz5ZGzYoBXt3Qy4KmhLX2/18n srxOrRsHW00pHa/wg5E088NoH5IwrPlAUqSaO88ff8Pr0sVSvpa5atu74GAP8GC2HXBq ajpEl7Gg+3+bzuLU0OKi8TrOcQI1gz9SKcdmngg/wpEmT8WgOk2MoHVF/yWFzPd+hbmU F8fHAPxZTv+iBUi7gTTfkRhbDfLWSc8lh3RfuQQgflldzIDegaqw9MAv7N3s8ulpslS8 5ySg== X-Gm-Message-State: AFqh2kp/zZK6YLAdgyr2hUDjPY0KKoQRSZiBxcqF3Ol3v9yhPCuYnl8O kqgFKDy803C2wD741Gy4JDGh7w== X-Google-Smtp-Source: AMrXdXvpnaPN3DIGx28duMmt22RIPa3PVOhbzeBY2JXBj0NVu79klDzsc61FMsPQt6hWnGzA9DIS2Q== X-Received: by 2002:a17:906:f49:b0:864:8c78:e7ff with SMTP id h9-20020a1709060f4900b008648c78e7ffmr28543678ejj.23.1674657310876; Wed, 25 Jan 2023 06:35:10 -0800 (PST) Received: from c64.fritz.box ([81.221.122.240]) by smtp.gmail.com with ESMTPSA id gx2-20020a1709068a4200b0082000f8d871sm2437789ejc.152.2023.01.25.06.35.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 06:35:10 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tglx@linutronix.de, maz@kernel.org, lee@kernel.org, linus.walleij@linaro.org, matthias.bgg@gmail.com, gregkh@linuxfoundation.org, daniel.lezcano@linaro.org, chunfeng.yun@mediatek.com, angelogioacchino.delregno@collabora.com, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, sean.wang@mediatek.com, zhiyong.tao@mediatek.com Subject: [PATCH v9 4/9] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC Date: Wed, 25 Jan 2023 15:34:58 +0100 Message-Id: <20230125143503.1015424-5-bero@baylibre.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230125143503.1015424-1-bero@baylibre.com> References: <20230125143503.1015424-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree bindings for Mediatek MT8365 pinctrl driver. Signed-off-by: Bernhard Rosenkr=C3=A4nzer Reviewed-by: Rob Herring --- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 197 ++++++++++++++++++ 1 file changed, 197 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt83= 65-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctr= l.yaml new file mode 100644 index 0000000000000..4b96884a1afc7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -0,0 +1,197 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8365 Pin Controller + +maintainers: + - Zhiyong Tao + - Bernhard Rosenkr=C3=A4nzer + +description: | + The MediaTek's MT8365 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8365-pinctrl + + reg: + maxItems: 1 + + mediatek,pctl-regmap: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + minItems: 1 + maxItems: 2 + description: | + Should be phandles of the syscfg node. + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the= below + mentioned gpio binding representation for description of particular = cells. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +patternProperties: + "-pins$": + type: object + additionalProperties: false + patternProperties: + "pins$": + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnode representing = the + pinctrl groups available on the machine. Each subnode will list = the + pins it needs, and how they should be configured, with regard to= muxer + configuration, pullups, drive strength, input enable/disable and= input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and = are + defined as macros in -pinfunc.h directly. + + bias-disable: true + + bias-pull-up: + description: | + Besides generic pinconfig options, it can be used as the pul= l up + settings for 2 pull resistors, R0 and R1. User can configure= those + special pins. + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only su= pport + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup= , they + can support 0.125/0.25/0.5/1mA adjustment. If we enable spec= ific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=3D0/E0=3D0, the strength is 0.125mA. + When E1=3D0/E0=3D1, the strength is 0.25mA. + When E1=3D1/E0=3D0, the strength is 0.5mA. + When E1=3D1/E0=3D1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) =3D (0, 0, 0) + 1: (E1, E0, EN) =3D (0, 0, 1) + 2: (E1, E0, EN) =3D (0, 1, 0) + 3: (E1, E0, EN) =3D (0, 1, 1) + 4: (E1, E0, EN) =3D (1, 0, 0) + 5: (E1, E0, EN) =3D (1, 0, 1) + 6: (E1, E0, EN) =3D (1, 1, 0) + 7: (E1, E0, EN) =3D (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described = as below: + 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. + 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. + 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. + 3: (R1, R0) =3D (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described = as below: + 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. + 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. + 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. + 3: (R1, R0) =3D (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,tdsel: + description: | + An integer describing the steps for output level shifter duty + cycle when asserted (high pulse width adjustment). Valid arg= uments + are from 0 to 15. + $ref: /schemas/types.yaml#/definitions/uint32 + + mediatek,rdsel: + description: | + An integer describing the steps for input level shifter duty= cycle + when asserted (high pulse width adjustment). Valid arguments= are + from 0 to 63. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pinmux + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pio: pinctrl@1000b000 { + compatible =3D "mediatek,mt8365-pinctrl"; + reg =3D <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap =3D <&syscfg_pctl>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + + pio-pins { + pins { + pinmux =3D , ; + mediatek,pull-up-adv =3D <3>; + mediatek,drive-strength-adv =3D <00>; + bias-pull-up; + }; + }; + }; + }; --=20 2.39.1