From nobody Thu Nov 14 06:57:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 588A8C27C76 for ; Wed, 25 Jan 2023 14:36:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235846AbjAYOgw (ORCPT ); Wed, 25 Jan 2023 09:36:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235844AbjAYOgK (ORCPT ); Wed, 25 Jan 2023 09:36:10 -0500 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A94E2568A2 for ; Wed, 25 Jan 2023 06:35:40 -0800 (PST) Received: by mail-ej1-x632.google.com with SMTP id kt14so48213513ejc.3 for ; Wed, 25 Jan 2023 06:35:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=tOiRWymI4rd5WlsVYIaIq9NoZeWymaeFEkgKA/Uo35w=; b=YayUVbnlxoaVRKYH90E4Pp6J/ospChaNFYmXvVklwZkydkwFE8AhRwOx7ep9skBU+t HII1j71ESkai6nYl14m4JWkpGawmy7obefyz5JO0tQ4Jq4tyRF36iEoyXrGbMyqkkBm3 fvh9s7TPzNCllVBrxerh/fHn+8sHVLcuGKJTd/6k2fS9xKQ3L894d51bGinlUXskepDj /lw0vca8RxfccearHt0cZHABnlvUKayoOH2ZPCjjb9+stM5aMK7OE3UDoNFfKtaTqw4J TIwGmg2iC6jGA5AVCeYEipM8zfSQt6H4H/1H3jx7FVxkc4sAopTtxmPXztzcPYc9/8vC 4kCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tOiRWymI4rd5WlsVYIaIq9NoZeWymaeFEkgKA/Uo35w=; b=qCWWJKO4k8KDXptJQhq7k2n3IU9Ca5TsxwQaRn874Wy5fzMBEIXp5PY1tmH3w3Lsju +Q/2qr6PglXhiwCOBRqOfz8dE3bNAzQ5YgCDs91hVqQ41o1HOh0MtZtfBsiq5q2wgrIZ 5hC84Lu9Xv6ZdrA6JdLreDIaWe923ZhSXg9duyyspZNHKDVsEe4CaumvBm8p6+vsGX35 cd2m4Pq34s5teMjdpfc74DC+ksiaHXUj4LoRAXYYXkCGZb7GWYGInTPAF9uy6XT76cTF k0sPu5MBXp0+SK2oSnpUFKTz8QgAS8v30q5ALTsmJeEwk3ScQqYySp0F6s+girmdmYAX K5yw== X-Gm-Message-State: AFqh2kozh2n2lPbtlnLHMh3RnZGGKYz139fJGOxwRTo1yOVlDyzu0RdQ l/GO6Tu2rb6wXVGllIaTF04iQw== X-Google-Smtp-Source: AMrXdXt5XZXcE5DsziGClu9GaRZMa9sl+Qa1tF6z/83wXeE5WbUxrmk2cDszz/r7rv3vCcUGkI2Gsg== X-Received: by 2002:a17:906:fb09:b0:859:aca8:fe4d with SMTP id lz9-20020a170906fb0900b00859aca8fe4dmr30524138ejb.46.1674657316956; Wed, 25 Jan 2023 06:35:16 -0800 (PST) Received: from c64.fritz.box ([81.221.122.240]) by smtp.gmail.com with ESMTPSA id gx2-20020a1709068a4200b0082000f8d871sm2437789ejc.152.2023.01.25.06.35.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 06:35:16 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tglx@linutronix.de, maz@kernel.org, lee@kernel.org, linus.walleij@linaro.org, matthias.bgg@gmail.com, gregkh@linuxfoundation.org, daniel.lezcano@linaro.org, chunfeng.yun@mediatek.com, angelogioacchino.delregno@collabora.com, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, sean.wang@mediatek.com, zhiyong.tao@mediatek.com Subject: [PATCH v9 9/9] arm64: dts: mediatek: Initial mt8365-evk support Date: Wed, 25 Jan 2023 15:35:03 +0100 Message-Id: <20230125143503.1015424-10-bero@baylibre.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230125143503.1015424-1-bero@baylibre.com> References: <20230125143503.1015424-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent This adds minimal support for the Mediatek 8365 SOC and the EVK reference board, allowing the board to boot to initramfs with serial port I/O. Signed-off-by: Fabien Parent [bero@baylibre.com: Removed parts depending on drivers that aren't upstream= yet, cleanups, add CPU cache layout, add systimer, fix GIC] Signed-off-by: Bernhard Rosenkr=C3=A4nzer Tested-by: Kevin Hilman Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 168 +++++++++ arch/arm64/boot/dts/mediatek/mt8365.dtsi | 377 ++++++++++++++++++++ 3 files changed, 546 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 813e735c5b96d..d78523c5a7dd6 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -47,4 +47,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-cherry-tomato-r2.= dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-cherry-tomato-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/= dts/mediatek/mt8365-evk.dts new file mode 100644 index 0000000000000..4683704ea2355 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021-2022 BayLibre, SAS. + * Authors: + * Fabien Parent + * Bernhard Rosenkr=C3=A4nzer + */ + +/dts-v1/; + +#include +#include +#include +#include "mt8365.dtsi" + +/ { + model =3D "MediaTek MT8365 Open Platform EVK"; + compatible =3D "mediatek,mt8365-evk", "mediatek,mt8365"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:921600n8"; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio_keys>; + + key-volume-up { + gpios =3D <&pio 24 GPIO_ACTIVE_LOW>; + label =3D "volume_up"; + linux,code =3D ; + wakeup-source; + debounce-interval =3D <15>; + }; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 0 0xc0000000>; + }; + + usb_otg_vbus: regulator-0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "otg_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg =3D <0 0x43000000 0 0x20000>; + }; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg =3D <0 0x43200000 0 0x00c00000>; + }; + }; +}; + +&pio { + gpio_keys: gpio-keys-pins { + pins { + pinmux =3D ; + bias-pull-up; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux =3D , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux =3D , + ; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux =3D , + ; + }; + }; + + usb_pins: usb-pins { + id-pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + usb0-vbus-pins { + pinmux =3D ; + output-high; + }; + + usb1-vbus-pins { + pinmux =3D ; + output-high; + }; + }; + + pwm_pins: pwm-pins { + pins { + pinmux =3D , + ; + }; + }; +}; + +&pwm { + pinctrl-0 =3D <&pwm_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + pinctrl-0 =3D <&uart1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts= /mediatek/mt8365.dtsi new file mode 100644 index 0000000000000..15ac4c1f09661 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) 2018 MediaTek Inc. + * Copyright (C) 2022 BayLibre SAS + * Fabien Parent + * Bernhard Rosenkr=C3=A4nzer + */ +#include +#include +#include +#include + +/ { + compatible =3D "mediatek,mt8365"; + interrupt-parent =3D <&sysirq>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-unified; + }; + }; + + clk26m: oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "clk26m"; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <3>; + interrupt-parent =3D <&gic>; + interrupt-controller; + reg =3D <0 0x0c000000 0 0x10000>, /* GICD */ + <0 0x0c080000 0 0x80000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + + interrupts =3D ; + }; + + topckgen: syscon@10000000 { + compatible =3D "mediatek,mt8365-topckgen", "syscon"; + reg =3D <0 0x10000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + infracfg: syscon@10001000 { + compatible =3D "mediatek,mt8365-infracfg", "syscon"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pericfg: syscon@10003000 { + compatible =3D "mediatek,mt8365-pericfg", "syscon"; + reg =3D <0 0x10003000 0 0x1000>; + #clock-cells =3D <1>; + }; + + syscfg_pctl: syscfg-pctl@10005000 { + compatible =3D "mediatek,mt8365-syscfg", "syscon"; + reg =3D <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@1000b000 { + compatible =3D "mediatek,mt8365-pinctrl"; + reg =3D <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap =3D <&syscfg_pctl>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + }; + + apmixedsys: syscon@1000c000 { + compatible =3D "mediatek,mt8365-apmixedsys", "syscon"; + reg =3D <0 0x1000c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + keypad: keypad@10010000 { + compatible =3D "mediatek,mt6779-keypad"; + reg =3D <0 0x10010000 0 0x1000>; + wakeup-source; + interrupts =3D ; + clocks =3D <&clk26m>; + clock-names =3D "kpd"; + status =3D "disabled"; + }; + + mcucfg: syscon@10200000 { + compatible =3D "mediatek,mt8365-mcucfg", "syscon"; + reg =3D <0 0x10200000 0 0x2000>; + #clock-cells =3D <1>; + }; + + sysirq: interrupt-controller@10200a80 { + compatible =3D "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells =3D <3>; + interrupt-parent =3D <&gic>; + reg =3D <0 0x10200a80 0 0x20>; + }; + + infracfg_nao: infracfg@1020e000 { + compatible =3D "mediatek,mt8365-infracfg", "syscon"; + reg =3D <0 0x1020e000 0 0x1000>; + #clock-cells =3D <1>; + }; + + rng: rng@1020f000 { + compatible =3D "mediatek,mt8365-rng", "mediatek,mt7623-rng"; + reg =3D <0 0x1020f000 0 0x100>; + clocks =3D <&infracfg CLK_IFR_TRNG>; + clock-names =3D "rng"; + }; + + apdma: dma-controller@11000280 { + compatible =3D "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; + reg =3D <0 0x11000280 0 0x80>, + <0 0x11000300 0 0x80>, + <0 0x11000380 0 0x80>, + <0 0x11000400 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>; + interrupts =3D , + , + , + , + , + ; + dma-requests =3D <6>; + clocks =3D <&infracfg CLK_IFR_AP_DMA>; + clock-names =3D "apdma"; + #dma-cells =3D <1>; + }; + + uart0: serial@11002000 { + compatible =3D "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11002000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART0>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 0>, <&apdma 1>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + uart1: serial@11003000 { + compatible =3D "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11003000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART1>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 2>, <&apdma 3>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + uart2: serial@11004000 { + compatible =3D "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11004000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART2>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 4>, <&apdma 5>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + pwm: pwm@11006000 { + compatible =3D "mediatek,mt8365-pwm"; + reg =3D <0 0x11006000 0 0x1000>; + #pwm-cells =3D <2>; + interrupts =3D ; + clocks =3D <&infracfg CLK_IFR_PWM_HCLK>, + <&infracfg CLK_IFR_PWM>, + <&infracfg CLK_IFR_PWM1>, + <&infracfg CLK_IFR_PWM2>, + <&infracfg CLK_IFR_PWM3>; + clock-names =3D "top", "main", "pwm1", "pwm2", "pwm3"; + }; + + spi: spi@1100a000 { + compatible =3D "mediatek,mt8365-spi", "mediatek,mt7622-spi"; + reg =3D <0 0x1100a000 0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_IFR_SPI0>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + ssusb: usb@11201000 { + compatible =3D "mediatek,mt8365-mtu3", "mediatek,mtu3"; + reg =3D <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port0 PHY_TYPE_USB2>, + <&u2port1 PHY_TYPE_USB2>; + clocks =3D <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + usb_host: usb@11200000 { + compatible =3D "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>; + reg-names =3D "mac"; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>, + <&infracfg CLK_IFR_SSUSB_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck"; + status =3D "disabled"; + }; + }; + + u3phy: t-phy@11cc0000 { + compatible =3D "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0x11cc0000 0x9000>; + + u2port0: usb-phy@0 { + reg =3D <0x0 0x400>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + + u2port1: usb-phy@1000 { + reg =3D <0x1000 0x400>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; + + system_clk: dummy13m { + compatible =3D "fixed-clock"; + clock-frequency =3D <13000000>; + #clock-cells =3D <0>; + }; + + systimer: timer@10017000 { + compatible =3D "mediatek,mt8365-systimer", "mediatek,mt6795-systimer"; + reg =3D <0 0x10017000 0 0x10>; + interrupts =3D ; + clocks =3D <&system_clk>; + clock-names =3D "clk13m"; + }; +}; --=20 2.39.1