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[77.158.188.58]) by smtp.gmail.com with ESMTPSA id a5-20020adfeec5000000b002bfb5ebf8cfsm49427wrp.21.2023.01.24.05.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 05:17:25 -0800 (PST) From: bchihi@baylibre.com To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com, james.lo@mediatek.com, rex-bc.chen@mediatek.com Subject: [PATCH v11 5/6] arm64/dts/mt8195: Add thermal zones and thermal nodes Date: Tue, 24 Jan 2023 14:17:16 +0100 Message-Id: <20230124131717.128660-6-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124131717.128660-1-bchihi@baylibre.com> References: <20230124131717.128660-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Balsam CHIHI Add thermal zones and thermal nodes for the mt8195. Signed-off-by: Balsam CHIHI Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 129 +++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 09df105f4606..636676f4ba25 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8195"; @@ -954,6 +955,17 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvts_ap: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8195-lvts-ap"; + reg =3D <0 0x1100b000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells =3D <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names =3D "lvts-calib-data-1", "lvts-calib-data-2"; + #thermal-sensor-cells =3D <1>; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8195-spi", "mediatek,mt6765-spi"; @@ -1114,6 +1126,17 @@ mmc2: mmc@11250000 { status =3D "disabled"; }; =20 + lvts_mcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8195-lvts-mcu"; + reg =3D <0 0x11278000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells =3D <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names =3D "lvts-calib-data-1", "lvts-calib-data-2"; + #thermal-sensor-cells =3D <1>; + }; + xhci1: usb@11290000 { compatible =3D "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; @@ -2387,4 +2410,110 @@ dp_tx: dp-tx@1c600000 { status =3D "disabled"; }; }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; + trips { + cpu0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; + trips { + cpu1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; + trips { + cpu2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; + trips { + cpu3_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8195_MCU_BIG_CPU0>; + trips { + cpu4_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8195_MCU_BIG_CPU1>; + trips { + cpu5_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8195_MCU_BIG_CPU2>; + trips { + cpu6_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8195_MCU_BIG_CPU3>; + trips { + cpu7_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + }; }; --=20 2.34.1