From nobody Sun Sep 14 11:12:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02414C25B4E for ; Tue, 24 Jan 2023 12:48:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234127AbjAXMsa (ORCPT ); Tue, 24 Jan 2023 07:48:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233508AbjAXMsI (ORCPT ); Tue, 24 Jan 2023 07:48:08 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E54B045F55 for ; Tue, 24 Jan 2023 04:47:37 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id q5so9101409wrv.0 for ; Tue, 24 Jan 2023 04:47:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LI7ob5A3GLS+/fd2IRfiNMK3JCx07FDBF5mmOVVsu4U=; b=E/Pr8Bh6XtfCypEgIEh0gYbDps/AgIyfRuowm653uK3vWGpgg2eF77fZz4mQ0sU4pd Phkr0zaBSFqvwOdNb8nK/jZXTYMnips1Xct41XaHiclCDW7yx9iQghgR0ZXzg+lRVTOM GsQTg0E//dZd5fxxP1v4iRS8BYkXsXAp9sJQsSfGsFQQ7xVd/89w/2Sy8ghF5+Airmgy fwWIhRHm8Y4+q6O5PG+hbbkYPx0Tw7hFgzfr9s3UKfS8dfrJqzOVpTGc8sXXgmcfMOMq 3pXOCVn1oouUq9/KzsiTlRzzNTIC/NbFvFjsGP5qGXhs7CfpgG6htRZ+BhtGvr4u1eiZ XR3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LI7ob5A3GLS+/fd2IRfiNMK3JCx07FDBF5mmOVVsu4U=; b=HsqiByMU0eUWcXLc6g8zSiJMJkU421q75jFCUChhzNMv9C82Yq+Cc3Fsjf6qkf8c/c AYreivvwXqTnZXInxqEATyRQT8/g1TtzF30Ynj6xP/9TUVBfd6HTbkAFux2ct+sG1oHr ioDF32MfGn7I+XxahFkqhOi+2tdpBKW2ekms4IXikRtjBx2IDkpGk3tO9LrCqjoAy+4l 9hKspfR5MJsC/AsfaBPffY/T77yej0y31/rLPuPZ1DrPU13MfazCUP4kUxj1Gl1SOCSA 4RB6tLKm8t5B8oOrHB8NDy2eY2XS5RHPMTHBEPQ2BcigLZ6BdNT74mRkeMqnJG6y6V/+ 4wGA== X-Gm-Message-State: AFqh2kqIBpKi78CGBN2AbTe2Kqrnu/yt9fvfKZmM5i6LC09j/ancIB6u BiBfydYkr+nWymuLuH+c7gMNGA== X-Google-Smtp-Source: AMrXdXvMfMyHE90bq/w41/dGeRJL3t6Wy35AgiIX8k9jAHqzxq8SiiUoo5ApH/AVqTdna62CXa3uZA== X-Received: by 2002:adf:8b1c:0:b0:2bf:9478:a91d with SMTP id n28-20020adf8b1c000000b002bf9478a91dmr11422554wra.39.1674564457407; Tue, 24 Jan 2023 04:47:37 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id a5-20020a5d5705000000b002bdbde1d3absm1766840wrv.78.2023.01.24.04.47.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 04:47:36 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-phy@lists.infradead.org Subject: [PATCH v5 10/12] PCI: qcom: Add SM8550 PCIe support Date: Tue, 24 Jan 2023 14:47:12 +0200 Message-Id: <20230124124714.3087948-11-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124124714.3087948-1-abel.vesa@linaro.org> References: <20230124124714.3087948-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatible for both PCIe found on SM8550. Also add the cnoc_pcie_sf_axi clock needed by the SM8550. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam --- The v4 of this patchset is: https://lore.kernel.org/all/20230119140453.3942340-11-abel.vesa@linaro.org/ Changes since v4: * added Mani's R-b tag Changes since v3: * renamed cnoc_pcie_sf_axi to cnoc_sf_axi Changes since v2: * none Changes since v1: * changed the subject line prefix for the patch to match the history, like Bjorn Helgaas suggested. * added Konrad's R-b tag drivers/pci/controller/dwc/pcie-qcom.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 77e5dc7b88ad..0297f86e15c9 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -182,10 +182,10 @@ struct qcom_pcie_resources_2_3_3 { =20 /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[14]; int num_clks; struct regulator_bulk_data supplies[2]; - struct reset_control *pci_reset; + struct reset_control *rst; }; =20 struct qcom_pcie_resources_2_9_0 { @@ -1177,9 +1177,9 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_= pcie *pcie) unsigned int idx; int ret; =20 - res->pci_reset =3D devm_reset_control_get_exclusive(dev, "pci"); - if (IS_ERR(res->pci_reset)) - return PTR_ERR(res->pci_reset); + res->rst =3D devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(res->rst)) + return PTR_ERR(res->rst); =20 res->supplies[0].supply =3D "vdda"; res->supplies[1].supply =3D "vddpe-3v3"; @@ -1205,9 +1205,11 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom= _pcie *pcie) res->clks[idx++].id =3D "ddrss_sf_tbu"; res->clks[idx++].id =3D "aggre0"; res->clks[idx++].id =3D "aggre1"; + res->clks[idx++].id =3D "noc_aggr"; res->clks[idx++].id =3D "noc_aggr_4"; res->clks[idx++].id =3D "noc_aggr_south_sf"; res->clks[idx++].id =3D "cnoc_qx"; + res->clks[idx++].id =3D "cnoc_sf_axi"; =20 num_opt_clks =3D idx - num_clks; res->num_clks =3D idx; @@ -1237,17 +1239,17 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *p= cie) if (ret < 0) goto err_disable_regulators; =20 - ret =3D reset_control_assert(res->pci_reset); - if (ret < 0) { - dev_err(dev, "cannot assert pci reset\n"); + ret =3D reset_control_assert(res->rst); + if (ret) { + dev_err(dev, "reset assert failed (%d)\n", ret); goto err_disable_clocks; } =20 usleep_range(1000, 1500); =20 - ret =3D reset_control_deassert(res->pci_reset); - if (ret < 0) { - dev_err(dev, "cannot deassert pci reset\n"); + ret =3D reset_control_deassert(res->rst); + if (ret) { + dev_err(dev, "reset deassert failed (%d)\n", ret); goto err_disable_clocks; } =20 @@ -1828,6 +1830,7 @@ static const struct of_device_id qcom_pcie_match[] = =3D { { .compatible =3D "qcom,pcie-sm8250", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sm8450-pcie0", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sm8450-pcie1", .data =3D &cfg_1_9_0 }, + { .compatible =3D "qcom,pcie-sm8550", .data =3D &cfg_1_9_0 }, { } }; =20 --=20 2.34.1