From nobody Sun Sep 14 14:31:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90E35C61D9D for ; Sun, 22 Jan 2023 12:21:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230086AbjAVMVk (ORCPT ); Sun, 22 Jan 2023 07:21:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229921AbjAVMVi (ORCPT ); Sun, 22 Jan 2023 07:21:38 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 855E961A4; Sun, 22 Jan 2023 04:21:37 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 30MCLRLH106734; Sun, 22 Jan 2023 06:21:27 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1674390087; bh=TISRczCqqClgTnuh9Jgbp4YdFIC7Href1UTZ0gVUQ5I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vEINhMjtD19zKyn81aKyiO8PEEYlg97ZkguUPjq6lA79zoe9+q7jb13wTyTtLdId5 9pOhwf79bQ5GIDtIP2xjd6Yd1LMqA0uW6Cwpmf4FeiZnOdYLzLO8W1ET5kWq0hzH+G yYk/Kyd53aAGLjcgLeMIBm6apoU6AxNSd9NvdPWQ= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 30MCLRab102324 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 22 Jan 2023 06:21:27 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Sun, 22 Jan 2023 06:21:27 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Sun, 22 Jan 2023 06:21:27 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30MCLQWM029950; Sun, 22 Jan 2023 06:21:27 -0600 From: Achal Verma To: , , , , , , , , , , , CC: , , , Subject: [PATCH v9 3/5] PCI: j721e: Add PCIe 4x lane selection support Date: Sun, 22 Jan 2023 17:51:19 +0530 Message-ID: <20230122122121.3552375-4-a-verma1@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230122122121.3552375-1-a-verma1@ti.com> References: <20230122122121.3552375-1-a-verma1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matt Ranostay Add support for setting of two-bit field that allows selection of 4x lane PCIe which was previously limited to only 2x lanes. Signed-off-by: Matt Ranostay Reviewed-by: Vignesh Raghavendra Reviewed-by: Roger Quadros Signed-off-by: Achal Verma --- drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/contr= oller/cadence/pci-j721e.c index f4dc2c5abedb..58dcac9021e4 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -42,7 +42,6 @@ enum link_status { }; =20 #define J721E_MODE_RC BIT(7) -#define LANE_COUNT_MASK BIT(8) #define LANE_COUNT(n) ((n) << 8) =20 #define GENERATION_SEL_MASK GENMASK(1, 0) @@ -52,6 +51,7 @@ struct j721e_pcie { struct clk *refclk; u32 mode; u32 num_lanes; + u32 max_lanes; void __iomem *user_cfg_base; void __iomem *intd_cfg_base; u32 linkdown_irq_regfield; @@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pci= e *pcie, { struct device *dev =3D pcie->cdns_pcie->dev; u32 lanes =3D pcie->num_lanes; + u32 mask =3D BIT(8); u32 val =3D 0; int ret; =20 + if (pcie->max_lanes =3D=3D 4) + mask =3D GENMASK(9, 8); + val =3D LANE_COUNT(lanes - 1); - ret =3D regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); + ret =3D regmap_update_bits(syscon, offset, mask, val); if (ret) dev_err(dev, "failed to set link count\n"); =20 @@ -441,7 +445,9 @@ static int j721e_pcie_probe(struct platform_device *pde= v) dev_warn(dev, "num-lanes property not provided or invalid, setting num-l= anes to 1\n"); num_lanes =3D 1; } + pcie->num_lanes =3D num_lanes; + pcie->max_lanes =3D data->max_lanes; =20 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) return -EINVAL; --=20 2.25.1