From nobody Sun Sep 14 12:32:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE1B0C25B4E for ; Sun, 22 Jan 2023 08:17:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229841AbjAVIRc (ORCPT ); Sun, 22 Jan 2023 03:17:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229768AbjAVIR1 (ORCPT ); Sun, 22 Jan 2023 03:17:27 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F3EB222F7 for ; Sun, 22 Jan 2023 00:17:26 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 30M8GrJx068237; Sun, 22 Jan 2023 02:16:53 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1674375413; bh=mv0hV8ewp95lt3yVu41QLxHIs0FJ5UPFOndlM24JKb4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SSGGTw0deoid9ImgiWTAVwv4gbqrtM6vqV8AoM/DF+UJpBDOkpm3DKu4YlJDuTdz/ 6bQCWKmmJI4W3MhPwLM+T21SFYkvcqH2hTb8KAeuzrzlTTVy+Tj+EAx/411dCm61Xw bdic81Na1034MgYhcny1zEz+msgsalRjbhq/UC2U= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 30M8Grmt074821 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 22 Jan 2023 02:16:53 -0600 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Sun, 22 Jan 2023 02:16:53 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Sun, 22 Jan 2023 02:16:53 -0600 Received: from ula0132425.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30M8GjId079831; Sun, 22 Jan 2023 02:16:50 -0600 From: Vignesh Raghavendra To: Nishanth Menon , Tero Kristo , Santosh Shilimkar , Thomas Gleixner , Marc Zyngier CC: , , Vignesh Raghavendra Subject: [RFC PATCH 1/2] irqchip: irq-ti-sci-inta: Don't aggregate MSI events until necessary Date: Sun, 22 Jan 2023 13:46:06 +0530 Message-ID: <20230122081607.959474-2-vigneshr@ti.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230122081607.959474-1-vigneshr@ti.com> References: <20230122081607.959474-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" INTA on K3 SoCs convert DMA global events (MSI) to wired interrupts (VINT). Currently driver maps multiple events to single wired interrupt lines. This makes setting IRQ affinity impossible as migrating wired interrupt to different core will end up migrating all events to that core. Allocate a dedicated VINT for each DMA event request until there are no more VINTs. This creates a 1:1 DMA event to VINT mapping and thus provides unique IRQ line. This will help allocate dedicated IRQs for high performance DMA channels which can thus be mapped to particular CPUs using IRQ affinity. Signed-off-by: Vignesh Raghavendra --- drivers/irqchip/irq-ti-sci-inta.c | 45 +++++++++++++++++-------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/irqchip/irq-ti-sci-inta.c b/drivers/irqchip/irq-ti-sci= -inta.c index a6ecc53d055c..f1419d24568e 100644 --- a/drivers/irqchip/irq-ti-sci-inta.c +++ b/drivers/irqchip/irq-ti-sci-inta.c @@ -202,7 +202,8 @@ static int ti_sci_inta_xlate_irq(struct ti_sci_inta_irq= _domain *inta, * * Return 0 if all went well else corresponding error value. */ -static struct ti_sci_inta_vint_desc *ti_sci_inta_alloc_parent_irq(struct i= rq_domain *domain) +static struct ti_sci_inta_vint_desc *ti_sci_inta_alloc_parent_irq(struct i= rq_domain *domain, + u16 vint_id) { struct ti_sci_inta_irq_domain *inta =3D domain->host_data; struct ti_sci_inta_vint_desc *vint_desc; @@ -210,11 +211,6 @@ static struct ti_sci_inta_vint_desc *ti_sci_inta_alloc= _parent_irq(struct irq_dom struct device_node *parent_node; unsigned int parent_virq; int p_hwirq, ret; - u16 vint_id; - - vint_id =3D ti_sci_get_free_resource(inta->vint); - if (vint_id =3D=3D TI_SCI_RESOURCE_NULL) - return ERR_PTR(-EINVAL); =20 p_hwirq =3D ti_sci_inta_xlate_irq(inta, vint_id); if (p_hwirq < 0) { @@ -328,29 +324,38 @@ static struct ti_sci_inta_event_desc *ti_sci_inta_all= oc_irq(struct irq_domain *d struct ti_sci_inta_vint_desc *vint_desc =3D NULL; struct ti_sci_inta_event_desc *event_desc; u16 free_bit; + u16 vint_id; =20 mutex_lock(&inta->vint_mutex); - list_for_each_entry(vint_desc, &inta->vint_list, list) { + /* + * Allocate new VINT each time until we runout, then start + * aggregating + */ + vint_id =3D ti_sci_get_free_resource(inta->vint); + if (vint_id =3D=3D TI_SCI_RESOURCE_NULL) { + list_for_each_entry(vint_desc, &inta->vint_list, list) { + free_bit =3D find_first_zero_bit(vint_desc->event_map, + MAX_EVENTS_PER_VINT); + if (free_bit !=3D MAX_EVENTS_PER_VINT) + set_bit(free_bit, vint_desc->event_map); + } + } else { + vint_desc =3D ti_sci_inta_alloc_parent_irq(domain, vint_id); + if (IS_ERR(vint_desc)) { + event_desc =3D ERR_CAST(vint_desc); + goto unlock; + } + free_bit =3D find_first_zero_bit(vint_desc->event_map, MAX_EVENTS_PER_VINT); - if (free_bit !=3D MAX_EVENTS_PER_VINT) { - set_bit(free_bit, vint_desc->event_map); - goto alloc_event; - } + set_bit(free_bit, vint_desc->event_map); } =20 - /* No free bits available. Allocate a new vint */ - vint_desc =3D ti_sci_inta_alloc_parent_irq(domain); - if (IS_ERR(vint_desc)) { - event_desc =3D ERR_CAST(vint_desc); + if (free_bit =3D=3D MAX_EVENTS_PER_VINT) { + event_desc =3D ERR_PTR(-EINVAL); goto unlock; } =20 - free_bit =3D find_first_zero_bit(vint_desc->event_map, - MAX_EVENTS_PER_VINT); - set_bit(free_bit, vint_desc->event_map); - -alloc_event: event_desc =3D ti_sci_inta_alloc_event(vint_desc, free_bit, hwirq); if (IS_ERR(event_desc)) clear_bit(free_bit, vint_desc->event_map); --=20 2.39.0 From nobody Sun Sep 14 12:32:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DF32C25B4E for ; Sun, 22 Jan 2023 08:17:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229686AbjAVIRT (ORCPT ); Sun, 22 Jan 2023 03:17:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229625AbjAVIRS (ORCPT ); Sun, 22 Jan 2023 03:17:18 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E805A222D2 for ; Sun, 22 Jan 2023 00:17:16 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 30M8Gvci039901; Sun, 22 Jan 2023 02:16:57 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1674375417; bh=jJajb1VP2PjMo6TmRNZ2Wj2zpHQ05oS+g9eclveVChc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zEKXzQnf6mJkyA0cR3OwS+ShNgOm3gMfT/Sa9PDlXNS5taSHFytuFIbxzPvy0jbQF kXYQ/VbJ8pVkiRzbn9c3ucy+my1RY71hDN0Vi9/gKqkRfsTZMiGhCJg/ubcu4cTjh7 f81+FBew0wXGawyDXqQf2qUxlx+xovneCTuYoHwI= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 30M8Guq7064961 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 22 Jan 2023 02:16:57 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Sun, 22 Jan 2023 02:16:56 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Sun, 22 Jan 2023 02:16:56 -0600 Received: from ula0132425.ent.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30M8GjIe079831; Sun, 22 Jan 2023 02:16:53 -0600 From: Vignesh Raghavendra To: Nishanth Menon , Tero Kristo , Santosh Shilimkar , Thomas Gleixner , Marc Zyngier CC: , , Vignesh Raghavendra Subject: [RFC PATCH 2/2] irqchip: irq-ti-sci-inta: Introduce IRQ affinity support Date: Sun, 22 Jan 2023 13:46:07 +0530 Message-ID: <20230122081607.959474-3-vigneshr@ti.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230122081607.959474-1-vigneshr@ti.com> References: <20230122081607.959474-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for setting IRQ affinity for VINTs which have only one event mapped to them. This just involves changing the parent IRQs affinity (GIC/INTR). Flag VINTs which have affinity configured so as to not aggregate/map more events to such VINTs. Signed-off-by: Vignesh Raghavendra --- drivers/irqchip/irq-ti-sci-inta.c | 39 +++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/irqchip/irq-ti-sci-inta.c b/drivers/irqchip/irq-ti-sci= -inta.c index f1419d24568e..237cb4707cb8 100644 --- a/drivers/irqchip/irq-ti-sci-inta.c +++ b/drivers/irqchip/irq-ti-sci-inta.c @@ -64,6 +64,7 @@ struct ti_sci_inta_event_desc { * @events: Array of event descriptors assigned to this vint. * @parent_virq: Linux IRQ number that gets attached to parent * @vint_id: TISCI vint ID + * @affinity_managed flag to indicate VINT affinity is managed */ struct ti_sci_inta_vint_desc { struct irq_domain *domain; @@ -72,6 +73,7 @@ struct ti_sci_inta_vint_desc { struct ti_sci_inta_event_desc events[MAX_EVENTS_PER_VINT]; unsigned int parent_virq; u16 vint_id; + bool affinity_managed; }; =20 /** @@ -334,6 +336,8 @@ static struct ti_sci_inta_event_desc *ti_sci_inta_alloc= _irq(struct irq_domain *d vint_id =3D ti_sci_get_free_resource(inta->vint); if (vint_id =3D=3D TI_SCI_RESOURCE_NULL) { list_for_each_entry(vint_desc, &inta->vint_list, list) { + if (vint_desc->affinity_managed) + continue; free_bit =3D find_first_zero_bit(vint_desc->event_map, MAX_EVENTS_PER_VINT); if (free_bit !=3D MAX_EVENTS_PER_VINT) @@ -434,6 +438,7 @@ static int ti_sci_inta_request_resources(struct irq_dat= a *data) return PTR_ERR(event_desc); =20 data->chip_data =3D event_desc; + irq_data_update_effective_affinity(data, cpu_online_mask); =20 return 0; } @@ -504,11 +509,45 @@ static void ti_sci_inta_ack_irq(struct irq_data *data) ti_sci_inta_manage_event(data, VINT_STATUS_OFFSET); } =20 +#ifdef CONFIG_SMP +static int ti_sci_inta_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, bool force) +{ + struct ti_sci_inta_event_desc *event_desc; + struct ti_sci_inta_vint_desc *vint_desc; + struct irq_data *parent_irq_data; + + if (cpumask_equal(irq_data_get_effective_affinity_mask(d), mask_val)) + return 0; + + event_desc =3D irq_data_get_irq_chip_data(d); + if (event_desc) { + vint_desc =3D to_vint_desc(event_desc, event_desc->vint_bit); + + /* + * Cannot set affinity if there is more than one event + * mapped to same VINT + */ + if (bitmap_weight(vint_desc->event_map, MAX_EVENTS_PER_VINT) > 1) + return -EINVAL; + + vint_desc->affinity_managed =3D true; + + irq_data_update_effective_affinity(d, mask_val); + parent_irq_data =3D irq_get_irq_data(vint_desc->parent_virq); + if (parent_irq_data->chip->irq_set_affinity) + return parent_irq_data->chip->irq_set_affinity(parent_irq_data, mask_va= l, force); + } + + return -EINVAL; +} +#else static int ti_sci_inta_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force) { return -EINVAL; } +#endif =20 /** * ti_sci_inta_set_type() - Update the trigger type of the irq. --=20 2.39.0