From nobody Sun Sep 14 12:34:52 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADDB6C38142 for ; Sat, 21 Jan 2023 21:35:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229911AbjAUVfe (ORCPT ); Sat, 21 Jan 2023 16:35:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229825AbjAUVf0 (ORCPT ); Sat, 21 Jan 2023 16:35:26 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 515C6233E3 for ; Sat, 21 Jan 2023 13:35:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674336925; x=1705872925; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Utkwbxd4F4NcYH1oAdF84yeEOd+4iF/ZZchylSgannA=; b=cQ6IbpuREL7gi1Co98O+fJdM3zpFqrvbDoM6sGdwfhJ3CZXVVDZ0n0vx 9/tl7gW+N2E9r3CR6THtp8tv8Gc8uPioP/CglK/M8VHNJdxl1w/cfOOCa tuMtzdq4OesR1ZgUsNDabQUludvsjPHaPRhqi34ZC1lVmAc8kdcdDDdDl w83YvSklHz4cTbG50jDFmjDvEUCxei+sYEKW36R78/TZtAKzJ6AXZ/ORB JEFn4UNpIb3wVZvVMppY0F4amTb5ahD1DRLvJE9uxYcyioBP4RwtWJmPM uu30QL31FApEiDfK3/v0pw3+Z3FI6ldlpTP/ZkmaxA3IWltHL0JLfqAe5 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10597"; a="412066332" X-IronPort-AV: E=Sophos;i="5.97,235,1669104000"; d="scan'208";a="412066332" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jan 2023 13:35:22 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10597"; a="784946316" X-IronPort-AV: E=Sophos;i="5.97,235,1669104000"; d="scan'208";a="784946316" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jan 2023 13:35:21 -0800 From: Ashok Raj To: Thomas Gleixner , Borislav Petkov Cc: Ashok Raj , LKML , x86 , Ingo Molnar , Tony Luck , Dave Hansen , Alison Schofield , Reinette Chatre , Tom Lendacky , Stefan Talpalaru , David Woodhouse , Benjamin Herrenschmidt , Jonathan Corbet , "Rafael J . Wysocki" , Peter Zilstra , Andy Lutomirski , Andrew Cooper , Boris Ostrovsky , Martin Pohlack Subject: [Part 2 v2[cleanup] 3/4] x86/microcode/intel: Fix collect_cpu_info() to reflect current microcode Date: Sat, 21 Jan 2023 13:35:11 -0800 Message-Id: <20230121213512.251578-4-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230121213512.251578-1-ashok.raj@intel.com> References: <87y1pygiyf.ffs@tglx> <20230121213512.251578-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently collect_cpu_info() is only returning what was cached earlier instead of reading the current revision from the proper MSR. Collect the current revision and report that value instead of reflecting what was cached in the past. [TBD: Need to change microcode/amd.c. I didn't quite follow the logic since it reports the patch from the pathfile instead of reading the real PATCH_LEVEL MSR. ] Signed-off-by: Ashok Raj Cc: LKML Cc: x86 Cc: Ingo Molnar Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner (Intel) Cc: Tom Lendacky Cc: Stefan Talpalaru Cc: David Woodhouse Cc: Benjamin Herrenschmidt Cc: Jonathan Corbet Cc: Rafael J. Wysocki Cc: Peter Zilstra (Intel) Cc: Andy Lutomirski Cc: Andrew Cooper Cc: Boris Ostrovsky Cc: Martin Pohlack --- arch/x86/kernel/cpu/microcode/intel.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 4471d418f28a..be830944178c 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -543,6 +543,13 @@ static int collect_cpu_info(int cpu_num, struct cpu_si= gnature *csig) { struct cpuinfo_x86 *c =3D &cpu_data(cpu_num); unsigned int val[2]; + int rev; + + /* + * intel_get_microcode_revision() reads a per-core MSR + * to read the revision (MSR_IA32_UCODE_REV). + */ + WARN_ON_ONCE(cpu_num !=3D smp_processor_id()); =20 memset(csig, 0, sizeof(*csig)); =20 @@ -554,7 +561,8 @@ static int collect_cpu_info(int cpu_num, struct cpu_sig= nature *csig) csig->pf =3D 1 << ((val[1] >> 18) & 7); } =20 - csig->rev =3D c->microcode; + rev =3D intel_get_microcode_revision(); + csig->rev =3D c->microcode =3D rev; =20 return 0; } --=20 2.34.1