From nobody Sun Sep 14 12:59:41 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D1C7C38159 for ; Sat, 21 Jan 2023 00:31:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230043AbjAUAbk (ORCPT ); Fri, 20 Jan 2023 19:31:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229773AbjAUAbh (ORCPT ); Fri, 20 Jan 2023 19:31:37 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6FC21420F; Fri, 20 Jan 2023 16:31:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674261079; x=1705797079; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=YMQAWurETlSCjBbvjxddlKNJW8TpNQNrIE4e8GG/gJs=; b=DANXdSbgFMJ+MkCkaczkA3VB+vXSHQuaFTXk3mpJNH3Y7LSro3/o4XRY ejgoYrQLvzE6OV9MnGZA/uZWIGVruVc+X7DBNCdVOH1DmQbE+atwdMH1z 7rpVxs+H+Yv5CsQ/I0sWwRBILH8DY3/0BsCLNUFaBcGXHZWb6MPKtv42Y i5/WZN1SGyhkSk7XkqQDvs08ZV7sFgk3QLNuuhrihlH5fSMrx2wun4WBK YOyt4s0Ufx7rIFM6sa6xpfaECZ/c6dRvncLi7i+Vx+4LmdsJrY3xAH+lw niYx1VTdZFcNBvqnTLRUivplaVztDgg3AHZQaupDTbySOWEN+kj32pqho A==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="305404609" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="305404609" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 16:30:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="784729483" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="784729483" Received: from chang-linux-3.sc.intel.com ([172.25.66.173]) by orsmga004.jf.intel.com with ESMTP; 20 Jan 2023 16:30:16 -0800 From: "Chang S. Bae" To: dave.hansen@linux.intel.com, x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de Cc: hpa@zytor.com, corbet@lwn.net, bagasdotme@gmail.com, tony.luck@intel.com, yang.zhong@intel.com, linux-doc@vger.kernel.org, linux-man@vger.kernel.org, linux-kernel@vger.kernel.org, chang.seok.bae@intel.com Subject: [PATCH v5 RESEND 1/4] Documentation/x86: Explain the purpose for dynamic features Date: Fri, 20 Jan 2023 16:18:57 -0800 Message-Id: <20230121001900.14900-2-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230121001900.14900-1-chang.seok.bae@intel.com> References: <20220922195810.23248-1-chang.seok.bae@intel.com> <20230121001900.14900-1-chang.seok.bae@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This summary will help to guide the proper use of the enabling model. Signed-off-by: Chang S. Bae Reviewed-by: Tony Luck Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org --- Changes from v4: * Re-write about the sigaltstack sizing (Dave Hansen). * Drop the second point as the case is not clear yet. Changes from v3: * Add as a new patch (Tony Luck). --- Documentation/x86/xstate.rst | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/x86/xstate.rst b/Documentation/x86/xstate.rst index 5cec7fb558d6..e954e79af4ce 100644 --- a/Documentation/x86/xstate.rst +++ b/Documentation/x86/xstate.rst @@ -11,6 +11,22 @@ are enabled by XCR0 as well, but the first use of relate= d instruction is trapped by the kernel because by default the required large XSTATE buffers are not allocated automatically. =20 +The purpose for dynamic features +-------------------------------- + +Legacy userspace libraries often have hard-coded, static sizes for +alternate signal stacks, often using MINSIGSTKSZ which is typically 2KB. +That stack must be able to store at *least* the signal frame that the +kernel sets up before jumping into the signal handler. That signal frame +must include an XSAVE buffer defined by the CPU. + +However, that means that the size of signal stacks is dynamic, not static, +because different CPUs have differently-sized XSAVE buffers. A compiled-in +size of 2KB with existing applications is too small for new CPU features +like AMX. Instead of universally requiring larger stack, with the dynamic +enabling, the kernel can enforce userspace applications to have +properly-sized altstacks. + Using dynamically enabled XSTATE features in user space applications -------------------------------------------------------------------- =20 --=20 2.17.1 From nobody Sun Sep 14 12:59:41 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B76ACC25B50 for ; Sat, 21 Jan 2023 00:31:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229973AbjAUAb6 (ORCPT ); Fri, 20 Jan 2023 19:31:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229741AbjAUAb4 (ORCPT ); Fri, 20 Jan 2023 19:31:56 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D29DDFF13; Fri, 20 Jan 2023 16:31:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674261085; x=1705797085; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=v8yPnByOxolH3y3Ja7dBlrus/vQe6rAVnEPjft+iu64=; b=OCaO3Qr6DVgQZRvgrGsQtBg83/tU7y6WFHokyBLjj09uF25OlukilrDb 7UX/Fk3Yv10tgiiJgv38BnnKF9HJunhNv+vZBC/2JLvmLnkPwQ/ntvUiE rWFcMzVSywPgUEy6nzLH2x9R33ron45VkxlEEpqFjSyYNGtu065fACw9f zKw+ktV4+6VwWFlTcgJq8luJMY47SMl/TE01LyEnk6OkK8Gu8IDz+OMBW 2j6NM01gO3BKv83I0SgwOIkwO7RyGFKXp8ATBZYGq747IxvGLhhWwu9GM B/7oohh20b8sIXs0NvNwxoJKLPjagBmR3qSwtfqvZWwAiacerrAQpYHk9 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="305404624" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="305404624" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 16:30:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="784729488" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="784729488" Received: from chang-linux-3.sc.intel.com ([172.25.66.173]) by orsmga004.jf.intel.com with ESMTP; 20 Jan 2023 16:30:16 -0800 From: "Chang S. Bae" To: dave.hansen@linux.intel.com, x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de Cc: hpa@zytor.com, corbet@lwn.net, bagasdotme@gmail.com, tony.luck@intel.com, yang.zhong@intel.com, linux-doc@vger.kernel.org, linux-man@vger.kernel.org, linux-kernel@vger.kernel.org, chang.seok.bae@intel.com Subject: [PATCH v5 RESEND 2/4] x86/arch_prctl: Add AMX feature numbers as ABI constants Date: Fri, 20 Jan 2023 16:18:58 -0800 Message-Id: <20230121001900.14900-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230121001900.14900-1-chang.seok.bae@intel.com> References: <20220922195810.23248-1-chang.seok.bae@intel.com> <20230121001900.14900-1-chang.seok.bae@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" AMX state is dynamically enabled by the architecture-specific prctl(). Expose the state components as ABI constants. They become handy not to be looked up from the architecture specification. Signed-off-by: Chang S. Bae Reviewed-by: Tony Luck Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org --- Changes from v2: * Add as a new patch (Tony Luck). --- arch/x86/include/uapi/asm/prctl.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/uapi/asm/prctl.h b/arch/x86/include/uapi/asm/= prctl.h index 500b96e71f18..f298c778f856 100644 --- a/arch/x86/include/uapi/asm/prctl.h +++ b/arch/x86/include/uapi/asm/prctl.h @@ -16,6 +16,9 @@ #define ARCH_GET_XCOMP_GUEST_PERM 0x1024 #define ARCH_REQ_XCOMP_GUEST_PERM 0x1025 =20 +#define ARCH_XCOMP_TILECFG 17 +#define ARCH_XCOMP_TILEDATA 18 + #define ARCH_MAP_VDSO_X32 0x2001 #define ARCH_MAP_VDSO_32 0x2002 #define ARCH_MAP_VDSO_64 0x2003 --=20 2.17.1 From nobody Sun Sep 14 12:59:41 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03CA2C27C76 for ; Sat, 21 Jan 2023 00:32:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230183AbjAUAcI (ORCPT ); Fri, 20 Jan 2023 19:32:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230107AbjAUAcE (ORCPT ); Fri, 20 Jan 2023 19:32:04 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D67E1FF0C; Fri, 20 Jan 2023 16:31:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674261097; x=1705797097; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=bfiBHovbm2wDNN6P4ZdJLa8C4JX44HUaHdUbsr9EAAI=; b=Jt2Miv2IuFhXXku+yj1pyK82QhvcnRHTGJRLD3ToCZc+mmaT8xva+7ai QpeVP5Uym7PWp+xD4ozWK1zqFbKeuuDAOQSva/0GlaPsx/9mStORVClpX 37wozEfGWqMNpdsk7ofWaKWVf5WFMgVdIae8k8aIq7STqEJB6rdZlGyql sYcAt8QJMDbRy3ws7lPgUWQ4r4ZZbNBrzwTta0hK2ndAEIXi5K3w0vS0q ditPlBRh26oSNVON7vwSQ+DXp8ddE2GVi5RAWq/1pWQQQj2oEo9pQ4yqD P7vyNpQupnVXDS6GNJu6/Mt4xGeQYArvw+5tQ4Eocr9L+w+vRBlpcrfuo A==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="305404631" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="305404631" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 16:30:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="784729495" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="784729495" Received: from chang-linux-3.sc.intel.com ([172.25.66.173]) by orsmga004.jf.intel.com with ESMTP; 20 Jan 2023 16:30:16 -0800 From: "Chang S. Bae" To: dave.hansen@linux.intel.com, x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de Cc: hpa@zytor.com, corbet@lwn.net, bagasdotme@gmail.com, tony.luck@intel.com, yang.zhong@intel.com, linux-doc@vger.kernel.org, linux-man@vger.kernel.org, linux-kernel@vger.kernel.org, chang.seok.bae@intel.com Subject: [PATCH v5 RESEND 3/4] Documentation/x86: Add the AMX enabling example Date: Fri, 20 Jan 2023 16:18:59 -0800 Message-Id: <20230121001900.14900-4-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230121001900.14900-1-chang.seok.bae@intel.com> References: <20220922195810.23248-1-chang.seok.bae@intel.com> <20230121001900.14900-1-chang.seok.bae@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Explain steps to enable the dynamic feature with a code example. Signed-off-by: Chang S. Bae Reviewed-by: Thiago Macieira Reviewed-by: Bagas Sanjaya Reviewed-by: Tony Luck Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org --- Changes from v1: * Update the description without mentioning CPUID & XGETBV (Dave Hansen). Changes from v2: * Massage sentences (Bagas Sanjaya). * Adjust the example with the (future) prctl.h. --- Documentation/x86/xstate.rst | 55 ++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/Documentation/x86/xstate.rst b/Documentation/x86/xstate.rst index e954e79af4ce..23b1c9f3efb2 100644 --- a/Documentation/x86/xstate.rst +++ b/Documentation/x86/xstate.rst @@ -80,6 +80,61 @@ the handler allocates a larger xstate buffer for the tas= k so the large state can be context switched. In the unlikely cases that the allocation fails, the kernel sends SIGSEGV. =20 +AMX TILE_DATA enabling example +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Below is the example of how userspace applications enable +TILE_DATA dynamically: + + 1. The application first needs to query the kernel for AMX + support:: + + #include + #include + #include + #include + + #ifndef ARCH_GET_XCOMP_SUPP + #define ARCH_GET_XCOMP_SUPP 0x1021 + #endif + + #ifndef ARCH_XCOMP_TILECFG + #define ARCH_XCOMP_TILECFG 17 + #endif + + #ifndef ARCH_XCOMP_TILEDATA + #define ARCH_XCOMP_TILEDATA 18 + #endif + + #define MASK_XCOMP_TILE ((1 << ARCH_XCOMP_TILECFG) | \ + (1 << ARCH_XCOMP_TILEDATA)) + + unsigned long features; + long rc; + + ... + + rc =3D syscall(SYS_arch_prctl, ARCH_GET_XCOMP_SUPP, &features); + + if (!rc && (features & MASK_XCOMP_TILE) =3D=3D MASK_XCOMP_TILE) + printf("AMX is available.\n"); + + 2. After that, determining support for AMX, an application must + explicitly ask permission to use it:: + + #ifndef ARCH_REQ_XCOMP_PERM + #define ARCH_REQ_XCOMP_PERM 0x1023 + #endif + + ... + + rc =3D syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_PERM, ARCH_XCOMP_TIL= EDATA); + + if (!rc) + printf("AMX is ready for use.\n"); + +Note this example does not include the sigaltstack preparation. + Dynamic features in signal frames --------------------------------- =20 --=20 2.17.1 From nobody Sun Sep 14 12:59:41 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19EFCC38159 for ; Sat, 21 Jan 2023 00:32:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230148AbjAUAcD (ORCPT ); Fri, 20 Jan 2023 19:32:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230125AbjAUAcA (ORCPT ); Fri, 20 Jan 2023 19:32:00 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AA26FF1F; Fri, 20 Jan 2023 16:31:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674261089; x=1705797089; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=APb2LiHwFZJrqIKUHw/Hp/TgOVz7B3k99VkTBnRFohc=; b=Ly7N+fEPJOD1GBrhwFHOBD2vN9IZ4wjBERujcncs4gWYGpRpi7hiUrdD X9T7bqYMPhf7T8YhQpJet2y+BrRPyo0+RMRHVmhZZzmjdxt9FiNrdsDhY L6QvXoKrSN8IA4b3fVhZ08TE+FXRSj9jk/3k3SdycaeUlGUk/aEcHZ9Dz 4p95OxFJuhR/GYYS3Koo2iT6aCcNAyOCQ1yP7mGSFS+UqK/VhKYf3anqt j50Ow0QTm1h7uTzVfLH/6zaO3s8kFQ07ftT5Ww8Ck+yuzkv1yZKYYRNwy as8aUCwiaiIiScbZVV/Nbu3QnRCCaomGNenEtIVzWIxZRrhn4d1nm2dZ4 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="305404637" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="305404637" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 16:30:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="784729506" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="784729506" Received: from chang-linux-3.sc.intel.com ([172.25.66.173]) by orsmga004.jf.intel.com with ESMTP; 20 Jan 2023 16:30:17 -0800 From: "Chang S. Bae" To: dave.hansen@linux.intel.com, x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de Cc: hpa@zytor.com, corbet@lwn.net, bagasdotme@gmail.com, tony.luck@intel.com, yang.zhong@intel.com, linux-doc@vger.kernel.org, linux-man@vger.kernel.org, linux-kernel@vger.kernel.org, chang.seok.bae@intel.com Subject: [PATCH v5 RESEND 4/4] Documentation/x86: Explain the state component permission for guests Date: Fri, 20 Jan 2023 16:19:00 -0800 Message-Id: <20230121001900.14900-5-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230121001900.14900-1-chang.seok.bae@intel.com> References: <20220922195810.23248-1-chang.seok.bae@intel.com> <20230121001900.14900-1-chang.seok.bae@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Commit 980fe2fddcff ("x86/fpu: Extend fpu_xstate_prctl() with guest permissions") extends a couple of arch_prctl(2) options for VCPU threads. Add description for them. Signed-off-by: Chang S. Bae Reviewed-by: Thiago Macieira Reviewed-by: Yang Zhong Reviewed-by: Tony Luck Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org --- Changes from v1: * Add the reason for the guest options (Dave Hansen). * Add a note to allude some VMM policy, i.e. KVM_X86_XCOMP_GUEST_SUPP. * Move it in the separate section. Note the correspondent attributes were also proposed for the KVM API. But, it was seen as inessential: https://lore.kernel.org/lkml/20220823231402.7839-1-chang.seok.bae@intel= .com/ --- Documentation/x86/xstate.rst | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/x86/xstate.rst b/Documentation/x86/xstate.rst index 23b1c9f3efb2..ae5c69e48b11 100644 --- a/Documentation/x86/xstate.rst +++ b/Documentation/x86/xstate.rst @@ -143,3 +143,32 @@ entry if the feature is in its initial configuration. = This differs from non-dynamic features which are always written regardless of their configuration. Signal handlers can examine the XSAVE buffer's XSTATE_BV field to determine if a features was written. + +Dynamic features for virtual machines +------------------------------------- + +The permission for the guest state component needs to be managed separately +from the host, as they are exclusive to each other. A coupled of options +are extended to control the guest permission: + +-ARCH_GET_XCOMP_GUEST_PERM + + arch_prctl(ARCH_GET_XCOMP_GUEST_PERM, &features); + + ARCH_GET_XCOMP_GUEST_PERM is a variant of ARCH_GET_XCOMP_PERM. So it + provides the same semantics and functionality but for the guest + components. + +-ARCH_REQ_XCOMP_GUEST_PERM + + arch_prctl(ARCH_REQ_XCOMP_GUEST_PERM, feature_nr); + + ARCH_REQ_XCOMP_GUEST_PERM is a variant of ARCH_REQ_XCOMP_PERM. It has the + same semantics for the guest permission. While providing a similar + functionality, this comes with a constraint. Permission is frozen when the + first VCPU is created. Any attempt to change permission after that point + is going to be rejected. So, the permission has to be requested before the + first VCPU creation. + +Note that some VMMs may have already established a set of supported state +components. These options are not presumed to support any particular VMM. --=20 2.17.1