From nobody Sun Sep 14 16:09:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6048EC05027 for ; Fri, 20 Jan 2023 16:20:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229907AbjATQT6 (ORCPT ); Fri, 20 Jan 2023 11:19:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229905AbjATQTo (ORCPT ); Fri, 20 Jan 2023 11:19:44 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BAB180B87 for ; Fri, 20 Jan 2023 08:19:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674231583; x=1705767583; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RmFvrxtGvudD8BSky4Jryf7VIRfahN5fZ4oy4yAxnsg=; b=kDE/UU29btbBxTiGzPbRTZLoPKyvtbKLIIE/JfoEOnCUTEGkBIVqaGn9 thW2cz6vsSu55SBjreCyrLGWFa5cHbkahox+Wko5HwYTcdnKKkFuO33wu N2glBBojIMMJ4RQ7euxCuEWZi69AlyYzsCKHlsYKq6jtMiDhm0+3H7H/O aweUWNjx2z5HDLXPfrEyvFxCp4w1DTJtNB6dRDLrmKBPBcjDZU9os2oWG jZROOh7czVA1GRm7A7s0OSKYnLLUZ/V4a0QYappxx4pbg8GR5RPUSLtcH BPuJu+hVKOZBEot+OgWZNwvVPmH+fIL9cTwvoXtw40JNpZHyVmegalypS g==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411846591" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="411846591" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:39 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="653836377" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="653836377" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:37 -0800 From: Ashok Raj To: Boris Petkov , Thomas Gleixner Cc: Ashok Raj , LKML , x86 , Ingo Molnar , Tony Luck , Dave Hansen , Alison Schofield , Reinette Chatre , Tom Lendacky , Stefan Talpalaru , David Woodhouse , Benjamin Herrenschmidt , Jonathan Corbet , "Rafael J . Wysocki" , Peter Zilstra , Andy Lutomirski , Andrew Cooper , Boris Ostrovsky Subject: [Patch v5 5/5] x86/microcode/intel: Print old and new rev during early boot Date: Fri, 20 Jan 2023 08:19:23 -0800 Message-Id: <20230120161923.118882-6-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230120161923.118882-1-ashok.raj@intel.com> References: <20230120161923.118882-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make early loading message to match late loading messages. Print both old and new revisions. This is helpful to know what the BIOS loaded revision is before an early update. New dmesg log is shown below. microcode: early update: 0x2b000041 -> 0x2b000070 date =3D 2000-01-01 Cache the early BIOS revision before the microcode update and change the print_ucode_info() so it prints both the old and new revision in the same format as microcode_reload_late(). Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner Cc: LKML Cc: x86 Cc: Ingo Molnar Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner (Intel) Cc: Tom Lendacky Cc: Stefan Talpalaru Cc: David Woodhouse Cc: Benjamin Herrenschmidt Cc: Jonathan Corbet Cc: Rafael J. Wysocki Cc: Peter Zilstra (Intel) Cc: Andy Lutomirski Cc: Andrew Cooper Cc: Boris Ostrovsky --- Updates since V1: Thomas: Commit log updates as suggested. --- arch/x86/kernel/cpu/microcode/intel.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 146a60a9449a..4471d418f28a 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,10 +310,10 @@ static bool load_builtin_intel_microcode(struct cpio_= data *cp) /* * Print ucode update info. */ -static void print_ucode_info(unsigned int new_rev, unsigned int date) +static void print_ucode_info(int old_rev, int new_rev, unsigned int date) { - pr_info_once("microcode updated early to revision 0x%x, date =3D %04x-%02= x-%02x\n", - new_rev, date & 0xffff, date >> 24, + pr_info_once("early update: 0x%x -> 0x%x, date =3D %04x-%02x-%02x\n", + old_rev, new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } =20 @@ -321,6 +321,7 @@ static void print_ucode_info(unsigned int new_rev, unsi= gned int date) =20 static int delay_ucode_info; static int current_mc_date; +static int early_old_rev; =20 /* * Print early updated ucode info after printk works. This is delayed info= dump. @@ -331,7 +332,7 @@ void show_ucode_info_early(void) =20 if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(uci.cpu_sig.rev, current_mc_date); + print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); delay_ucode_info =3D 0; } } @@ -340,29 +341,32 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode i= nfo in * show_ucode_info_early() until printk() works. */ -static void print_ucode(int new_rev, int date) +static void print_ucode(int old_rev, int new_rev, int date) { int *delay_ucode_info_p; int *current_mc_date_p; + int *early_old_rev_p; =20 delay_ucode_info_p =3D (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p =3D (int *)__pa_nodebug(¤t_mc_date); + early_old_rev_p =3D (int *)__pa_nodebug(&early_old_rev); =20 *delay_ucode_info_p =3D 1; *current_mc_date_p =3D date; + *early_old_rev_p =3D old_rev; } #else =20 -static inline void print_ucode(int new_rev, int date) +static inline void print_ucode(int old_rev, int new_rev, int date) { - print_ucode_info(new_rev, date); + print_ucode_info(old_rev, new_rev, date); } #endif =20 static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; - u32 rev; + u32 rev, old_rev; =20 mc =3D uci->mc; if (!mc) @@ -388,6 +392,7 @@ static int apply_microcode_early(struct ucode_cpu_info = *uci, bool early) /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); =20 + old_rev =3D rev; rev =3D intel_get_microcode_revision(); if (rev !=3D mc->hdr.rev) return -1; @@ -395,9 +400,9 @@ static int apply_microcode_early(struct ucode_cpu_info = *uci, bool early) uci->cpu_sig.rev =3D rev; =20 if (early) - print_ucode(uci->cpu_sig.rev, mc->hdr.date); + print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); + print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); =20 return 0; } --=20 2.34.1