From nobody Sun Sep 14 16:08:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A959C05027 for ; Fri, 20 Jan 2023 16:19:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229957AbjATQTv (ORCPT ); Fri, 20 Jan 2023 11:19:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229674AbjATQTm (ORCPT ); Fri, 20 Jan 2023 11:19:42 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FB117EE4 for ; Fri, 20 Jan 2023 08:19:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674231581; x=1705767581; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hW/mmXgPQePcN9cL5PTH19NmnMicaiGlNPe23TbIMaw=; b=mTaCr0s2hXTtgqShq53vdSEki0tHmt2u0+v66aukOIPrlXjZDLLEJszM O+Pr+XDZ6hDqcR0HIwd1eOlk5UPE7UNldnkv8V8E8sCqfKMvtZfSUoCqi bmY8akH3GDDKSQ4Pj9vfiX6DpyjeJj6Z3nuI80/W0nLocp+6Wrc3J59kh i3FunUBdZcnnQ04rTaJ5oMdz624nVsu4kgyPg0UaU7gLAaJBQehwqTDMb I18QmbuKTrdCpPCTrjghPEIWIPR0sKtXK58eKmCTFIX/E/AWPuY/4ps0e 4cn1Gt2ibHZ66MXHmVa0z0miG7p9rMIH+oiCig+xy8i3n2pclco9IC3Mu g==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411846562" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="411846562" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:38 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="653836369" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="653836369" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:37 -0800 From: Ashok Raj To: Boris Petkov , Thomas Gleixner Cc: Ashok Raj , LKML , x86 , Ingo Molnar , Tony Luck , Dave Hansen , Alison Schofield , Reinette Chatre , Tom Lendacky , Stefan Talpalaru , David Woodhouse , Benjamin Herrenschmidt , Jonathan Corbet , "Rafael J . Wysocki" , Peter Zilstra , Andy Lutomirski , Andrew Cooper , Boris Ostrovsky Subject: [Patch v5 2/5] x86/microcode/core: Take a snapshot before and after applying microcode Date: Fri, 20 Jan 2023 08:19:20 -0800 Message-Id: <20230120161923.118882-3-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230120161923.118882-1-ashok.raj@intel.com> References: <20230120161923.118882-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The kernel caches features about each CPU's features at boot in an x86_capability[] structure. The microcode update takes one snapshot and compares it with the saved copy at boot. However, the capabilities in the boot copy can be turned off as a result of certain command line parameters or configuration restrictions. This can cause a mismatch when comparing the values before and after the microcode update. microcode_check() is called after an update to report any previously cached CPUID bits might have changed due to the update. store_cpu_caps() basically stores the original CPU reported values and not the OS modified values. This will avoid giving a false warning even when no capabilities have changed. Ignore the capabilities recorded at boot. Take a new snapshot before the update and compare with a snapshot after the update to eliminate the false warning. Signed-off-by: Ashok Raj Fixes: 1008c52c09dc ("x86/CPU: Add a microcode loader callback") Cc: LKML Cc: x86 Cc: Ingo Molnar Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner (Intel) Cc: Tom Lendacky Cc: Stefan Talpalaru Cc: David Woodhouse Cc: Benjamin Herrenschmidt Cc: Jonathan Corbet Cc: Rafael J. Wysocki Cc: Peter Zilstra (Intel) Cc: Andy Lutomirski Cc: Andrew Cooper Cc: Boris Ostrovsky --- Changes since V3: - Boris - Change function from microcode_store_cpu_caps -> store_cpu_caps - Split comments in store_cpu_caps(). - Dave Hansen - Change parameters names to something meaninful. - Cleaned up some commit log. Changes since V2: - Boris - Keep microcode_check() inside cpu/common.c and not bleed get_cpu_caps() outside of core code. - Thomas - Commit log changes. --- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/common.c | 39 ++++++++++++++++++++-------- arch/x86/kernel/cpu/microcode/core.c | 7 +++++ 3 files changed, 36 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index f256a4ddd25d..a77dee6a2bf2 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -698,6 +698,7 @@ bool xen_set_default_idle(void); =20 void __noreturn stop_this_cpu(void *dummy); void microcode_check(struct cpuinfo_x86 *prev_info); +void store_cpu_caps(struct cpuinfo_x86 *info); =20 enum l1tf_mitigations { L1TF_MITIGATION_OFF, diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 0f5a173d0871..f5c6feed6c26 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2297,6 +2297,29 @@ void cpu_init_secondary(void) #endif =20 #ifdef CONFIG_MICROCODE_LATE_LOADING +/** + * store_cpu_caps() - Store a snapshot of CPU capabilities + * + * Returns: None + */ +void store_cpu_caps(struct cpuinfo_x86 *curr_info) +{ + /* Reload CPUID max function as it might've changed. */ + curr_info->cpuid_level =3D cpuid_eax(0); + + /* + * Copy all capability leafs to pick up the synthetic ones + */ + memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, + sizeof(curr_info->x86_capability)); + + /* + * Capabilities copied from BSP will get overwritten + * with the snapshot below + */ + get_cpu_cap(curr_info); +} + /** * microcode_check() - Check if any CPU capabilities changed after an upda= te. * @prev_info: CPU capabilities stored before an update. @@ -2309,22 +2332,16 @@ void cpu_init_secondary(void) */ void microcode_check(struct cpuinfo_x86 *prev_info) { - perf_check_microcode(); + struct cpuinfo_x86 curr_info; =20 - /* Reload CPUID max function as it might've changed. */ - prev_info->cpuid_level =3D cpuid_eax(0); + perf_check_microcode(); =20 /* - * Copy all capability leafs to pick up the synthetic ones so that - * memcmp() below doesn't fail on that. The ones coming from CPUID will - * get overwritten in get_cpu_cap(). + * Get a snapshot of CPU capabilities */ - memcpy(&prev_info->x86_capability, &boot_cpu_data.x86_capability, - sizeof(prev_info->x86_capability)); - - get_cpu_cap(prev_info); + store_cpu_caps(&curr_info); =20 - if (!memcmp(&prev_info->x86_capability, &boot_cpu_data.x86_capability, + if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, sizeof(prev_info->x86_capability))) return; =20 diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index e39d83be794b..bb943a91a364 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -447,6 +447,13 @@ static int microcode_reload_late(void) atomic_set(&late_cpus_in, 0); atomic_set(&late_cpus_out, 0); =20 + /* + * Take a snapshot before the microcode update, so we can compare + * them after the update is successful to check for any bits + * changed. + */ + store_cpu_caps(&prev_info); + ret =3D stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret =3D=3D 0) microcode_check(&prev_info); --=20 2.34.1