From nobody Sun Sep 14 14:26:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89487C25B4E for ; Fri, 20 Jan 2023 16:19:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229899AbjATQTo (ORCPT ); Fri, 20 Jan 2023 11:19:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229631AbjATQTl (ORCPT ); Fri, 20 Jan 2023 11:19:41 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 598577A8D for ; Fri, 20 Jan 2023 08:19:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674231580; x=1705767580; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ln3922WzqwFOb1wmU3cZl9JGmSn0AMZmtenFituTbpU=; b=MkftYn+UCfcO+kxC5k+jDEgT4mVAqDEKMkeb8bEF3nO532dkG4+bDE9r 2h/VWMI24SErvTR6/d7E6S0OufJlzMhA97+b1wYVMZQeM5w6JHIt03QeE 3xM5TnzQJ718syGrXUazdCiK+MF8MxwAPwxDFTinbbDgLXHajO2zZBUVR ZPANOt3QShUNevZj+sdstGCvvBzRtuEUwRpCZ+I7vmTmonIFlr1KtbgOE yG80onlwgtUo8fSrUspbTCBK0gFXoSxXfC+NIcYDMGFZOoC2F3fAq0rlM lXbO9duIdW7yG2JUQorGJTfXiema95JE/DNM3f4AfsldI4QjKzL7jn6O7 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411846555" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="411846555" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:38 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="653836366" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="653836366" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:37 -0800 From: Ashok Raj To: Boris Petkov , Thomas Gleixner Cc: Ashok Raj , LKML , x86 , Ingo Molnar , Tony Luck , Dave Hansen , Alison Schofield , Reinette Chatre , Tom Lendacky , Stefan Talpalaru , David Woodhouse , Benjamin Herrenschmidt , Jonathan Corbet , "Rafael J . Wysocki" , Peter Zilstra , Andy Lutomirski , Andrew Cooper , Boris Ostrovsky Subject: [Patch v5 1/5] x86/microcode: Add a parameter to microcode_check() to store CPU capabilities Date: Fri, 20 Jan 2023 08:19:19 -0800 Message-Id: <20230120161923.118882-2-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230120161923.118882-1-ashok.raj@intel.com> References: <20230120161923.118882-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a parameter to store CPU capabilities before performing a microcode update so that the code later can compare CPU capabilities before and after performing the update. Signed-off-by: Ashok Raj Cc: LKML Cc: LKML Cc: x86 Cc: Ingo Molnar Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner (Intel) Cc: Tom Lendacky Cc: Stefan Talpalaru Cc: David Woodhouse Cc: Benjamin Herrenschmidt Cc: Jonathan Corbet Cc: Rafael J. Wysocki Cc: Peter Zilstra (Intel) Cc: Andy Lutomirski Cc: Andrew Cooper Cc: Boris Ostrovsky --- Changes since V3 Boris: - Fix commit log to drop "next patch". - Add documentation to new parameter to microcode_check() --- arch/x86/include/asm/processor.h | 2 +- arch/x86/kernel/cpu/common.c | 21 +++++++++++++-------- arch/x86/kernel/cpu/microcode/core.c | 3 ++- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index 4e35c66edeb7..f256a4ddd25d 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -697,7 +697,7 @@ bool xen_set_default_idle(void); #endif =20 void __noreturn stop_this_cpu(void *dummy); -void microcode_check(void); +void microcode_check(struct cpuinfo_x86 *prev_info); =20 enum l1tf_mitigations { L1TF_MITIGATION_OFF, diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9cfca3d7d0e2..0f5a173d0871 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2297,30 +2297,35 @@ void cpu_init_secondary(void) #endif =20 #ifdef CONFIG_MICROCODE_LATE_LOADING -/* +/** + * microcode_check() - Check if any CPU capabilities changed after an upda= te. + * @prev_info: CPU capabilities stored before an update. + * * The microcode loader calls this upon late microcode load to recheck fea= tures, * only when microcode has been updated. Caller holds microcode_mutex and = CPU * hotplug lock. + * + * Return: None */ -void microcode_check(void) +void microcode_check(struct cpuinfo_x86 *prev_info) { - struct cpuinfo_x86 info; - perf_check_microcode(); =20 /* Reload CPUID max function as it might've changed. */ - info.cpuid_level =3D cpuid_eax(0); + prev_info->cpuid_level =3D cpuid_eax(0); =20 /* * Copy all capability leafs to pick up the synthetic ones so that * memcmp() below doesn't fail on that. The ones coming from CPUID will * get overwritten in get_cpu_cap(). */ - memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x= 86_capability)); + memcpy(&prev_info->x86_capability, &boot_cpu_data.x86_capability, + sizeof(prev_info->x86_capability)); =20 - get_cpu_cap(&info); + get_cpu_cap(prev_info); =20 - if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(i= nfo.x86_capability))) + if (!memcmp(&prev_info->x86_capability, &boot_cpu_data.x86_capability, + sizeof(prev_info->x86_capability))) return; =20 pr_warn("x86/CPU: CPU features have changed after loading microcode, but = might not take effect.\n"); diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index c4cd7328177b..e39d83be794b 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -439,6 +439,7 @@ static int __reload_late(void *info) static int microcode_reload_late(void) { int old =3D boot_cpu_data.microcode, ret; + struct cpuinfo_x86 prev_info; =20 pr_err("Attempting late microcode loading - it is dangerous and taints th= e kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); @@ -448,7 +449,7 @@ static int microcode_reload_late(void) =20 ret =3D stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret =3D=3D 0) - microcode_check(); + microcode_check(&prev_info); =20 pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); --=20 2.34.1 From nobody Sun Sep 14 14:26:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A959C05027 for ; Fri, 20 Jan 2023 16:19:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229957AbjATQTv (ORCPT ); Fri, 20 Jan 2023 11:19:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229674AbjATQTm (ORCPT ); Fri, 20 Jan 2023 11:19:42 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FB117EE4 for ; Fri, 20 Jan 2023 08:19:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674231581; x=1705767581; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hW/mmXgPQePcN9cL5PTH19NmnMicaiGlNPe23TbIMaw=; b=mTaCr0s2hXTtgqShq53vdSEki0tHmt2u0+v66aukOIPrlXjZDLLEJszM O+Pr+XDZ6hDqcR0HIwd1eOlk5UPE7UNldnkv8V8E8sCqfKMvtZfSUoCqi bmY8akH3GDDKSQ4Pj9vfiX6DpyjeJj6Z3nuI80/W0nLocp+6Wrc3J59kh i3FunUBdZcnnQ04rTaJ5oMdz624nVsu4kgyPg0UaU7gLAaJBQehwqTDMb I18QmbuKTrdCpPCTrjghPEIWIPR0sKtXK58eKmCTFIX/E/AWPuY/4ps0e 4cn1Gt2ibHZ66MXHmVa0z0miG7p9rMIH+oiCig+xy8i3n2pclco9IC3Mu g==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411846562" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="411846562" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:38 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="653836369" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="653836369" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:37 -0800 From: Ashok Raj To: Boris Petkov , Thomas Gleixner Cc: Ashok Raj , LKML , x86 , Ingo Molnar , Tony Luck , Dave Hansen , Alison Schofield , Reinette Chatre , Tom Lendacky , Stefan Talpalaru , David Woodhouse , Benjamin Herrenschmidt , Jonathan Corbet , "Rafael J . Wysocki" , Peter Zilstra , Andy Lutomirski , Andrew Cooper , Boris Ostrovsky Subject: [Patch v5 2/5] x86/microcode/core: Take a snapshot before and after applying microcode Date: Fri, 20 Jan 2023 08:19:20 -0800 Message-Id: <20230120161923.118882-3-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230120161923.118882-1-ashok.raj@intel.com> References: <20230120161923.118882-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The kernel caches features about each CPU's features at boot in an x86_capability[] structure. The microcode update takes one snapshot and compares it with the saved copy at boot. However, the capabilities in the boot copy can be turned off as a result of certain command line parameters or configuration restrictions. This can cause a mismatch when comparing the values before and after the microcode update. microcode_check() is called after an update to report any previously cached CPUID bits might have changed due to the update. store_cpu_caps() basically stores the original CPU reported values and not the OS modified values. This will avoid giving a false warning even when no capabilities have changed. Ignore the capabilities recorded at boot. Take a new snapshot before the update and compare with a snapshot after the update to eliminate the false warning. Signed-off-by: Ashok Raj Fixes: 1008c52c09dc ("x86/CPU: Add a microcode loader callback") Cc: LKML Cc: x86 Cc: Ingo Molnar Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner (Intel) Cc: Tom Lendacky Cc: Stefan Talpalaru Cc: David Woodhouse Cc: Benjamin Herrenschmidt Cc: Jonathan Corbet Cc: Rafael J. Wysocki Cc: Peter Zilstra (Intel) Cc: Andy Lutomirski Cc: Andrew Cooper Cc: Boris Ostrovsky --- Changes since V3: - Boris - Change function from microcode_store_cpu_caps -> store_cpu_caps - Split comments in store_cpu_caps(). - Dave Hansen - Change parameters names to something meaninful. - Cleaned up some commit log. Changes since V2: - Boris - Keep microcode_check() inside cpu/common.c and not bleed get_cpu_caps() outside of core code. - Thomas - Commit log changes. --- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/common.c | 39 ++++++++++++++++++++-------- arch/x86/kernel/cpu/microcode/core.c | 7 +++++ 3 files changed, 36 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index f256a4ddd25d..a77dee6a2bf2 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -698,6 +698,7 @@ bool xen_set_default_idle(void); =20 void __noreturn stop_this_cpu(void *dummy); void microcode_check(struct cpuinfo_x86 *prev_info); +void store_cpu_caps(struct cpuinfo_x86 *info); =20 enum l1tf_mitigations { L1TF_MITIGATION_OFF, diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 0f5a173d0871..f5c6feed6c26 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2297,6 +2297,29 @@ void cpu_init_secondary(void) #endif =20 #ifdef CONFIG_MICROCODE_LATE_LOADING +/** + * store_cpu_caps() - Store a snapshot of CPU capabilities + * + * Returns: None + */ +void store_cpu_caps(struct cpuinfo_x86 *curr_info) +{ + /* Reload CPUID max function as it might've changed. */ + curr_info->cpuid_level =3D cpuid_eax(0); + + /* + * Copy all capability leafs to pick up the synthetic ones + */ + memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, + sizeof(curr_info->x86_capability)); + + /* + * Capabilities copied from BSP will get overwritten + * with the snapshot below + */ + get_cpu_cap(curr_info); +} + /** * microcode_check() - Check if any CPU capabilities changed after an upda= te. * @prev_info: CPU capabilities stored before an update. @@ -2309,22 +2332,16 @@ void cpu_init_secondary(void) */ void microcode_check(struct cpuinfo_x86 *prev_info) { - perf_check_microcode(); + struct cpuinfo_x86 curr_info; =20 - /* Reload CPUID max function as it might've changed. */ - prev_info->cpuid_level =3D cpuid_eax(0); + perf_check_microcode(); =20 /* - * Copy all capability leafs to pick up the synthetic ones so that - * memcmp() below doesn't fail on that. The ones coming from CPUID will - * get overwritten in get_cpu_cap(). + * Get a snapshot of CPU capabilities */ - memcpy(&prev_info->x86_capability, &boot_cpu_data.x86_capability, - sizeof(prev_info->x86_capability)); - - get_cpu_cap(prev_info); + store_cpu_caps(&curr_info); =20 - if (!memcmp(&prev_info->x86_capability, &boot_cpu_data.x86_capability, + if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, sizeof(prev_info->x86_capability))) return; =20 diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index e39d83be794b..bb943a91a364 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -447,6 +447,13 @@ static int microcode_reload_late(void) atomic_set(&late_cpus_in, 0); atomic_set(&late_cpus_out, 0); =20 + /* + * Take a snapshot before the microcode update, so we can compare + * them after the update is successful to check for any bits + * changed. + */ + store_cpu_caps(&prev_info); + ret =3D stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret =3D=3D 0) microcode_check(&prev_info); --=20 2.34.1 From nobody Sun Sep 14 14:26:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E72EC25B4E for ; Fri, 20 Jan 2023 16:19:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230010AbjATQTy (ORCPT ); Fri, 20 Jan 2023 11:19:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229769AbjATQTn (ORCPT ); Fri, 20 Jan 2023 11:19:43 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B5C226843 for ; Fri, 20 Jan 2023 08:19:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674231582; x=1705767582; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9CCNdlSDny/3dQlb/K05NLxYiooqDXz3qOp5IJDFRMY=; b=aeKAwwdT4HMTcimJKJjbnqtESFzVp/UFjphlRf0jPJB+c9N6yqEichJ4 N9SdT+vrnLsv1MfzxZO6rYPgMAET+gVAmJVdLetlXs9GJ+WSgsSuMgwil wAKrFg53JMBu4dErAw0Fo5Wlix0EGGYydp0o59GRFEKoJPxk+KPejRjAv vVHZ1+RD3fZNfz7+3TJ0+kCfYV6/h4e7ylfVzDP2MVBFsunFDginkD7FR 5vJU2lL6OBIIaNsg6Gy7zU+YpAONvq+XPOdIXGxIlWgXBjCLHqHGt0l+4 LkPTCU+jSwVAilHzjUa3IdF1+UlPEAgGrPCmDad14Pw/72vEe5Zuhdi22 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411846577" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="411846577" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:38 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="653836372" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="653836372" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:37 -0800 From: Ashok Raj To: Boris Petkov , Thomas Gleixner Cc: Ashok Raj , Tony Luck , LKML , x86 , Ingo Molnar , Dave Hansen , Alison Schofield , Reinette Chatre , Tom Lendacky , Stefan Talpalaru , David Woodhouse , Benjamin Herrenschmidt , Jonathan Corbet , "Rafael J . Wysocki" , Peter Zilstra , Andy Lutomirski , Andrew Cooper , Boris Ostrovsky Subject: [Patch v5 3/5] x86/microcode: Display revisions only when update is successful Date: Fri, 20 Jan 2023 08:19:21 -0800 Message-Id: <20230120161923.118882-4-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230120161923.118882-1-ashok.raj@intel.com> References: <20230120161923.118882-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Right now, microcode loading failures and successes print the same message "Reloading completed". This is misleading to users. Display the updated revision number only if an update was successful. Display "Reload completed" only if the update was successful, otherwise report the update failed. Signed-off-by: Ashok Raj Fixes: 9bd681251b7c ("x86/microcode: Announce reload operation's completion= ") Suggested-by: Thomas Gleixner Reviewed-by: Tony Luck Link: https://lore.kernel.org/lkml/874judpqqd.ffs@tglx/ Cc: LKML Cc: x86 Cc: Ingo Molnar Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner (Intel) Cc: Tom Lendacky Cc: Stefan Talpalaru Cc: David Woodhouse Cc: Benjamin Herrenschmidt Cc: Jonathan Corbet Cc: Rafael J. Wysocki Cc: Peter Zilstra (Intel) Cc: Andy Lutomirski Cc: Andrew Cooper Cc: Boris Ostrovsky --- Changes since V3: Tony, Ingo - Print clear message if the update was successful or not. --- arch/x86/kernel/cpu/microcode/core.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index bb943a91a364..d7cbc83df9b6 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -455,11 +455,15 @@ static int microcode_reload_late(void) store_cpu_caps(&prev_info); =20 ret =3D stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); - if (ret =3D=3D 0) - microcode_check(&prev_info); =20 - pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", - old, boot_cpu_data.microcode); + if (ret =3D=3D 0) { + pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", + old, boot_cpu_data.microcode); + microcode_check(&prev_info); + } else { + pr_info("Reload failed, current microcode revision: 0x%x\n", + boot_cpu_data.microcode); + } =20 return ret; } --=20 2.34.1 From nobody Sun Sep 14 14:26:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73D6BC05027 for ; Fri, 20 Jan 2023 16:20:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230045AbjATQUB (ORCPT ); Fri, 20 Jan 2023 11:20:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229786AbjATQTo (ORCPT ); Fri, 20 Jan 2023 11:19:44 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E13429400 for ; Fri, 20 Jan 2023 08:19:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674231582; x=1705767582; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mcr2yb7ZiR1idAR8ZlgAQTtq4p4cCDWrTt1cLCmxsGY=; b=h2JSc0SAvWzTDBngDGV9o8YI7DRPqAl4spqq2ulV+9cZPU9d6PExfP9Z 2lZlH/W0taU09oOIE+BIbOAyWbW3k+Xt+kZ0X1781pUak3jh6F8Q65m0j 8hRI0jn4RIGm3BjLV1G22hwUqFlhOK4u8UNkjHEa/reCTMa4vLdkNo2hr ieZVhf3UXvhrt0C2vSU3drY6Lf7+ZIXbZrtgjHi+siKX1nmlBJmLZy36G LcpmITW2smRRyldjdnDtXkQtsJr0ad+prin+SOu8gnNyQitt1M3BmVH6f gytBhTgQslOfd2kaM+f3FAWR7hgJmyhc8q1i5/IzkDxC4s5TfVTTs8Vvn w==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411846589" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="411846589" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:38 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="653836375" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="653836375" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:37 -0800 From: Ashok Raj To: Boris Petkov , Thomas Gleixner Cc: Ashok Raj , LKML , x86 , Ingo Molnar , Tony Luck , Dave Hansen , Alison Schofield , Reinette Chatre , Tom Lendacky , Stefan Talpalaru , David Woodhouse , Benjamin Herrenschmidt , Jonathan Corbet , "Rafael J . Wysocki" , Peter Zilstra , Andy Lutomirski , Andrew Cooper , Boris Ostrovsky Subject: [Patch v5 4/5] x86/microcode/intel: Use a plain revision argument for print_ucode_rev() Date: Fri, 20 Jan 2023 08:19:22 -0800 Message-Id: <20230120161923.118882-5-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230120161923.118882-1-ashok.raj@intel.com> References: <20230120161923.118882-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" print_ucode_rev() takes a struct ucode_cpu_info argument. The sole purpose of it is to print the microcode revision. The only available ucode_cpu_info always describes the currently loaded microcode revision. After a microcode update is successful, this is the new revision, or on failure it is the original revision. Subsequent changes need to print both the original and new revision, but the original version will be cached in a plain integer, which makes the code inconsistent. Replace the struct ucode_cpu_info argument with a plain integer which contains the revision number and adjust the call sites accordingly. No functional change. Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner Cc: LKML Cc: x86 Cc: Ingo Molnar Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner (Intel) Cc: Tom Lendacky Cc: Stefan Talpalaru Cc: David Woodhouse Cc: Benjamin Herrenschmidt Cc: Jonathan Corbet Cc: Rafael J. Wysocki Cc: Peter Zilstra (Intel) Cc: Andy Lutomirski Cc: Andrew Cooper Cc: Boris Ostrovsky --- Changes since v4: Boris: - Removed unused variable mc, and fixed compile error in show_ucode_info_early() Changes since V1: Thomas: - Updated commit log as suggested - Remove the line break after static void before print_ucode_info --- arch/x86/kernel/cpu/microcode/intel.c | 32 ++++++++------------------- 1 file changed, 9 insertions(+), 23 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 6bebc46ad8b1..146a60a9449a 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,13 +310,10 @@ static bool load_builtin_intel_microcode(struct cpio_= data *cp) /* * Print ucode update info. */ -static void -print_ucode_info(struct ucode_cpu_info *uci, unsigned int date) +static void print_ucode_info(unsigned int new_rev, unsigned int date) { pr_info_once("microcode updated early to revision 0x%x, date =3D %04x-%02= x-%02x\n", - uci->cpu_sig.rev, - date & 0xffff, - date >> 24, + new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } =20 @@ -334,7 +331,7 @@ void show_ucode_info_early(void) =20 if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(&uci, current_mc_date); + print_ucode_info(uci.cpu_sig.rev, current_mc_date); delay_ucode_info =3D 0; } } @@ -343,33 +340,22 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode i= nfo in * show_ucode_info_early() until printk() works. */ -static void print_ucode(struct ucode_cpu_info *uci) +static void print_ucode(int new_rev, int date) { - struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; =20 - mc =3D uci->mc; - if (!mc) - return; - delay_ucode_info_p =3D (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p =3D (int *)__pa_nodebug(¤t_mc_date); =20 *delay_ucode_info_p =3D 1; - *current_mc_date_p =3D mc->hdr.date; + *current_mc_date_p =3D date; } #else =20 -static inline void print_ucode(struct ucode_cpu_info *uci) +static inline void print_ucode(int new_rev, int date) { - struct microcode_intel *mc; - - mc =3D uci->mc; - if (!mc) - return; - - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(new_rev, date); } #endif =20 @@ -409,9 +395,9 @@ static int apply_microcode_early(struct ucode_cpu_info = *uci, bool early) uci->cpu_sig.rev =3D rev; =20 if (early) - print_ucode(uci); + print_ucode(uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); =20 return 0; } --=20 2.34.1 From nobody Sun Sep 14 14:26:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6048EC05027 for ; Fri, 20 Jan 2023 16:20:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229907AbjATQT6 (ORCPT ); Fri, 20 Jan 2023 11:19:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229905AbjATQTo (ORCPT ); Fri, 20 Jan 2023 11:19:44 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BAB180B87 for ; Fri, 20 Jan 2023 08:19:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674231583; x=1705767583; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RmFvrxtGvudD8BSky4Jryf7VIRfahN5fZ4oy4yAxnsg=; b=kDE/UU29btbBxTiGzPbRTZLoPKyvtbKLIIE/JfoEOnCUTEGkBIVqaGn9 thW2cz6vsSu55SBjreCyrLGWFa5cHbkahox+Wko5HwYTcdnKKkFuO33wu N2glBBojIMMJ4RQ7euxCuEWZi69AlyYzsCKHlsYKq6jtMiDhm0+3H7H/O aweUWNjx2z5HDLXPfrEyvFxCp4w1DTJtNB6dRDLrmKBPBcjDZU9os2oWG jZROOh7czVA1GRm7A7s0OSKYnLLUZ/V4a0QYappxx4pbg8GR5RPUSLtcH BPuJu+hVKOZBEot+OgWZNwvVPmH+fIL9cTwvoXtw40JNpZHyVmegalypS g==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411846591" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="411846591" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:39 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="653836377" X-IronPort-AV: E=Sophos;i="5.97,232,1669104000"; d="scan'208";a="653836377" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 08:19:37 -0800 From: Ashok Raj To: Boris Petkov , Thomas Gleixner Cc: Ashok Raj , LKML , x86 , Ingo Molnar , Tony Luck , Dave Hansen , Alison Schofield , Reinette Chatre , Tom Lendacky , Stefan Talpalaru , David Woodhouse , Benjamin Herrenschmidt , Jonathan Corbet , "Rafael J . Wysocki" , Peter Zilstra , Andy Lutomirski , Andrew Cooper , Boris Ostrovsky Subject: [Patch v5 5/5] x86/microcode/intel: Print old and new rev during early boot Date: Fri, 20 Jan 2023 08:19:23 -0800 Message-Id: <20230120161923.118882-6-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230120161923.118882-1-ashok.raj@intel.com> References: <20230120161923.118882-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make early loading message to match late loading messages. Print both old and new revisions. This is helpful to know what the BIOS loaded revision is before an early update. New dmesg log is shown below. microcode: early update: 0x2b000041 -> 0x2b000070 date =3D 2000-01-01 Cache the early BIOS revision before the microcode update and change the print_ucode_info() so it prints both the old and new revision in the same format as microcode_reload_late(). Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner Cc: LKML Cc: x86 Cc: Ingo Molnar Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner (Intel) Cc: Tom Lendacky Cc: Stefan Talpalaru Cc: David Woodhouse Cc: Benjamin Herrenschmidt Cc: Jonathan Corbet Cc: Rafael J. Wysocki Cc: Peter Zilstra (Intel) Cc: Andy Lutomirski Cc: Andrew Cooper Cc: Boris Ostrovsky --- Updates since V1: Thomas: Commit log updates as suggested. --- arch/x86/kernel/cpu/microcode/intel.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 146a60a9449a..4471d418f28a 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,10 +310,10 @@ static bool load_builtin_intel_microcode(struct cpio_= data *cp) /* * Print ucode update info. */ -static void print_ucode_info(unsigned int new_rev, unsigned int date) +static void print_ucode_info(int old_rev, int new_rev, unsigned int date) { - pr_info_once("microcode updated early to revision 0x%x, date =3D %04x-%02= x-%02x\n", - new_rev, date & 0xffff, date >> 24, + pr_info_once("early update: 0x%x -> 0x%x, date =3D %04x-%02x-%02x\n", + old_rev, new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } =20 @@ -321,6 +321,7 @@ static void print_ucode_info(unsigned int new_rev, unsi= gned int date) =20 static int delay_ucode_info; static int current_mc_date; +static int early_old_rev; =20 /* * Print early updated ucode info after printk works. This is delayed info= dump. @@ -331,7 +332,7 @@ void show_ucode_info_early(void) =20 if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(uci.cpu_sig.rev, current_mc_date); + print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); delay_ucode_info =3D 0; } } @@ -340,29 +341,32 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode i= nfo in * show_ucode_info_early() until printk() works. */ -static void print_ucode(int new_rev, int date) +static void print_ucode(int old_rev, int new_rev, int date) { int *delay_ucode_info_p; int *current_mc_date_p; + int *early_old_rev_p; =20 delay_ucode_info_p =3D (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p =3D (int *)__pa_nodebug(¤t_mc_date); + early_old_rev_p =3D (int *)__pa_nodebug(&early_old_rev); =20 *delay_ucode_info_p =3D 1; *current_mc_date_p =3D date; + *early_old_rev_p =3D old_rev; } #else =20 -static inline void print_ucode(int new_rev, int date) +static inline void print_ucode(int old_rev, int new_rev, int date) { - print_ucode_info(new_rev, date); + print_ucode_info(old_rev, new_rev, date); } #endif =20 static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; - u32 rev; + u32 rev, old_rev; =20 mc =3D uci->mc; if (!mc) @@ -388,6 +392,7 @@ static int apply_microcode_early(struct ucode_cpu_info = *uci, bool early) /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); =20 + old_rev =3D rev; rev =3D intel_get_microcode_revision(); if (rev !=3D mc->hdr.rev) return -1; @@ -395,9 +400,9 @@ static int apply_microcode_early(struct ucode_cpu_info = *uci, bool early) uci->cpu_sig.rev =3D rev; =20 if (early) - print_ucode(uci->cpu_sig.rev, mc->hdr.date); + print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); + print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); =20 return 0; } --=20 2.34.1