From nobody Sat Sep 21 07:27:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FE51C25B50 for ; Fri, 20 Jan 2023 09:22:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230309AbjATJW1 (ORCPT ); Fri, 20 Jan 2023 04:22:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230314AbjATJVq (ORCPT ); Fri, 20 Jan 2023 04:21:46 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AC8E94327; Fri, 20 Jan 2023 01:21:19 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B78526602E16; Fri, 20 Jan 2023 09:21:09 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674206471; bh=iyGyvF4gSjXW/Me+rS7Fs3WJzATcoXZh4BloNFgcSoA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lOdCOM/dyeY4ObpgWRkuSoeUmFdrXzhML+C1Krr3RzdQI46qxoXxl48z1wKFhri3R 8mWzQ6qLx8nHMUqL7ecYs4uE8Qf9BXt58kK3I3gHjdv+nSGlHZEvLEcJkwF+d+ht8e x+34Zvxu/ifJNS4+FuTV6EuhR9PpF3+hO0bjE0DT5jnmXdRq6V16oLwgzEmUhK84U5 XLr8AY3Jrom5UtJLqV3SmFZSMqdwf2EHH9QijOcq6HxiYUaEXBLat8UTBn22RfsKtU UeFjp0OYMB7eDvH3qmVaLy0bmgdVbzlAtoYzQ9myqubyv+tLaS+cBiW3oTA5I9BLI8 CH+aE6TdpcoCg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v4 07/23] clk: mediatek: clk-mtk: Add dummy clock ops Date: Fri, 20 Jan 2023 10:20:37 +0100 Message-Id: <20230120092053.182923-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120092053.182923-1-angelogioacchino.delregno@collabora.com> References: <20230120092053.182923-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to migrate some (few) old clock drivers to the common mtk_clk_simple_probe() function, add dummy clock ops to be able to insert a dummy clock with ID 0 at the beginning of the list. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen Reviewed-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mtk.c | 16 ++++++++++++++++ drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index cf2f465ecf22..ca9aa24e769c 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -18,6 +18,22 @@ #include "clk-mtk.h" #include "clk-gate.h" =20 +const struct mtk_gate_regs cg_regs_dummy =3D { 0, 0, 0 }; +EXPORT_SYMBOL_GPL(cg_regs_dummy); + +static int mtk_clk_dummy_enable(struct clk_hw *hw) +{ + return 0; +} + +static void mtk_clk_dummy_disable(struct clk_hw *hw) { } + +const struct clk_ops mtk_clk_dummy_ops =3D { + .enable =3D mtk_clk_dummy_enable, + .disable =3D mtk_clk_dummy_disable, +}; +EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops); + static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data, unsigned int clk_num) { diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index cd97d2722380..ed329d8d7349 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -22,6 +22,25 @@ =20 struct platform_device; =20 +/* + * We need the clock IDs to start from zero but to maintain devicetree + * backwards compatibility we can't change bindings to start from zero. + * Only a few platforms are affected, so we solve issues given by the + * commonized MTK clocks probe function(s) by adding a dummy clock at + * the beginning where needed. + */ +#define CLK_DUMMY 0 + +extern const struct clk_ops mtk_clk_dummy_ops; +extern const struct mtk_gate_regs cg_regs_dummy; + +#define GATE_DUMMY(_id, _name) { \ + .id =3D _id, \ + .name =3D _name, \ + .regs =3D &cg_regs_dummy, \ + .ops =3D &mtk_clk_dummy_ops, \ + } + struct mtk_fixed_clk { int id; const char *name; --=20 2.39.0