From nobody Sat Sep 21 07:54:08 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 907B4C27C76 for ; Fri, 20 Jan 2023 09:23:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230522AbjATJXQ (ORCPT ); Fri, 20 Jan 2023 04:23:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230451AbjATJWj (ORCPT ); Fri, 20 Jan 2023 04:22:39 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 388149EE11; Fri, 20 Jan 2023 01:21:47 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E696A6602DE9; Fri, 20 Jan 2023 09:21:29 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674206491; bh=IVNkSTL1Ac045C8DuqPAkVteL1MrOc/053CjcEkcRrk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Rz5/ikVQnL5QbH1r0zchI4XE43l6EhtMlMG8k4lihf0zT6jIQ8n/Yb7VpNktwMA7N e8aCC8TCV82D3eBU0NpVQTdK0uwWAJpL2wNGzTt1RI+O97TS8qtJotSvBIZlllooOk l4zjH4mY9Z3j97e2+jE9o/M4xa29Ca8hfL6kWOKA2sL8hG12pGjhiTZPO7/GtxzVWX +eksj7h4Rdd1R8oEUspIzfceHff+HPW7BFYEhUBtsOwSKzsd1hGkxztJdFPdQ/Q/z1 /qmAZy2wOyW/wfeQPJ1ADlJbTyPDmTjLopkpZgDf0F4g1NeS8RGqL0GAjvHH9fOIgt UsgXZOW9l9ygw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v4 19/23] clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe() Date: Fri, 20 Jan 2023 10:20:49 +0100 Message-Id: <20230120092053.182923-20-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120092053.182923-1-angelogioacchino.delregno@collabora.com> References: <20230120092053.182923-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since the common simple probe function for MediaTek clock drivers can now register the MFG MUX notifier, it's possible to migrate MT8192's topckgen to that, allowing for some code size reduction. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt8192.c | 85 +++++++------------------------ 1 file changed, 17 insertions(+), 68 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index 1ffff53bbe90..61299960d28a 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1064,71 +1064,6 @@ static int clk_mt8192_reg_mfg_mux_notifier(struct de= vice *dev, struct clk *clk) return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); } =20 -static int clk_mt8192_top_probe(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *top_clk_data; - int r; - void __iomem *base; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - top_clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - if (!top_clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_cl= ks), top_clk_data); - if (r) - return r; - - r =3D mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_da= ta); - if (r) - goto unregister_fixed_clks; - - r =3D mtk_clk_register_muxes(&pdev->dev, top_mtk_muxes, - ARRAY_SIZE(top_mtk_muxes), node, - &mt8192_clk_lock, top_clk_data); - if (r) - goto unregister_factors; - - r =3D mtk_clk_register_composites(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt8192_clk_lock, top_clk_data); - if (r) - goto unregister_muxes; - - r =3D mtk_clk_register_gates(&pdev->dev, node, top_clks, - ARRAY_SIZE(top_clks), top_clk_data); - if (r) - goto unregister_top_composites; - - r =3D clk_mt8192_reg_mfg_mux_notifier(&pdev->dev, - top_clk_data->hws[CLK_TOP_MFG_PLL_SEL]->clk); - if (r) - goto unregister_gates; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); - if (r) - goto unregister_gates; - - return 0; - -unregister_gates: - mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data); -unregister_top_composites: - mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_d= ata); -unregister_muxes: - mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_cl= k_data); -unregister_factors: - mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); -unregister_fixed_clks: - mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - top_clk_data); - return r; -} - static int clk_mt8192_apmixed_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1162,9 +1097,6 @@ static const struct of_device_id of_match_clk_mt8192[= ] =3D { { .compatible =3D "mediatek,mt8192-apmixedsys", .data =3D clk_mt8192_apmixed_probe, - }, { - .compatible =3D "mediatek,mt8192-topckgen", - .data =3D clk_mt8192_top_probe, }, { /* sentinel */ } @@ -1197,9 +1129,26 @@ static const struct mtk_clk_desc peri_desc =3D { .num_clks =3D ARRAY_SIZE(peri_clks), }; =20 +static const struct mtk_clk_desc topck_desc =3D { + .fixed_clks =3D top_fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(top_fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .mux_clks =3D top_mtk_muxes, + .num_mux_clks =3D ARRAY_SIZE(top_mtk_muxes), + .composite_clks =3D top_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .clks =3D top_clks, + .num_clks =3D ARRAY_SIZE(top_clks), + .clk_lock =3D &mt8192_clk_lock, + .clk_notifier_func =3D clk_mt8192_reg_mfg_mux_notifier, + .mfg_clk_idx =3D CLK_TOP_MFG_PLL_SEL, +}; + static const struct of_device_id of_match_clk_mt8192_simple[] =3D { { .compatible =3D "mediatek,mt8192-infracfg", .data =3D &infra_desc }, { .compatible =3D "mediatek,mt8192-pericfg", .data =3D &peri_desc }, + { .compatible =3D "mediatek,mt8192-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; =20 --=20 2.39.0