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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id s5-20020a170906c30500b008552bc8399dsm18410066ejz.172.2023.01.23.05.30.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 05:30:23 -0800 (PST) From: Luca Weiss Date: Mon, 23 Jan 2023 14:29:49 +0100 Subject: [PATCH v4 1/3] dt-bindings: phy: qcom,qmp-usb3-dp: Add sm6350 compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230120-sm6350-usbphy-v4-1-4d700a90ba16@fairphone.com> References: <20230120-sm6350-usbphy-v4-0-4d700a90ba16@fairphone.com> In-Reply-To: <20230120-sm6350-usbphy-v4-0-4d700a90ba16@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Johan Hovold , Krzysztof Kozlowski X-Mailer: b4 0.12.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the compatible describing the combo phy found on SM6350. Reviewed-by: Johan Hovold Acked-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml |= 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43d= p-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43d= p-phy.yaml index 6f31693d9868..0764cd977e76 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.y= aml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.y= aml @@ -17,6 +17,7 @@ properties: compatible: enum: - qcom,sc8280xp-qmp-usb43dp-phy + - qcom,sm6350-qmp-usb3-dp-phy =20 reg: maxItems: 1 --=20 2.39.1 From nobody Sun Sep 14 11:00:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A2D1C05027 for ; Mon, 23 Jan 2023 13:30:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231501AbjAWNam (ORCPT ); Mon, 23 Jan 2023 08:30:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232052AbjAWNa3 (ORCPT ); Mon, 23 Jan 2023 08:30:29 -0500 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6514322A10 for ; Mon, 23 Jan 2023 05:30:26 -0800 (PST) Received: by mail-ej1-x62e.google.com with SMTP id az20so30528964ejc.1 for ; Mon, 23 Jan 2023 05:30:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vItZId2qjHoqHEQiookDEl4j8ijl0eOr3aln9UWpQCU=; b=SgBgxCCrYzD932YwV3j+OEWw5/eNUyc2ibTXx8y6ue0ayDYKeiIdmA247MKvw70Gcb yGFVidyLxZVzDKbydX3QWz2QaCphXcowwrK+GbQ7il3OZbY+Kdr4dhSH+fRzlPBOfXns lLFy7jgyGGf/NIG7kx8LkoZ91uGy9BLyDU5Al+iavbBP0gb7Ol1w4sKV1E0/ri1tF9o2 /8jfmpnVVAMoFgWH1EGrj6FPVUt59UMeQ0LTwZwEqtT9kS7GlK6lFTqBvD/TQB1hwx0S ktmDzJV+VMyVOyQ/Io6giCJcRlMYqOsopWDI+7TXtKw9oq83oFghcybz76Uc8bqw7zC7 R2iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vItZId2qjHoqHEQiookDEl4j8ijl0eOr3aln9UWpQCU=; b=MkdXE5EzKdH9Pyz6hRpUokRuafvyWgh4XDyMYD2LTmWxYvgJrgrgBdLj6EtjLli5C5 Yx18Cce0E9EF5zOkVkiSFYoWX5wYlo++CRwBuet0lT3HUYGSF/CXlkM2P1KQHgB9X7ne KcY/9jZJ5WI/RkjUhotbTdJAs8zPKQffb1c5kJQZCvUtq4gKHZPpzqmdY8xIu7BFKVKc W4RfaPN+wSYhhOFEvyfO0DfK7EJeI23k5oJ8P529K4Gn3e6m6mR+R+jonf5P+IMBR4ij eCyKwi0WSmA1ociBEeS2WFtZd8kwV8RbZlu+/R5B6TUtINglbfZBFUiqqJUSVDDFlhgl YuRw== X-Gm-Message-State: AFqh2krNJ/vy22ODmxUSIPwXzWkrazzu1bSzoJphFtuJT00MnoEWXqV3 znTFH0ckaTmcx5nJQaLsXYlJ5w== X-Google-Smtp-Source: AMrXdXuY9rKKiTew8gsyGNx7jQ4dFMtk0GuYbZsRrfsMqIpZ1Ciap58f3VqjQphqL25U4JIsQ8I0NA== X-Received: by 2002:a17:907:2096:b0:7c1:2075:199a with SMTP id pv22-20020a170907209600b007c12075199amr25748955ejb.76.1674480624781; Mon, 23 Jan 2023 05:30:24 -0800 (PST) Received: from [172.16.220.87] (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id s5-20020a170906c30500b008552bc8399dsm18410066ejz.172.2023.01.23.05.30.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 05:30:24 -0800 (PST) From: Luca Weiss Date: Mon, 23 Jan 2023 14:29:50 +0100 Subject: [PATCH v4 2/3] phy: qcom-qmp-combo: Add config for SM6350 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230120-sm6350-usbphy-v4-2-4d700a90ba16@fairphone.com> References: <20230120-sm6350-usbphy-v4-0-4d700a90ba16@fairphone.com> In-Reply-To: <20230120-sm6350-usbphy-v4-0-4d700a90ba16@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the tables and config for the combo phy found on SM6350. Signed-off-by: Luca Weiss Reviewed-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 139 ++++++++++++++++++++++++++= +++- 1 file changed, 137 insertions(+), 2 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 1f022e580407..82b46f4c6df0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -309,6 +309,70 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_t= bl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), }; =20 +static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), +}; + +static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] =3D { + /* FLL settings */ + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + + /* Lock Det settings */ + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), +}; + static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), @@ -807,6 +871,8 @@ struct qmp_combo_offsets { u16 usb3_pcs; u16 usb3_pcs_usb; u16 dp_serdes; + u16 dp_txa; + u16 dp_txb; u16 dp_dp_phy; }; =20 @@ -973,6 +1039,21 @@ static const char * const sc7180_usb3phy_reset_l[] = =3D { "phy", }; =20 +static const struct qmp_combo_offsets qmp_combo_offsets_v3 =3D { + .com =3D 0x0000, + .txa =3D 0x1200, + .rxa =3D 0x1400, + .txb =3D 0x1600, + .rxb =3D 0x1800, + .usb3_serdes =3D 0x1000, + .usb3_pcs_misc =3D 0x1a00, + .usb3_pcs =3D 0x1c00, + .dp_serdes =3D 0x2000, + .dp_txa =3D 0x2200, + .dp_txb =3D 0x2600, + .dp_dp_phy =3D 0x2a00, +}; + static const struct qmp_combo_offsets qmp_combo_offsets_v5 =3D { .com =3D 0x0000, .txa =3D 0x0400, @@ -1170,6 +1251,51 @@ static const struct qmp_phy_cfg sc8280xp_usb43dpphy_= cfg =3D { .regs =3D qmp_v4_usb3phy_regs_layout, }; =20 +static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg =3D { + .offsets =3D &qmp_combo_offsets_v3, + + .serdes_tbl =3D qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), + .tx_tbl =3D qmp_v3_usb3_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(qmp_v3_usb3_tx_tbl), + .rx_tbl =3D sm6350_usb3_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(sm6350_usb3_rx_tbl), + .pcs_tbl =3D sm6350_usb3_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(sm6350_usb3_pcs_tbl), + + .dp_serdes_tbl =3D qmp_v3_dp_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v3_dp_serdes_tbl), + .dp_tx_tbl =3D qmp_v3_dp_tx_tbl, + .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v3_dp_tx_tbl), + + .serdes_tbl_rbr =3D qmp_v3_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v3_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v3_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v3_dp_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), + + .swing_hbr_rbr =3D &qmp_dp_v3_voltage_swing_hbr_rbr, + .pre_emphasis_hbr_rbr =3D &qmp_dp_v3_pre_emphasis_hbr_rbr, + .swing_hbr3_hbr2 =3D &qmp_dp_v3_voltage_swing_hbr3_hbr2, + .pre_emphasis_hbr3_hbr2 =3D &qmp_dp_v3_pre_emphasis_hbr3_hbr2, + + .dp_aux_init =3D qmp_v3_dp_aux_init, + .configure_dp_tx =3D qmp_v3_configure_dp_tx, + .configure_dp_phy =3D qmp_v3_configure_dp_phy, + .calibrate_dp_phy =3D qmp_v3_calibrate_dp_phy, + + .clk_list =3D qmp_v4_phy_clk_l, + .num_clks =3D ARRAY_SIZE(qmp_v4_phy_clk_l), + .reset_list =3D msm8996_usb3phy_reset_l, + .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D qmp_v3_usb3phy_regs_layout, +}; + static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg =3D { .serdes_tbl =3D sm8150_usb3_serdes_tbl, .serdes_tbl_num =3D ARRAY_SIZE(sm8150_usb3_serdes_tbl), @@ -2639,8 +2765,13 @@ static int qmp_combo_parse_dt(struct qmp_combo *qmp) qmp->pcs_usb =3D base + offs->usb3_pcs_usb; =20 qmp->dp_serdes =3D base + offs->dp_serdes; - qmp->dp_tx =3D base + offs->txa; - qmp->dp_tx2 =3D base + offs->txb; + if (offs->dp_txa) { + qmp->dp_tx =3D base + offs->dp_txa; + qmp->dp_tx2 =3D base + offs->dp_txb; + } else { + qmp->dp_tx =3D base + offs->txa; + qmp->dp_tx2 =3D base + offs->txb; + } qmp->dp_dp_phy =3D base + offs->dp_dp_phy; =20 qmp->pipe_clk =3D devm_clk_get(dev, "usb3_pipe"); @@ -2787,6 +2918,10 @@ static const struct of_device_id qmp_combo_of_match_= table[] =3D { .compatible =3D "qcom,sdm845-qmp-usb3-dp-phy", .data =3D &sdm845_usb3dpphy_cfg, }, + { + .compatible =3D "qcom,sm6350-qmp-usb3-dp-phy", + .data =3D &sm6350_usb3dpphy_cfg, + }, { .compatible =3D "qcom,sm8250-qmp-usb3-dp-phy", .data =3D &sm8250_usb3dpphy_cfg, --=20 2.39.1 From nobody Sun Sep 14 11:00:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5225CC05027 for ; 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id s5-20020a170906c30500b008552bc8399dsm18410066ejz.172.2023.01.23.05.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 05:30:25 -0800 (PST) From: Luca Weiss Date: Mon, 23 Jan 2023 14:29:51 +0100 Subject: [PATCH v4 3/3] arm64: dts: qcom: sm6350: Use specific qmpphy compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230120-sm6350-usbphy-v4-3-4d700a90ba16@fairphone.com> References: <20230120-sm6350-usbphy-v4-0-4d700a90ba16@fairphone.com> In-Reply-To: <20230120-sm6350-usbphy-v4-0-4d700a90ba16@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Johan Hovold X-Mailer: b4 0.12.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The sc7180 phy compatible works fine for some cases, but it turns out sm6350 does need proper phy configuration in the driver, so use the newly added sm6350 compatible. Because the sm6350 compatible is using the new binding, we need to change the node quite a bit to match it. This fixes qmpphy init when no USB cable is plugged in during bootloader stage. Reviewed-by: Johan Hovold Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 54 +++++++++++---------------------= ---- 1 file changed, 16 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 8224adb99948..128dbbe23ef5 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include #include =20 @@ -1314,49 +1315,26 @@ usb_1_hsphy: phy@88e3000 { resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; }; =20 - usb_1_qmpphy: phy@88e9000 { - compatible =3D "qcom,sc7180-qmp-usb3-dp-phy"; - reg =3D <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x40>, - <0 0x088ea000 0 0x200>; - status =3D "disabled"; - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges; + usb_1_qmpphy: phy@88e8000 { + compatible =3D "qcom,sm6350-qmp-usb3-dp-phy"; + reg =3D <0 0x088e8000 0 0x3000>; =20 clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&xo_board>, - <&rpmhcc RPMH_QLINK_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names =3D "aux", "cfg_ahb", "ref", "com_aux"; + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "aux", "ref", "com_aux", "usb3_pipe"; + + power-domains =3D <&gcc USB30_PRIM_GDSC>; =20 - resets =3D <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; + resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; reset-names =3D "phy", "common"; =20 - usb_1_ssphy: usb3-phy@88e9200 { - reg =3D <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #clock-cells =3D <0>; - #phy-cells =3D <0>; - clocks =3D <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names =3D "pipe0"; - clock-output-names =3D "usb3_phy_pipe_clk_src"; - }; + #clock-cells =3D <1>; + #phy-cells =3D <1>; =20 - dp_phy: dp-phy@88ea200 { - reg =3D <0 0x088ea200 0 0x200>, - <0 0x088ea400 0 0x200>, - <0 0x088eaa00 0 0x200>, - <0 0x088ea600 0 0x200>, - <0 0x088ea800 0 0x200>; - #phy-cells =3D <0>; - #clock-cells =3D <1>; - }; + status =3D "disabled"; }; =20 dc_noc: interconnect@9160000 { @@ -1430,7 +1408,7 @@ usb_1_dwc3: usb@a600000 { snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold =3D /bits/ 8 <0x10>; - phys =3D <&usb_1_hsphy>, <&usb_1_ssphy>; + phys =3D <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names =3D "usb2-phy", "usb3-phy"; }; }; --=20 2.39.1