From nobody Sun Sep 14 18:46:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FF2DC004D4 for ; Thu, 19 Jan 2023 14:06:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231565AbjASOGe (ORCPT ); Thu, 19 Jan 2023 09:06:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231504AbjASOF4 (ORCPT ); Thu, 19 Jan 2023 09:05:56 -0500 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A20987F9B0 for ; Thu, 19 Jan 2023 06:05:23 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id g10so1632551wmo.1 for ; Thu, 19 Jan 2023 06:05:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pnjm/PMfCWBhtrU2iGU0gG9+KDqoUzC+C9XvnUy9xOc=; b=M0O7PQaCGbV0hMlBcsh03sRfPVTNskwhjem187W4uuej4J5RtyB+jYc8c2OnJJfFmC oZe/BTbbPyI2bYXggtFLLdK3G4NQw5KrE9rLIC07z4v/Tn5Ke1HTn1rk+aZtGG9MdHar SfVnXT6hXblTh9g5OhkWdQ/tVIbMGaHSnO7iLt4pnMVcEm/X8SuXJZO6Yrr5k+ocFmaw nXKB4Iw89bYgdOXW/idAPWdqGyXDtHSkWo3ME6qzizd9Hs8UqAUlATNrJaaTyvLkxHTY wBK7s6Dbtx4HjyzfBMu8SVesBOdIsPWd8nl445KGqlaflELTVG4Lw/4ZUc3UTI4SPYGq slEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pnjm/PMfCWBhtrU2iGU0gG9+KDqoUzC+C9XvnUy9xOc=; b=eyNj9mpGCgoICd2HS8EQyXRHqtBCv0PHiB8z/d5vScyFCtXE6TSOoh3LkVTPVTNCJK XMFRNSHPA95JRLK8JCKponpa7HC5Zu04sB1PmGkdThRV8JErL0EmlMhPemBxG9yl3vwG q/hrqldpv3W2xhsfXkeDvyoqidcLSB7Dd1qOgrD6Ii3B51VxUuv6JsN027bN9qOeFbdX 9VmU8DNsCFjpKEIXjXl3MmLpg83K4fRo+2FYKxH8mOOcq5mbe10afZla5/qNp5EyxCxt FKd8ttnDoqH+y49hfkPS59BvQ1Sk+gnHxtvUQKeNp1l/Ax9OMdPXwM29aiP+Fv0WLbj3 PF7g== X-Gm-Message-State: AFqh2kpUuEbBB09Vlq63+cqK3pTJ/RSZ8bEoPgoqOFF45oMKMGT1ffky lQOkGLJ0BAHXyhmskwDrGzzKzA== X-Google-Smtp-Source: AMrXdXtphli43eFWHG1PjJ2mKVvRbspfaY8ujSfwWfzIsqOG/XGx12InmUGDoNDQm10pyYnxc0FWpQ== X-Received: by 2002:a05:600c:4e05:b0:3d3:5a4a:9103 with SMTP id b5-20020a05600c4e0500b003d35a4a9103mr10304805wmq.31.1674137123398; Thu, 19 Jan 2023 06:05:23 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id m10-20020a05600c4f4a00b003d96efd09b7sm5263883wmq.19.2023.01.19.06.05.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 06:05:22 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v4 10/12] PCI: qcom: Add SM8550 PCIe support Date: Thu, 19 Jan 2023 16:04:51 +0200 Message-Id: <20230119140453.3942340-11-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230119140453.3942340-1-abel.vesa@linaro.org> References: <20230119140453.3942340-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatible for both PCIe found on SM8550. Also add the cnoc_pcie_sf_axi clock needed by the SM8550. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam --- The v3 of this patchset is: https://lore.kernel.org/all/20230119112453.3393911-1-abel.vesa@linaro.org/ Changes since v3: * renamed cnoc_pcie_sf_axi to cnoc_sf_axi Changes since v2: * none =20 Changes since v1: * changed the subject line prefix for the patch to match the history, like Bjorn Helgaas suggested. * added Konrad's R-b tag drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 77e5dc7b88ad..30f74bc51dbf 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 { =20 /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[13]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_= pcie *pcie) res->clks[idx++].id =3D "noc_aggr_4"; res->clks[idx++].id =3D "noc_aggr_south_sf"; res->clks[idx++].id =3D "cnoc_qx"; + res->clks[idx++].id =3D "cnoc_sf_axi"; =20 num_opt_clks =3D idx - num_clks; res->num_clks =3D idx; @@ -1828,6 +1829,7 @@ static const struct of_device_id qcom_pcie_match[] = =3D { { .compatible =3D "qcom,pcie-sm8250", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sm8450-pcie0", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sm8450-pcie1", .data =3D &cfg_1_9_0 }, + { .compatible =3D "qcom,pcie-sm8550", .data =3D &cfg_1_9_0 }, { } }; =20 --=20 2.34.1