From nobody Sun Sep 14 18:27:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 704D5C004D4 for ; Thu, 19 Jan 2023 08:47:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229789AbjASIrw (ORCPT ); Thu, 19 Jan 2023 03:47:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230126AbjASIrh (ORCPT ); Thu, 19 Jan 2023 03:47:37 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7103861D77; Thu, 19 Jan 2023 00:47:33 -0800 (PST) Received: from benjamin-XPS-13-9310.. (unknown [IPv6:2a01:e0a:120:3210:2ad6:2833:dcf0:41ee]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by madras.collabora.co.uk (Postfix) with ESMTPSA id 783926600864; Thu, 19 Jan 2023 08:47:31 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674118051; bh=CAlP9QcCzlEbxHvVcSyXEx1s2/N6vplOVRdCA93dTew=; h=From:To:Cc:Subject:Date:From; b=WXKcs6gWzur4lPf8hAJvPjWmt79h0TzssBAPj2/0GLycgG/I8poyZofsrsMBznMFU cRX7Nj6PphBfVQ4PDNs9VsxhLRDXdPlbJYrB3+1ginwhCyw7fjx7sEr9OZVUr5GZtE 6oJIo/FHZIUWsT0unwWs4UyAFAJO4eFkZOzilhWJm0iwZZcXIkVWvZCd+k7Ih3zBcs Q6YW3cy4T+Y0CwoGh7NlbJLIuyymuh21grZYALQZQO08z1uiN+fJAsdc1vIpEx+tkW 69ubYa+9BgIrXD5awIyNp6OvH3o78md9B/sDCy3Z4pNJq8hlvoYdUPAzi9cLy7IksU 80FI/eGjO6lsA== From: Benjamin Gaignard To: ezequiel@vanguardiasur.com.ar, p.zabel@pengutronix.de, mchehab@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, hverkuil-cisco@xs4all.nl, nicolas.dufresne@collabora.co.uk Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, Benjamin Gaignard Subject: [PATCH v3] media: verisilicon: HEVC: Only propose 10 bits compatible pixels formats Date: Thu, 19 Jan 2023 09:47:23 +0100 Message-Id: <20230119084723.133576-1-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When decoding a 10bits bitstreams HEVC driver should only expose 10bits pixel formats. To fulfill this requirement it is needed to call hantro_reset_raw_fmt() when bit depth change and to correctly set match_depth in pixel formats enumeration. Fixes: dc39473d0340 ("media: hantro: imx8m: Enable 10bit decoding") Signed-off-by: Benjamin Gaignard Tested-by: Nicolas Dufresne --- version 3: - Propagate hantro_reset_raw_fmt() error. I hope I have correctly understood Ezekiel's thoughts=20 in the way I have implemented them. version 2: - Remove struct hantro_ctx *ctx variable in hantro_try_ctrl() because it isn't used anymore. .../media/platform/verisilicon/hantro_drv.c | 40 +++++++++++++++---- .../media/platform/verisilicon/hantro_v4l2.c | 6 +-- .../media/platform/verisilicon/hantro_v4l2.h | 1 + .../media/platform/verisilicon/imx8m_vpu_hw.c | 2 + 4 files changed, 38 insertions(+), 11 deletions(-) diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/medi= a/platform/verisilicon/hantro_drv.c index 8cb4a68c9119..a713a45c0108 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -251,11 +251,6 @@ queue_init(void *priv, struct vb2_queue *src_vq, struc= t vb2_queue *dst_vq) =20 static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) { - struct hantro_ctx *ctx; - - ctx =3D container_of(ctrl->handler, - struct hantro_ctx, ctrl_handler); - if (ctrl->id =3D=3D V4L2_CID_STATELESS_H264_SPS) { const struct v4l2_ctrl_h264_sps *sps =3D ctrl->p_new.p_h264_sps; =20 @@ -274,8 +269,6 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) if (sps->bit_depth_luma_minus8 !=3D 0 && sps->bit_depth_luma_minus8 !=3D= 2) /* Only 8-bit and 10-bit are supported */ return -EINVAL; - - ctx->bit_depth =3D sps->bit_depth_luma_minus8 + 8; } else if (ctrl->id =3D=3D V4L2_CID_STATELESS_VP9_FRAME) { const struct v4l2_ctrl_vp9_frame *dec_params =3D ctrl->p_new.p_vp9_frame; =20 @@ -286,6 +279,32 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) return 0; } =20 +static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct hantro_ctx *ctx; + + ctx =3D container_of(ctrl->handler, + struct hantro_ctx, ctrl_handler); + + vpu_debug(1, "s_ctrl: id =3D %d, val =3D %d\n", ctrl->id, ctrl->val); + + switch (ctrl->id) { + case V4L2_CID_STATELESS_HEVC_SPS: + const struct v4l2_ctrl_hevc_sps *sps =3D ctrl->p_new.p_hevc_sps; + int bit_depth =3D sps->bit_depth_luma_minus8 + 8; + + if (ctx->bit_depth !=3D bit_depth) { + ctx->bit_depth =3D bit_depth; + return hantro_reset_raw_fmt(ctx); + } + break; + default: + return -EINVAL; + } + + return 0; +} + static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl) { struct hantro_ctx *ctx; @@ -328,6 +347,11 @@ static const struct v4l2_ctrl_ops hantro_ctrl_ops =3D { .try_ctrl =3D hantro_try_ctrl, }; =20 +static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops =3D { + .s_ctrl =3D hantro_hevc_s_ctrl, + .try_ctrl =3D hantro_try_ctrl, +}; + static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops =3D { .s_ctrl =3D hantro_jpeg_s_ctrl, }; @@ -470,7 +494,7 @@ static const struct hantro_ctrl controls[] =3D { .codec =3D HANTRO_HEVC_DECODER, .cfg =3D { .id =3D V4L2_CID_STATELESS_HEVC_SPS, - .ops =3D &hantro_ctrl_ops, + .ops =3D &hantro_hevc_ctrl_ops, }, }, { .codec =3D HANTRO_HEVC_DECODER, diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.c b/drivers/med= ia/platform/verisilicon/hantro_v4l2.c index 2c7a805289e7..cd85877bbbe2 100644 --- a/drivers/media/platform/verisilicon/hantro_v4l2.c +++ b/drivers/media/platform/verisilicon/hantro_v4l2.c @@ -398,7 +398,7 @@ hantro_reset_encoded_fmt(struct hantro_ctx *ctx) hantro_set_fmt_out(ctx, fmt); } =20 -static void +int hantro_reset_raw_fmt(struct hantro_ctx *ctx) { const struct hantro_fmt *raw_vpu_fmt; @@ -420,9 +420,9 @@ hantro_reset_raw_fmt(struct hantro_ctx *ctx) raw_fmt->width =3D encoded_fmt->width; raw_fmt->height =3D encoded_fmt->height; if (ctx->is_encoder) - hantro_set_fmt_out(ctx, raw_fmt); + return hantro_set_fmt_out(ctx, raw_fmt); else - hantro_set_fmt_cap(ctx, raw_fmt); + return hantro_set_fmt_cap(ctx, raw_fmt); } =20 void hantro_reset_fmts(struct hantro_ctx *ctx) diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.h b/drivers/med= ia/platform/verisilicon/hantro_v4l2.h index 64f6f57e9d7a..cb8e1fe3422d 100644 --- a/drivers/media/platform/verisilicon/hantro_v4l2.h +++ b/drivers/media/platform/verisilicon/hantro_v4l2.h @@ -21,6 +21,7 @@ extern const struct v4l2_ioctl_ops hantro_ioctl_ops; extern const struct vb2_ops hantro_queue_ops; =20 +int hantro_reset_raw_fmt(struct hantro_ctx *ctx); void hantro_reset_fmts(struct hantro_ctx *ctx); int hantro_get_format_depth(u32 fourcc); const struct hantro_fmt * diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c b/drivers/me= dia/platform/verisilicon/imx8m_vpu_hw.c index b390228fd3b4..f850d8bddef6 100644 --- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c +++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c @@ -152,6 +152,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fm= ts[] =3D { { .fourcc =3D V4L2_PIX_FMT_NV12, .codec_mode =3D HANTRO_MODE_NONE, + .match_depth =3D true, .postprocessed =3D true, .frmsize =3D { .min_width =3D FMT_MIN_WIDTH, @@ -165,6 +166,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fm= ts[] =3D { { .fourcc =3D V4L2_PIX_FMT_P010, .codec_mode =3D HANTRO_MODE_NONE, + .match_depth =3D true, .postprocessed =3D true, .frmsize =3D { .min_width =3D FMT_MIN_WIDTH, --=20 2.34.1