From nobody Sun Sep 14 18:30:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C26D9C00A5A for ; Thu, 19 Jan 2023 04:31:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230323AbjASEa7 (ORCPT ); Wed, 18 Jan 2023 23:30:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229973AbjASE1k (ORCPT ); Wed, 18 Jan 2023 23:27:40 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91A966CCF2; Wed, 18 Jan 2023 20:26:50 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 30J4QONW015261; Wed, 18 Jan 2023 22:26:24 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1674102384; bh=ynrV2oGHwYXAQlAvAQmhMZx3OijLheuKW61DC7TDWcI=; h=From:To:CC:Subject:Date; b=q1FqUDX4MqOWbwOm7kuWit7GQATWV2LvJzfDaaDC7rGnvOBh/h+JMm9IQOoQVms9P /ucpdkSws+BOX2XHq29de5f/m61/LROG4gcZWvtMjhcYN8H39y3JluxFoin50MtmWv 0lpgmbyoaSlzgd7bX3+0UesztHAttH8qBa4cXJ24= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 30J4QOZb059417 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 18 Jan 2023 22:26:24 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 18 Jan 2023 22:26:23 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 18 Jan 2023 22:26:23 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30J4QM5B119592; Wed, 18 Jan 2023 22:26:23 -0600 From: Vaishnav Achath To: , , , , , , , CC: , , Subject: [PATCH] arm64: dts: ti: k3-j7200: Fix wakeup pinmux range Date: Thu, 19 Jan 2023 09:56:22 +0530 Message-ID: <20230119042622.22310-1-vaishnav.a@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The WKUP_PADCONFIG register region in J7200 has multiple non-addressable regions, split the existing wkup_pmx region as follows to avoid the non-addressable regions and include all valid WKUP_PADCONFIG registers. Also update references to old nodes with new ones. wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15) wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84) wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100) J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Signed-off-by: Vaishnav Achath Reviewed-by: Jayesh Choudhary --- .../dts/ti/k3-j7200-common-proc-board.dts | 2 +- .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 29 ++++++++++++++++++- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 6240856e4863..0d39d6b8cc0c 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -80,7 +80,7 @@ }; }; =20 -&wkup_pmx0 { +&wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins =3D < J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index fe669deba489..de56a0165bd0 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -56,7 +56,34 @@ wkup_pmx0: pinctrl@4301c000 { compatible =3D "pinctrl-single"; /* Proxy 0 addressing */ - reg =3D <0x00 0x4301c000 0x00 0x178>; + reg =3D <0x00 0x4301c000 0x00 0x34>; + #pinctrl-cells =3D <1>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0xffffffff>; + }; + + wkup_pmx1: pinctrl@0x4301c038 { + compatible =3D "pinctrl-single"; + /* Proxy 0 addressing */ + reg =3D <0x00 0x4301c038 0x00 0x8>; + #pinctrl-cells =3D <1>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0xffffffff>; + }; + + wkup_pmx2: pinctrl@0x4301c068 { + compatible =3D "pinctrl-single"; + /* Proxy 0 addressing */ + reg =3D <0x00 0x4301c068 0x00 0xec>; + #pinctrl-cells =3D <1>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0xffffffff>; + }; + + wkup_pmx3: pinctrl@0x4301c174 { + compatible =3D "pinctrl-single"; + /* Proxy 0 addressing */ + reg =3D <0x00 0x4301c174 0x00 0x20>; #pinctrl-cells =3D <1>; pinctrl-single,register-width =3D <32>; pinctrl-single,function-mask =3D <0xffffffff>; --=20 2.17.1