From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79C3FC38142 for ; Thu, 19 Jan 2023 03:52:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229961AbjASDts (ORCPT ); Wed, 18 Jan 2023 22:49:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229915AbjASDmQ (ORCPT ); Wed, 18 Jan 2023 22:42:16 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A12FD68416 for ; Wed, 18 Jan 2023 19:39:45 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id v23so1139261plo.1 for ; Wed, 18 Jan 2023 19:39:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=Gl+NRk1lPPWu1qLYsSSP0N9uQlgD1WldvUdBw1ctCec=; b=qoqKcYS8f6LMfCltLCw76kTijQXNvX8/VfSXOt8OQrO2E8WQaYIhFmesf6yohs5pCL CKe9/hsZiNYjWzFOxE8+B9URT7SJoH8qGUey1J4QXn0UcWxlbgMZNlEAFjewsp5T4lxS oKV5aeT3lsA7bO2sBGFyhsj14m/2UucKNjWqsRl+8fuy+YCWQ9zlFLvQZdrDjEoYqug4 Ol7di2eThl9GBfTVpWJJQUHB0bMtZv6nv244CE/TRC4TFC53wNdW9mkC/kWX6d4MsdWK 8uAfsPcBZUSepvXvgxsXuSf/zZIMFO/79KjunLxONC5XWH2tN8ihE875BDx9+hLxAtvh Cdfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Gl+NRk1lPPWu1qLYsSSP0N9uQlgD1WldvUdBw1ctCec=; b=8L6z5mVXHD6MktIXvkziJca3gWxlz2IkGl6R4tiIRuGFTWsx8QNVwHOYpk/0EMrbzl dFhxmTyUKIOHERT5vY5VdbtqIHUfi3uPTuCGKbYABD5gaC8QcI53Hayh96nPqZP9EzPz eqiVK2BuxpSvWdKMSKUOMGu4WrqBW1aFQaoVhGckWz68+DMScagQee1UMBmGt0FXghyX pH4SBFXqgDQw9retmrhwQvvOjTp7loYnIREGBPmPGkzQUwDR5JRc4wrpLAFmQQxXM0T8 Bvrx5N1b8Q/fC3Y+YgXTGr40xY3XznCCMIlvttyMKNP5fHKXmsnryqMD8QIOSZ8UD0Ja BBEg== X-Gm-Message-State: AFqh2kqjSO2O4kkACKesjgGjJ+ps/PWNeKuliG4dkDMFIU2ZXs6HWNvN MqjEnhXnw/ByEuSlaqNNBG9K7g== X-Google-Smtp-Source: AMrXdXvbKqKaMAq7GGHotAAAqe4B4wwrXEa//ZM+fYtZneMxVJOeS6SJD7B7/df7q0hm0iWG4UMHMQ== X-Received: by 2002:a05:6a20:8f0f:b0:ac:9d6b:c1f0 with SMTP id b15-20020a056a208f0f00b000ac9d6bc1f0mr13369763pzk.40.1674099585005; Wed, 18 Jan 2023 19:39:45 -0800 (PST) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id f13-20020aa7968d000000b0056b4c5dde61sm11097879pfk.98.2023.01.18.19.39.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 19:39:44 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 01/15] dt-bindings: arm: add AMD Pensando boards Date: Wed, 18 Jan 2023 19:39:04 -0800 Message-Id: <20230119033918.44117-2-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Document the compatible for AMD Pensando Elba SoC boards. Reviewed-by: Rob Herring Signed-off-by: Brad Larson --- .../devicetree/bindings/arm/amd,pensando.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amd,pensando.yaml diff --git a/Documentation/devicetree/bindings/arm/amd,pensando.yaml b/Docu= mentation/devicetree/bindings/arm/amd,pensando.yaml new file mode 100644 index 000000000000..e5c2591834a8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amd,pensando.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/amd,pensando.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando SoC Platforms + +maintainers: + - Brad Larson + +properties: + $nodename: + const: "/" + compatible: + oneOf: + + - description: Boards with Pensando Elba SoC + items: + - enum: + - amd,pensando-elba-ortano + - const: amd,pensando-elba + +additionalProperties: true + +... --=20 2.17.1 From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59546C38142 for ; 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Wed, 18 Jan 2023 19:39:54 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 02/15] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC Date: Wed, 18 Jan 2023 19:39:05 -0800 Message-Id: <20230119033918.44117-3-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" AMD Pensando Elba ARM 64-bit SoC is integrated with this IP and explicitly controls byte-lane enables. Signed-off-by: Brad Larson --- Changes since v6: - Add reset-names and resets properties - Add if/then on property amd,pensando-elba-sd4hc to set reg property values for minItems and maxItems --- .../devicetree/bindings/mmc/cdns,sdhci.yaml | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Docume= ntation/devicetree/bindings/mmc/cdns,sdhci.yaml index 8b1a0fdcb5e3..f7dd6f990f96 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -16,12 +16,14 @@ properties: compatible: items: - enum: + - amd,pensando-elba-sd4hc - microchip,mpfs-sd4hc - socionext,uniphier-sd4hc - const: cdns,sd4hc =20 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 interrupts: maxItems: 1 @@ -111,12 +113,36 @@ properties: minimum: 0 maximum: 0x7f =20 + reset-names: + items: + - const: hw + + resets: + description: + optional. phandle to the system reset controller with line index + for mmc hw reset line if exists. + maxItems: 1 + required: - compatible - reg - interrupts - clocks =20 +if: + properties: + compatible: + const: amd,pensando-elba-sd4hc +then: + properties: + reg: + minItems: 2 +else: + properties: + reg: + minItems: 1 + maxItems: 2 + unevaluatedProperties: false =20 examples: --=20 2.17.1 From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29DEBC38142 for ; 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Wed, 18 Jan 2023 19:40:02 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 03/15] dt-bindings: spi: cdns: Add compatible for AMD Pensando Elba SoC Date: Wed, 18 Jan 2023 19:39:06 -0800 Message-Id: <20230119033918.44117-4-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Document the cadence qspi controller compatible for AMD Pensando Elba SoC boards. The Elba qspi fifo size is 1024. Signed-off-by: Brad Larson --- Changes since v6: - Add 1024 to cdns,fifo-depth property to resolve dtbs_check error --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Doc= umentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 4707294d8f59..a6556854234f 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -20,11 +20,23 @@ allOf: required: - power-domains =20 + - if: + properties: + compatible: + enum: + - amd,pensando-elba-qspi + then: + properties: + cdns,fifo-depth: + enum: [ 128, 256, 1024 ] + default: 1024 + properties: compatible: oneOf: - items: - enum: + - amd,pensando-elba-qspi - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi @@ -48,7 +60,7 @@ properties: description: Size of the data FIFO in words. $ref: "/schemas/types.yaml#/definitions/uint32" - enum: [ 128, 256 ] + enum: [ 128, 256, 1024 ] default: 128 =20 cdns,fifo-width: --=20 2.17.1 From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE6A3C00A5A for ; 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Wed, 18 Jan 2023 19:40:07 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 04/15] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller bindings Date: Wed, 18 Jan 2023 19:39:07 -0800 Message-Id: <20230119033918.44117-5-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The AMD Pensando Elba SoC has integrated the DW APB SPI Controller Signed-off-by: Brad Larson --- Changes since v6: - Define property amd,pensando-elba-syscon - Move compatible amd,pensando-elba-spi ahead of baikal,bt1-ssi --- .../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/D= ocumentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index d33b72fabc5d..96b072835de0 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -37,6 +37,18 @@ allOf: else: required: - interrupts + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-spi + then: + properties: + amd,pensando-elba-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: AMD Pensando Elba SoC system controller + required: + - amd,pensando-elba-syscon =20 properties: compatible: @@ -63,6 +75,8 @@ properties: const: intel,keembay-ssi - description: Intel Thunder Bay SPI Controller const: intel,thunderbay-ssi + - description: AMD Pensando Elba SoC SPI Controller + const: amd,pensando-elba-spi - description: Baikal-T1 SPI Controller const: baikal,bt1-ssi - description: Baikal-T1 System Boot SPI Controller --=20 2.17.1 From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18901C38142 for ; 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Wed, 18 Jan 2023 19:40:14 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 05/15] dt-bindings: mfd: syscon: Add amd,pensando-elba-syscon compatible Date: Wed, 18 Jan 2023 19:39:08 -0800 Message-Id: <20230119033918.44117-6-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the AMD Pensando Elba SoC system registers compatible Acked-by: Rob Herring Signed-off-by: Brad Larson --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 1b01bd010431..f4b0ed4ff03c 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -38,6 +38,7 @@ properties: - allwinner,sun8i-h3-system-controller - allwinner,sun8i-v3s-system-controller - allwinner,sun50i-a64-system-controller + - amd,pensando-elba-syscon - brcm,cru-clkset - freecom,fsg-cs2-system-controller - fsl,imx93-aonmix-ns-syscfg --=20 2.17.1 From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99014C00A5A for ; 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Wed, 18 Jan 2023 19:40:25 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 06/15] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando System Resource chip Date: Wed, 18 Jan 2023 19:39:09 -0800 Message-Id: <20230119033918.44117-7-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the AMD Pensando SoC System Resource chip using the SPI interface. The device functions are accessed using four chip-selects. This device is present for all Pensando SoC designs. Signed-off-by: Brad Larson --- Changes since v6: - Instead of four nodes, one per chip-select, a single node is used with reset-cells in the parent. - No MFD API is used anymore in the driver so it made sense to move this to drivers/spi. - This driver is common for all Pensando SoC based designs so changed the name to pensando-sr.c to not make it Elba SoC specific. - Added property cs for the chip-select number which is used by the driver to create /dev/pensr0.=20 --- .../bindings/spi/amd,pensando-sr.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/amd,pensando-sr.y= aml diff --git a/Documentation/devicetree/bindings/spi/amd,pensando-sr.yaml b/D= ocumentation/devicetree/bindings/spi/amd,pensando-sr.yaml new file mode 100644 index 000000000000..8504652f6e19 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/amd,pensando-sr.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/amd,pensando-sr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando SoC Resource Controller + +description: | + AMD Pensando SoC Resource Controller is a set of + control/status registers accessed on four chip-selects. + This device is present in all Pensando SoC based designs. + +maintainers: + - Brad Larson + +properties: + compatible: + contains: + enum: + - amd,pensando-sr + + reg: + minItems: 1 + + cs: + minItems: 1 + maxItems: 4 + description: + Device chip select + + '#reset-cells': + const: 1 + + interrupts: + maxItems: 1 + + spi-max-frequency: true + +required: + - compatible + - cs + - spi-max-frequency + - '#reset-cells' + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + num-cs =3D <4>; + + system-controller@0 { + compatible =3D "amd,pensando-sr"; + reg =3D <0>; + cs =3D <0 1 2 3>; + spi-max-frequency =3D <12000000>; + interrupt-parent =3D <&porta>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells =3D <1>; + }; + }; + +... --=20 2.17.1 From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A86BDC38142 for ; Thu, 19 Jan 2023 04:30:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229944AbjASEaB (ORCPT ); Wed, 18 Jan 2023 23:30:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229942AbjASDm3 (ORCPT ); Wed, 18 Jan 2023 22:42:29 -0500 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BF446D376 for ; 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Wed, 18 Jan 2023 19:40:36 -0800 (PST) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id f13-20020aa7968d000000b0056b4c5dde61sm11097879pfk.98.2023.01.18.19.40.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 19:40:36 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 07/15] MAINTAINERS: Add entry for AMD PENSANDO Date: Wed, 18 Jan 2023 19:39:10 -0800 Message-Id: <20230119033918.44117-8-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add entry for AMD PENSANDO maintainer and files Signed-off-by: Brad Larson --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f61eb221415b..74eb977badb4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1890,6 +1890,14 @@ N: allwinner N: sun[x456789]i N: sun50i =20 +ARM/AMD PENSANDO ARM64 ARCHITECTURE +M: Brad Larson +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/*/amd,pensando* +F: arch/arm64/boot/dts/amd/elba* +F: drivers/spi/spi-pensando-sr.c + ARM/Amlogic Meson SoC CLOCK FRAMEWORK M: Neil Armstrong M: Jerome Brunet --=20 2.17.1 From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1CE5C38142 for ; Thu, 19 Jan 2023 04:30:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229986AbjASEaS (ORCPT ); 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Wed, 18 Jan 2023 19:40:42 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 08/15] arm64: Add config for AMD Pensando SoC platforms Date: Wed, 18 Jan 2023 19:39:11 -0800 Message-Id: <20230119033918.44117-9-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add ARCH_PENSANDO configuration option for AMD Pensando SoC based platforms. Signed-off-by: Brad Larson --- arch/arm64/Kconfig.platforms | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index d1970adf80ab..11d4f73cd341 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -236,6 +236,18 @@ config ARCH_NPCM General support for NPCM8xx BMC (Arbel). Nuvoton NPCM8xx BMC based on the Cortex A35. =20 +config ARCH_PENSANDO + bool "AMD Pensando Platforms" + help + This enables support for the ARMv8 based AMD Pensando SoC + family to include the Elba SoC. + + AMD Pensando SoCs support a range of Distributed Services + Cards in PCIe format installed into servers. The Elba + SoC includes 16 A-72 CPU cores, 144 programmable P4 + cores for a minimal latency/jitter datapath, and network + interfaces up to 200 Gb/s. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB --=20 2.17.1 From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE559C678D6 for ; Thu, 19 Jan 2023 03:52:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230218AbjASDvv (ORCPT ); Wed, 18 Jan 2023 22:51:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229787AbjASDlS (ORCPT ); Wed, 18 Jan 2023 22:41:18 -0500 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 492AD6D6B1 for ; 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Wed, 18 Jan 2023 19:40:47 -0800 (PST) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id f13-20020aa7968d000000b0056b4c5dde61sm11097879pfk.98.2023.01.18.19.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 19:40:47 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 09/15] arm64: dts: Add AMD Pensando Elba SoC support Date: Wed, 18 Jan 2023 19:39:12 -0800 Message-Id: <20230119033918.44117-10-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add AMD Pensando common and Elba SoC specific device nodes Signed-off-by: Brad Larson --- Changes since v6: - Single node for spi0 system-controller and squash the reset-controller child into parent --- arch/arm64/boot/dts/amd/Makefile | 1 + arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++++++++++ arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 82 ++++++++ arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++ arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++ arch/arm64/boot/dts/amd/elba.dtsi | 192 ++++++++++++++++++ 6 files changed, 598 insertions(+) create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Mak= efile index 68103a8b0ef5..8502cc2afbc5 100644 --- a/arch/arm64/boot/dts/amd/Makefile +++ b/arch/arm64/boot/dts/amd/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_PENSANDO) +=3D elba-asic.dtb dtb-$(CONFIG_ARCH_SEATTLE) +=3D amd-overdrive-rev-b0.dtb amd-overdrive-rev= -b1.dtb diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts= /amd/elba-16core.dtsi new file mode 100644 index 000000000000..37aadd442db8 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/ { + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { cpu =3D <&cpu0>; }; + core1 { cpu =3D <&cpu1>; }; + core2 { cpu =3D <&cpu2>; }; + core3 { cpu =3D <&cpu3>; }; + }; + + cluster1 { + core0 { cpu =3D <&cpu4>; }; + core1 { cpu =3D <&cpu5>; }; + core2 { cpu =3D <&cpu6>; }; + core3 { cpu =3D <&cpu7>; }; + }; + + cluster2 { + core0 { cpu =3D <&cpu8>; }; + core1 { cpu =3D <&cpu9>; }; + core2 { cpu =3D <&cpu10>; }; + core3 { cpu =3D <&cpu11>; }; + }; + + cluster3 { + core0 { cpu =3D <&cpu12>; }; + core1 { cpu =3D <&cpu13>; }; + core2 { cpu =3D <&cpu14>; }; + core3 { cpu =3D <&cpu15>; }; + }; + }; + + /* CLUSTER 0 */ + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x0>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x1>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x2>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x3>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + }; + + /* CLUSTER 1 */ + cpu4: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x100>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + }; + + cpu5: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x101>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + }; + + cpu6: cpu@102 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x102>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + }; + + cpu7: cpu@103 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x103>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + }; + + /* CLUSTER 2 */ + cpu8: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x200>; + next-level-cache =3D <&l2_2>; + enable-method =3D "psci"; + }; + + cpu9: cpu@201 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x201>; + next-level-cache =3D <&l2_2>; + enable-method =3D "psci"; + }; + + cpu10: cpu@202 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x202>; + next-level-cache =3D <&l2_2>; + enable-method =3D "psci"; + }; + + cpu11: cpu@203 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x203>; + next-level-cache =3D <&l2_2>; + enable-method =3D "psci"; + }; + + l2_2: l2-cache2 { + compatible =3D "cache"; + }; + + /* CLUSTER 3 */ + cpu12: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x300>; + next-level-cache =3D <&l2_3>; + enable-method =3D "psci"; + }; + + cpu13: cpu@301 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x301>; + next-level-cache =3D <&l2_3>; + enable-method =3D "psci"; + }; + + cpu14: cpu@302 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x302>; + next-level-cache =3D <&l2_3>; + enable-method =3D "psci"; + }; + + cpu15: cpu@303 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x303>; + next-level-cache =3D <&l2_3>; + enable-method =3D "psci"; + }; + + l2_3: l2-cache3 { + compatible =3D "cache"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boo= t/dts/amd/elba-asic-common.dtsi new file mode 100644 index 000000000000..1abcb1264108 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&ahb_clk { + clock-frequency =3D <400000000>; +}; + +&emmc_clk { + clock-frequency =3D <200000000>; +}; + +&flash_clk { + clock-frequency =3D <400000000>; +}; + +&ref_clk { + clock-frequency =3D <156250000>; +}; + +&qspi { + status =3D "okay"; + + flash0: flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <40000000>; + spi-rx-bus-width =3D <2>; + m25p,fast-read; + cdns,read-delay =3D <0>; + cdns,tshsl-ns =3D <0>; + cdns,tsd2d-ns =3D <0>; + cdns,tchsh-ns =3D <0>; + cdns,tslch-ns =3D <0>; + }; +}; + +&gpio0 { + status =3D "okay"; +}; + +&emmc { + bus-width =3D <8>; + cap-mmc-hw-reset; + reset-names =3D "hw"; + resets =3D <&rstc 0>; + status =3D "okay"; +}; + +&wdt0 { + status =3D "okay"; +}; + +&i2c0 { + clock-frequency =3D <100000>; + status =3D "okay"; + + rtc@51 { + compatible =3D "nxp,pcf85263"; + reg =3D <0x51>; + }; +}; + +&spi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + num-cs =3D <4>; + cs-gpios =3D <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, + <&porta 7 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + rstc: system-controller@0 { + compatible =3D "amd,pensando-sr"; + reg =3D <0>; + cs =3D <0 1 2 3>; + spi-max-frequency =3D <12000000>; + interrupt-parent =3D <&porta>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells =3D <1>; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/am= d/elba-asic.dts new file mode 100644 index 000000000000..c3f4da2f7449 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Device Tree file for AMD Pensando Elba Board. + * + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +#include "elba.dtsi" +#include "elba-16core.dtsi" +#include "elba-asic-common.dtsi" +#include "elba-flash-parts.dtsi" + +/ { + model =3D "AMD Pensando Elba Board"; + compatible =3D "amd,pensando-elba-ortano", "amd,pensando-elba"; + + aliases { + serial0 =3D &uart0; + spi0 =3D &spi0; + spi1 =3D &qspi; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boo= t/dts/amd/elba-flash-parts.dtsi new file mode 100644 index 000000000000..734893fef2c3 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&flash0 { + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + partition@0 { + label =3D "flash"; + reg =3D <0x10000 0xfff0000>; + }; + + partition@f0000 { + label =3D "golduenv"; + reg =3D <0xf0000 0x10000>; + }; + + partition@100000 { + label =3D "boot0"; + reg =3D <0x100000 0x80000>; + }; + + partition@180000 { + label =3D "golduboot"; + reg =3D <0x180000 0x200000>; + }; + + partition@380000 { + label =3D "brdcfg0"; + reg =3D <0x380000 0x10000>; + }; + + partition@390000 { + label =3D "brdcfg1"; + reg =3D <0x390000 0x10000>; + }; + + partition@400000 { + label =3D "goldfw"; + reg =3D <0x400000 0x3c00000>; + }; + + partition@4010000 { + label =3D "fwmap"; + reg =3D <0x4010000 0x20000>; + }; + + partition@4030000 { + label =3D "fwsel"; + reg =3D <0x4030000 0x20000>; + }; + + partition@4090000 { + label =3D "bootlog"; + reg =3D <0x4090000 0x20000>; + }; + + partition@40b0000 { + label =3D "panicbuf"; + reg =3D <0x40b0000 0x20000>; + }; + + partition@40d0000 { + label =3D "uservars"; + reg =3D <0x40d0000 0x20000>; + }; + + partition@4200000 { + label =3D "uboota"; + reg =3D <0x4200000 0x400000>; + }; + + partition@4600000 { + label =3D "ubootb"; + reg =3D <0x4600000 0x400000>; + }; + + partition@4a00000 { + label =3D "mainfwa"; + reg =3D <0x4a00000 0x1000000>; + }; + + partition@5a00000 { + label =3D "mainfwb"; + reg =3D <0x5a00000 0x1000000>; + }; + + partition@6a00000 { + label =3D "diaguboot"; + reg =3D <0x6a00000 0x400000>; + }; + + partition@8000000 { + label =3D "diagfw"; + reg =3D <0x8000000 0x7fe0000>; + }; + + partition@ffe0000 { + label =3D "ubootenv"; + reg =3D <0xffe0000 0x10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/el= ba.dtsi new file mode 100644 index 000000000000..285d776aa67b --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +#include +#include "dt-bindings/interrupt-controller/arm-gic.h" + +/ { + model =3D "Elba ASIC Board"; + compatible =3D "amd,pensando-elba"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + dma-coherent; + + ahb_clk: oscillator0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + emmc_clk: oscillator2 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + flash_clk: oscillator3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + ref_clk: oscillator4 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + pmu { + compatible =3D "arm,cortex-a72-pmu"; + interrupts =3D ; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + i2c0: i2c@400 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x400 0x0 0x100>; + clocks =3D <&ahb_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-sda-hold-time-ns =3D <480>; + snps,sda-timeout-ms =3D <750>; + interrupts =3D ; + status =3D "disabled"; + }; + + wdt0: watchdog@1400 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x0 0x1400 0x0 0x100>; + clocks =3D <&ahb_clk>; + interrupts =3D ; + status =3D "disabled"; + }; + + qspi: spi@2400 { + compatible =3D "amd,pensando-elba-qspi", "cdns,qspi-nor"; + reg =3D <0x0 0x2400 0x0 0x400>, + <0x0 0x7fff0000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&flash_clk>; + cdns,fifo-depth =3D <1024>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x7fff0000>; + status =3D "disabled"; + }; + + spi0: spi@2800 { + compatible =3D "amd,pensando-elba-spi"; + reg =3D <0x0 0x2800 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + amd,pensando-elba-syscon =3D <&syscon>; + clocks =3D <&ahb_clk>; + interrupts =3D ; + num-cs =3D <2>; + status =3D "disabled"; + }; + + gpio0: gpio@4000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x0 0x4000 0x0 0x78>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + porta: gpio-port@0 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <0>; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <8>; + interrupts =3D ; + interrupt-controller; + interrupt-parent =3D <&gic>; + #interrupt-cells =3D <2>; + }; + + portb: gpio-port@1 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <1>; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <8>; + }; + }; + + uart0: serial@4800 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x4800 0x0 0x100>; + clocks =3D <&ref_clk>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + }; + + gic: interrupt-controller@800000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x800000 0x0 0x200000>, /* GICD */ + <0x0 0xa00000 0x0 0x200000>, /* GICR */ + <0x0 0x60000000 0x0 0x2000>, /* GICC */ + <0x0 0x60010000 0x0 0x1000>, /* GICH */ + <0x0 0x60020000 0x0 0x2000>; /* GICV */ + #address-cells =3D <2>; + #size-cells =3D <2>; + #interrupt-cells =3D <3>; + ranges; + interrupt-controller; + interrupts =3D ; + + /* + * Elba specific pre-ITS is enabled using the + * existing property socionext,synquacer-pre-its + */ + gic_its: msi-controller@820000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x820000 0x0 0x10000>; + msi-controller; + #msi-cells =3D <1>; + socionext,synquacer-pre-its =3D + <0xc00000 0x1000000>; + }; + }; + + emmc: mmc@30440000 { + compatible =3D "amd,pensando-elba-sd4hc", "cdns,sd4hc"; + reg =3D <0x0 0x30440000 0x0 0x10000>, + <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */ + clocks =3D <&emmc_clk>; + interrupts =3D ; + cdns,phy-input-delay-sd-highspeed =3D <0x4>; + cdns,phy-input-delay-legacy =3D <0x4>; + cdns,phy-input-delay-sd-uhs-sdr50 =3D <0x6>; + cdns,phy-input-delay-sd-uhs-ddr50 =3D <0x16>; + mmc-ddr-1_8v; + status =3D "disabled"; + }; + + syscon: syscon@307c0000 { + compatible =3D "amd,pensando-elba-syscon", "syscon"; + reg =3D <0x0 0x307c0000 0x0 0x3000>; + }; + }; +}; --=20 2.17.1 From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1823BC678D4 for ; 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Wed, 18 Jan 2023 19:40:54 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 10/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Wed, 18 Jan 2023 19:39:13 -0800 Message-Id: <20230119033918.44117-11-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson --- Changes since v6: - Rebase to linux-next 6.2.0-rc1 --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 676313e1bdad..e042781d3db5 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,6 +40,7 @@ #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) =20 /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -89,6 +90,7 @@ struct cqspi_st { u32 pd_dev_id; bool wr_completion; bool slow_sram; + bool apb_ahb_hazard; }; =20 struct cqspi_driver_platdata { @@ -978,6 +980,13 @@ static int cqspi_indirect_write_execute(struct cqspi_f= lash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); =20 + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; =20 @@ -1700,6 +1709,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->wr_completion =3D false; if (ddata->quirks & CQSPI_SLOW_SRAM) cqspi->slow_sram =3D true; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard =3D true; =20 if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1825,6 +1836,10 @@ static const struct cqspi_driver_platdata versal_osp= i =3D { .get_dma_status =3D cqspi_get_versal_dma_status, }; =20 +static const struct cqspi_driver_platdata pensando_cdns_qspi =3D { + .quirks =3D CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] =3D { { .compatible =3D "cdns,qspi-nor", @@ -1850,6 +1865,10 @@ static const struct of_device_id cqspi_dt_ids[] =3D { .compatible =3D "intel,socfpga-qspi", .data =3D &socfpga_qspi, }, + { + .compatible =3D "amd,pensando-elba-qspi", + .data =3D &pensando_cdns_qspi, + }, { /* end of table */ } }; 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Wed, 18 Jan 2023 19:41:02 -0800 (PST) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id f13-20020aa7968d000000b0056b4c5dde61sm11097879pfk.98.2023.01.18.19.41.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 19:41:02 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 11/15] spi: dw: Add support for AMD Pensando Elba SoC Date: Wed, 18 Jan 2023 19:39:14 -0800 Message-Id: <20230119033918.44117-12-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The AMD Pensando Elba SoC includes a DW apb_ssi v4 controller with device specific chip-select control. The Elba SoC provides four chip-selects where the native DW IP supports two chip-selects. The Elba DW_SPI instance has two native CS signals that are always overridden. Signed-off-by: Brad Larson --- Changes since v6: - Add use of macros GENMASK() and BIT() - Change ELBA_SPICS_SHIFT() to ELBA_SPICS_OFFSET() --- drivers/spi/spi-dw-mmio.c | 78 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 26c40ea6dd12..9b6f876227e8 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -53,6 +53,24 @@ struct dw_spi_mscc { void __iomem *spi_mst; /* Not sparx5 */ }; =20 +struct dw_spi_elba { + struct regmap *syscon; +}; + +/* + * Elba SoC does not use ssi, pin override is used for cs 0,1 and + * gpios for cs 2,3 as defined in the device tree. + * + * cs: | 1 0 + * bit: |---3-------2-------1-------0 + * | cs1 cs1_ovr cs0 cs0_ovr + */ +#define ELBA_SPICS_REG 0x2468 +#define ELBA_SPICS_OFFSET(cs) ((cs) << 1) +#define ELBA_SPICS_MASK(cs) (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs)) +#define ELBA_SPICS_SET(cs, val) \ + ((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs)) + /* * The Designware SPI controller (referred to as master in the documentati= on) * automatically deasserts chip select when the tx fifo is empty. The chip @@ -237,6 +255,65 @@ static int dw_spi_canaan_k210_init(struct platform_dev= ice *pdev, return 0; } =20 +static void dw_spi_elba_override_cs(struct dw_spi_elba *dwselba, int cs, i= nt enable) +{ + regmap_update_bits(dwselba->syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs), + ELBA_SPICS_SET(cs, enable)); + +} + +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable) +{ + struct dw_spi *dws =3D spi_master_get_devdata(spi->master); + struct dw_spi_mmio *dwsmmio =3D container_of(dws, struct dw_spi_mmio, dws= ); + struct dw_spi_elba *dwselba =3D dwsmmio->priv; + u8 cs; + + cs =3D spi->chip_select; + if (cs < 2) + dw_spi_elba_override_cs(dwselba, spi->chip_select, enable); + + /* + * The DW SPI controller needs a native CS bit selected to start + * the serial engine. + */ + spi->chip_select =3D 0; + dw_spi_set_cs(spi, enable); + spi->chip_select =3D cs; +} + +static int dw_spi_elba_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + const char *syscon_name =3D "amd,pensando-elba-syscon"; + struct device_node *np =3D pdev->dev.of_node; + struct dw_spi_elba *dwselba; + struct device_node *node; + struct regmap *regmap; + + node =3D of_parse_phandle(np, syscon_name, 0); + if (!node) { + dev_err(&pdev->dev, "failed to find %s\n", syscon_name); + return -ENODEV; + } + + regmap =3D syscon_node_to_regmap(node); + if (IS_ERR(regmap)) { + dev_err(&pdev->dev, "syscon regmap lookup failed\n"); + return PTR_ERR(regmap); + } + + dwselba =3D devm_kzalloc(&pdev->dev, sizeof(*dwselba), GFP_KERNEL); + if (!dwselba) + return -ENOMEM; + + dwselba->syscon =3D regmap; + dwsmmio->priv =3D dwselba; + dwsmmio->dws.set_cs =3D dw_spi_elba_set_cs; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -352,6 +429,7 @@ static const struct of_device_id dw_spi_mmio_of_match[]= =3D { { .compatible =3D "intel,thunderbay-ssi", .data =3D dw_spi_intel_init}, { .compatible =3D "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible =3D "canaan,k210-spi", dw_spi_canaan_k210_init}, + { .compatible =3D "amd,pensando-elba-spi", .data =3D dw_spi_elba_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); --=20 2.17.1 From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72DD2C678D6 for ; Thu, 19 Jan 2023 04:02:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230119AbjASEAC (ORCPT ); Wed, 18 Jan 2023 23:00:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229969AbjASDmk (ORCPT ); Wed, 18 Jan 2023 22:42:40 -0500 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 116F96D698 for ; Wed, 18 Jan 2023 19:41:14 -0800 (PST) Received: by mail-pf1-x436.google.com with SMTP id w2so500450pfc.11 for ; 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Wed, 18 Jan 2023 19:41:08 -0800 (PST) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id f13-20020aa7968d000000b0056b4c5dde61sm11097879pfk.98.2023.01.18.19.41.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 19:41:08 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 12/15] mmc: sdhci-cadence: Enable device specific override of writel() Date: Wed, 18 Jan 2023 19:39:15 -0800 Message-Id: <20230119033918.44117-13-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SoCs with device specific Cadence implementation, such as setting byte-enables before the write, need to override writel(). Add a callback where the default is writel() for all existing chips. Signed-off-by: Brad Larson --- Changes since v6: - No change to this patch but as some patches are deleted and this is a respin the three successive patches to sdhci-cadence.c are patches 12, 13, and 14 which do the following: 1. Add ability for Cadence specific design to have priv writel(). 2. Add Elba SoC support that requires its own priv writel() for byte-lane control . 3. Add support for mmc hardware reset. --- drivers/mmc/host/sdhci-cadence.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cade= nce.c index 6f2de54a5987..708d4297f241 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -67,6 +67,7 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; bool enhanced_strobe; + void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *= reg); unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -90,6 +91,12 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cf= gs[] =3D { { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, }; =20 +static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + writel(val, reg); +} + static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, u8 addr, u8 data) { @@ -104,17 +111,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns= _priv *priv, =20 tmp =3D FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); =20 tmp |=3D SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); =20 ret =3D readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10); if (ret) return ret; =20 tmp &=3D ~SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); =20 ret =3D readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK), 0, 10); @@ -191,7 +198,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_= priv *priv, u32 mode) tmp =3D readl(priv->hrs_addr + SDHCI_CDNS_HRS06); tmp &=3D ~SDHCI_CDNS_HRS06_MODE; tmp |=3D FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); - writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); + priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); } =20 static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) @@ -223,7 +230,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *h= ost, unsigned int val) */ for (i =3D 0; i < 2; i++) { tmp |=3D SDHCI_CDNS_HRS06_TUNE_UP; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); =20 ret =3D readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), @@ -386,6 +393,7 @@ static int sdhci_cdns_probe(struct platform_device *pde= v) priv->nr_phy_params =3D nr_phy_params; priv->hrs_addr =3D host->ioaddr; priv->enhanced_strobe =3D false; + priv->priv_writel =3D cdns_writel; host->ioaddr +=3D SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe =3D sdhci_cdns_hs400_enhanced_strobe; --=20 2.17.1 From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 351DFC00A5A for ; Thu, 19 Jan 2023 03:58:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229710AbjASD5p (ORCPT ); Wed, 18 Jan 2023 22:57:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229888AbjASDoY (ORCPT ); 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Wed, 18 Jan 2023 19:41:13 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Date: Wed, 18 Jan 2023 19:39:16 -0800 Message-Id: <20230119033918.44117-14-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for AMD Pensando Elba SoC which explicitly controls byte-lane enables on writes. Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which allows Elba SoC sdhci_elba_ops to overwrite the SDHCI IO memory accessors. Signed-off-by: Brad Larson --- Changes since v6: - Previously patch 16/17 --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-cadence.c | 131 ++++++++++++++++++++++++++++--- 2 files changed, 123 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 5e19a961c34d..9e41115cc753 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -255,6 +255,7 @@ config MMC_SDHCI_CADENCE tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" depends on MMC_SDHCI_PLTFM depends on OF + select MMC_SDHCI_IO_ACCESSORS help This selects the Cadence SD/SDIO/eMMC driver. =20 diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cade= nce.c index 708d4297f241..e92aa79a8be2 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -66,6 +66,8 @@ struct sdhci_cdns_phy_param { =20 struct sdhci_cdns_priv { void __iomem *hrs_addr; + void __iomem *ctl_addr; /* write control */ + spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *= reg); unsigned int nr_phy_params; @@ -77,6 +79,11 @@ struct sdhci_cdns_phy_cfg { u8 addr; }; =20 +struct sdhci_cdns_drv_data { + int (*init)(struct platform_device *pdev); + const struct sdhci_pltfm_data pltfm_data; +}; + static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] =3D { { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, }, { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, }, @@ -316,6 +323,92 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_= host *host, sdhci_set_uhs_signaling(host, timing); } =20 +/* Elba control register bits [6:3] are byte-lane enables */ +#define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3) + +/* + * The Pensando Elba SoC explicitly controls byte-lane enabling on writes + * which includes writes to the HRS registers. + */ +static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + unsigned long flags; + + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + writel(val, reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_l(struct sdhci_host *host, u32 val, int reg) +{ + elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg); +} + +static void elba_write_w(struct sdhci_host *host, u16 val, int reg) +{ + struct sdhci_cdns_priv *priv =3D sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables =3D GENMASK(1, 0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writew(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_b(struct sdhci_host *host, u8 val, int reg) +{ + struct sdhci_cdns_priv *priv =3D sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables =3D BIT(0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writeb(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static const struct sdhci_ops sdhci_elba_ops =3D { + .write_l =3D elba_write_l, + .write_w =3D elba_write_w, + .write_b =3D elba_write_b, + .set_clock =3D sdhci_set_clock, + .get_timeout_clock =3D sdhci_cdns_get_timeout_clock, + .set_bus_width =3D sdhci_set_bus_width, + .reset =3D sdhci_reset, + .set_uhs_signaling =3D sdhci_cdns_set_uhs_signaling, +}; + +static int elba_drv_init(struct platform_device *pdev) +{ + struct sdhci_host *host =3D platform_get_drvdata(pdev); + struct sdhci_cdns_priv *priv =3D sdhci_cdns_priv(host); + struct resource *iomem; + void __iomem *ioaddr; + + host->mmc->caps |=3D (MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA); + + iomem =3D platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!iomem) + return -ENOMEM; + + /* Byte-lane control register */ + ioaddr =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(ioaddr)) + return PTR_ERR(ioaddr); + + priv->ctl_addr =3D ioaddr; + priv->priv_writel =3D elba_priv_writel; + spin_lock_init(&priv->wrlock); + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + + return 0; +} + static const struct sdhci_ops sdhci_cdns_ops =3D { .set_clock =3D sdhci_set_clock, .get_timeout_clock =3D sdhci_cdns_get_timeout_clock, @@ -325,13 +418,24 @@ static const struct sdhci_ops sdhci_cdns_ops =3D { .set_uhs_signaling =3D sdhci_cdns_set_uhs_signaling, }; =20 -static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data =3D { - .ops =3D &sdhci_cdns_ops, - .quirks2 =3D SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data =3D { + .pltfm_data =3D { + .ops =3D &sdhci_cdns_ops, + .quirks2 =3D SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, }; =20 -static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data =3D { - .ops =3D &sdhci_cdns_ops, +static const struct sdhci_cdns_drv_data sdhci_elba_drv_data =3D { + .init =3D elba_drv_init, + .pltfm_data =3D { + .ops =3D &sdhci_elba_ops, + }, +}; + +static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data =3D { + .pltfm_data =3D { + .ops =3D &sdhci_cdns_ops, + }, }; =20 static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, @@ -357,7 +461,7 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc= _host *mmc, static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; - const struct sdhci_pltfm_data *data; + const struct sdhci_cdns_drv_data *data; struct sdhci_pltfm_host *pltfm_host; struct sdhci_cdns_priv *priv; struct clk *clk; @@ -376,10 +480,10 @@ static int sdhci_cdns_probe(struct platform_device *p= dev) =20 data =3D of_device_get_match_data(dev); if (!data) - data =3D &sdhci_cdns_pltfm_data; + data =3D &sdhci_cdns_drv_data; =20 nr_phy_params =3D sdhci_cdns_phy_param_count(dev->of_node); - host =3D sdhci_pltfm_init(pdev, data, + host =3D sdhci_pltfm_init(pdev, &data->pltfm_data, struct_size(priv, phy_params, nr_phy_params)); if (IS_ERR(host)) { ret =3D PTR_ERR(host); @@ -397,6 +501,11 @@ static int sdhci_cdns_probe(struct platform_device *pd= ev) host->ioaddr +=3D SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe =3D sdhci_cdns_hs400_enhanced_strobe; + if (data->init) { + ret =3D data->init(pdev); + if (ret) + goto free; + } sdhci_enable_v4_mode(host); __sdhci_read_caps(host, &version, NULL, NULL); =20 @@ -461,7 +570,11 @@ static const struct dev_pm_ops sdhci_cdns_pm_ops =3D { static const struct of_device_id sdhci_cdns_match[] =3D { { .compatible =3D "socionext,uniphier-sd4hc", - .data =3D &sdhci_cdns_uniphier_pltfm_data, + .data =3D &sdhci_cdns_uniphier_drv_data, + }, + { + .compatible =3D "amd,pensando-elba-sd4hc", + .data =3D &sdhci_elba_drv_data, }, { .compatible =3D "cdns,sd4hc" }, { /* sentinel */ } --=20 2.17.1 From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C19AC38142 for ; Thu, 19 Jan 2023 04:29:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229917AbjASE3i (ORCPT ); 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Wed, 18 Jan 2023 19:41:18 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 14/15] mmc: sdhci-cadence: Support mmc hardware reset Date: Wed, 18 Jan 2023 19:39:17 -0800 Message-Id: <20230119033918.44117-15-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for mmc hardware reset using a reset-controller that would need to be enabled in the device tree with a supporting driver. The default is disabled for all existing designs. Signed-off-by: Brad Larson --- Changes since v6: - Previously patch 17/17 - Changed delay after reset_control_assert() from 9 to 3 usec - Renamed sdhci_mmc_hw_reset() to sdhci_cdns_mmc_hw_reset() --- drivers/mmc/host/sdhci-cadence.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cade= nce.c index e92aa79a8be2..62321cef41db 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 #include "sdhci-pltfm.h" =20 @@ -70,6 +71,7 @@ struct sdhci_cdns_priv { spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *= reg); + struct reset_control *rst_hw; unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -458,6 +460,24 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mm= c_host *mmc, SDHCI_CDNS_HRS06_MODE_MMC_HS400); } =20 +extern unsigned int sdhci_timeout_val; + +static void sdhci_cdns_mmc_hw_reset(struct mmc_host *mmc) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct sdhci_cdns_priv *priv =3D sdhci_cdns_priv(host); + + dev_dbg(mmc_dev(host->mmc), "emmc hardware reset\n"); + + reset_control_assert(priv->rst_hw); + /* For eMMC, minimum is 1us but give it 3us for good measure */ + udelay(3); + + reset_control_deassert(priv->rst_hw); + /* For eMMC, minimum is 200us but give it 300us for good measure */ + usleep_range(300, 1000); +} + static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; @@ -521,6 +541,17 @@ static int sdhci_cdns_probe(struct platform_device *pd= ev) if (ret) goto free; =20 + if (host->mmc->caps & MMC_CAP_HW_RESET) { + priv->rst_hw =3D devm_reset_control_get_optional_exclusive(dev, "hw"); + if (IS_ERR(priv->rst_hw)) { + ret =3D PTR_ERR(priv->rst_hw); + if (ret =3D=3D -ENOENT) + priv->rst_hw =3D NULL; + } else { + host->mmc_host_ops.card_hw_reset =3D sdhci_cdns_mmc_hw_reset; + } + } + ret =3D sdhci_add_host(host); if (ret) goto free; --=20 2.17.1 From nobody Sun Sep 14 18:27:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7311CC678D4 for ; Thu, 19 Jan 2023 04:28:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230127AbjASE2b (ORCPT ); Wed, 18 Jan 2023 23:28:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229813AbjASDqc (ORCPT ); Wed, 18 Jan 2023 22:46:32 -0500 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 761636D680 for ; Wed, 18 Jan 2023 19:42:18 -0800 (PST) Received: by mail-pf1-x42f.google.com with SMTP id 200so517095pfx.7 for ; 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Wed, 18 Jan 2023 19:41:28 -0800 (PST) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id f13-20020aa7968d000000b0056b4c5dde61sm11097879pfk.98.2023.01.18.19.41.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 19:41:27 -0800 (PST) From: Brad Larson X-Google-Original-From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 15/15] spi: pensando-sr: Add AMD Pensando SoC System Resource Date: Wed, 18 Jan 2023 19:39:18 -0800 Message-Id: <20230119033918.44117-16-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119033918.44117-1-blarson@amd.com> References: <20230119033918.44117-1-blarson@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the AMD Pensando SoC System Resource chip using the SPI interface. The device functions are accessed using four chip-selects and the device can be a CPLD or FPGA depending on functionality. Signed-off-by: Brad Larson --- Changes since v6: - Previously patch 14/17 - After the change to the device tree node and squashing reset-cells into the parent simplified this to not use any MFD API and move it to drivers/spi/pensando-sr.c. - Change the naming to remove elba since this driver is common for all Pensando SoC designs . - Default yes SPI_PENSANDO_SR for ARCH_PENSANDO --- drivers/spi/Kconfig | 14 ++ drivers/spi/Makefile | 1 + drivers/spi/spi-pensando-sr.c | 454 ++++++++++++++++++++++++++++++++++ 3 files changed, 469 insertions(+) create mode 100644 drivers/spi/spi-pensando-sr.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3b1c0878bb85..1e8605c59a0e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -730,6 +730,20 @@ config SPI_PCI1XXXX This driver can be built as module. If so, the module will be called as spi-pci1xxxx. =20 +config SPI_PENSANDO_SR + bool "AMD Pensando SoC System Resource chip" + depends on SPI_MASTER=3Dy + depends on (ARCH_PENSANDO && OF) || COMPILE_TEST + default y if ARCH_PENSANDO + select REGMAP_SPI + select MFD_SYSCON + help + Support for the AMD Pensando SoC System Resource chip using the + SPI interface. This driver provides userspace access to the SPI + device functions via multiple chip selects. The device can be + a CPLD or FPGA depending on the functionality required and is + present in all Pensando SoC based designs. + config SPI_PIC32 tristate "Microchip PIC32 series SPI" depends on MACH_PIC32 || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index be9ba40ef8d0..71e0a95c6d88 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_SPI_OMAP_100K) +=3D spi-omap-100k.o obj-$(CONFIG_SPI_OMAP24XX) +=3D spi-omap2-mcspi.o obj-$(CONFIG_SPI_TI_QSPI) +=3D spi-ti-qspi.o obj-$(CONFIG_SPI_ORION) +=3D spi-orion.o +obj-$(CONFIG_SPI_PENSANDO_SR) +=3D spi-pensando-sr.o obj-$(CONFIG_SPI_PCI1XXXX) +=3D spi-pci1xxxx.o obj-$(CONFIG_SPI_PIC32) +=3D spi-pic32.o obj-$(CONFIG_SPI_PIC32_SQI) +=3D spi-pic32-sqi.o diff --git a/drivers/spi/spi-pensando-sr.c b/drivers/spi/spi-pensando-sr.c new file mode 100644 index 000000000000..91c64bcfba04 --- /dev/null +++ b/drivers/spi/spi-pensando-sr.c @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD Pensando SoC System Resource Driver + * + * Userspace interface and reset driver support for SPI + * connected Pensando SoC System Resource Chip. This + * device is present in all Pensando SoC based designs. + * This file is derived in part from spi/spidev.c. + * + * Copyright (C) 2006 SWAPP + * Andrea Paterniani + * Copyright (C) 2007 David Brownell (simplification, cleanup) + * Copyright 2023 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PENSR_MAX_REG 0xff +#define PENSR_CTRL0_REG 0x10 +#define PENSR_SPI_CMD_REGRD 0x0b +#define PENSR_SPI_CMD_REGWR 0x02 +#define SPI_IOC_MAGIC 'k' + +#define SPI_MSGSIZE(N) \ + ((((N)*(sizeof(struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ + ? ((N)*(sizeof(struct spi_ioc_transfer))) : 0) +#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) + +struct spi_ioc_transfer { + __u64 tx_buf; + __u64 rx_buf; + __u32 len; + __u32 speed_hz; + __u16 delay_usecs; + __u8 bits_per_word; + __u8 cs_change; + __u8 tx_nbits; + __u8 rx_nbits; + __u8 word_delay_usecs; + __u8 pad; +}; + +struct pensr_device { + struct spi_device *spi_dev; + struct reset_controller_dev rcdev; + struct mutex buf_lock; + spinlock_t spi_lock; + u8 *tx_buffer; + u8 *rx_buffer; +}; + +static dev_t pensr_devt; +static struct pensr_device *pensr; +static struct class *pensr_class; +static unsigned int bufsiz =3D 4096; + +static struct spi_ioc_transfer * +pensr_spi_get_ioc_message(unsigned int cmd, + struct spi_ioc_transfer __user *u_ioc, + unsigned int *n_ioc) +{ + u32 tmp; + + /* Check type, command number and direction */ + if (_IOC_TYPE(cmd) !=3D SPI_IOC_MAGIC + || _IOC_NR(cmd) !=3D _IOC_NR(SPI_IOC_MESSAGE(0)) + || _IOC_DIR(cmd) !=3D _IOC_WRITE) + return ERR_PTR(-ENOTTY); + + tmp =3D _IOC_SIZE(cmd); + if ((tmp % sizeof(struct spi_ioc_transfer)) !=3D 0) + return ERR_PTR(-EINVAL); + *n_ioc =3D tmp / sizeof(struct spi_ioc_transfer); + if (*n_ioc =3D=3D 0) + return NULL; + + /* copy into scratch area */ + return memdup_user(u_ioc, tmp); +} + +static long +pensr_spi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + struct spi_transfer t[2] =3D { 0 }; + struct spi_ioc_transfer *u_xfers; + struct spi_ioc_transfer *u_xfer; + struct pensr_device *pensr; + struct spi_device *spi_dev; + unsigned int n_xfers; + struct spi_message m; + u8 *tx_buf; + u8 *rx_buf; + int ret; + + /* Check type and command number */ + if (_IOC_TYPE(cmd) !=3D SPI_IOC_MAGIC) + return -ENOTTY; + + pensr =3D filp->private_data; + if (!pensr) + return -ESHUTDOWN; + + tx_buf =3D pensr->tx_buffer; + rx_buf =3D pensr->rx_buffer; + + spin_lock_irq(&pensr->spi_lock); + spi_dev =3D spi_dev_get(pensr->spi_dev); + spin_unlock_irq(&pensr->spi_lock); + if (spi_dev =3D=3D NULL) + return -ESHUTDOWN; + + /* Use the buffer lock here for triple duty: + * - prevent I/O (from us) so calling spi_setup() is safe; + * - prevent concurrent SPI_IOC_WR_* from morphing + * data fields while SPI_IOC_RD_* reads them; + * - SPI_IOC_MESSAGE needs the buffer locked "normally". + */ + mutex_lock(&pensr->buf_lock); + + u_xfers =3D pensr_spi_get_ioc_message(cmd, + (struct spi_ioc_transfer __user *)arg, &n_xfers); + if (IS_ERR(u_xfers)) { + ret =3D PTR_ERR(u_xfers); + goto done; + } + if (!u_xfers) + goto done; + u_xfer =3D u_xfers; + + t[0].tx_buf =3D tx_buf; + t[0].len =3D u_xfer->len; + if (copy_from_user(tx_buf, (const u8 __user *) (uintptr_t) u_xfer->tx_buf= , u_xfer->len)) { + ret =3D -EFAULT; + goto done; + } + + if (n_xfers > 1) { + u_xfer++; + t[1].rx_buf =3D rx_buf; + t[1].len =3D u_xfer->len; + } + + spi_message_init_with_transfers(&m, t, n_xfers); + ret =3D spi_sync(spi_dev, &m); + if (ret < 0) + goto done; + + if (n_xfers > 1) { + if (copy_to_user((u8 __user *)(uintptr_t)u_xfer->rx_buf, rx_buf, u_xfer-= >len)) { + ret =3D -EFAULT; + goto done; + } + } + +done: + mutex_unlock(&pensr->buf_lock); + spi_dev_put(spi_dev); + return ret; +} + +static int pensr_spi_open(struct inode *inode, struct file *filp) +{ + struct spi_device *spi_dev; + int status =3D -ENXIO; + u8 current_cs; + + if (!pensr) + return -ENODEV; + + filp->private_data =3D pensr; + current_cs =3D iminor(inode); + spi_dev =3D pensr->spi_dev; + spi_dev->chip_select =3D current_cs; + spi_dev->cs_gpiod =3D spi_dev->controller->cs_gpiods[current_cs]; + spi_setup(spi_dev); + + if (!pensr->tx_buffer) { + pensr->tx_buffer =3D kmalloc(bufsiz, GFP_KERNEL); + memset(pensr->tx_buffer, 0, bufsiz); + if (!pensr->tx_buffer) { + status =3D -ENOMEM; + goto err_alloc_tx_buf; + } + } + if (!pensr->rx_buffer) { + pensr->rx_buffer =3D kmalloc(bufsiz, GFP_KERNEL); + memset(pensr->rx_buffer, 0, bufsiz); + if (!pensr->rx_buffer) { + status =3D -ENOMEM; + goto err_alloc_rx_buf; + } + } + stream_open(inode, filp); + return 0; + +err_alloc_rx_buf: + kfree(pensr->tx_buffer); + pensr->tx_buffer =3D NULL; +err_alloc_tx_buf: + return status; +} + +static int pensr_spi_release(struct inode *inode, struct file *filp) +{ + filp->private_data =3D NULL; + return 0; +} + +static const struct file_operations pensr_spi_fops =3D { + .owner =3D THIS_MODULE, + .unlocked_ioctl =3D pensr_spi_ioctl, + .open =3D pensr_spi_open, + .release =3D pensr_spi_release, + .llseek =3D no_llseek, +}; + +static int pensr_regs_read(struct pensr_device *pensr, u32 reg, u32 *val) +{ + struct spi_device *spi_dev =3D pensr->spi_dev; + struct spi_transfer t[2] =3D { 0 }; + struct spi_message m; + u8 txbuf[3]; + u8 rxbuf[1]; + int ret; + + txbuf[0] =3D PENSR_SPI_CMD_REGRD; + txbuf[1] =3D reg; + txbuf[2] =3D 0x0; + t[0].tx_buf =3D (u8 *)txbuf; + t[0].len =3D 3; + + rxbuf[0] =3D 0x0; + t[1].rx_buf =3D rxbuf; + t[1].len =3D 1; + + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + ret =3D spi_sync(spi_dev, &m); + if (ret =3D=3D 0) { + /* 3 Tx + 1 Rx =3D 4 */ + *val =3D rxbuf[0]; + } + return ret; +} + +static int pensr_regs_write(struct pensr_device *pensr, u32 reg, u32 val) +{ + struct spi_device *spi_dev =3D pensr->spi_dev; + struct spi_transfer t[1] =3D { 0 }; + struct spi_message m; + u8 txbuf[4]; + int ret; + + spi_dev->chip_select =3D 0; + spi_dev->cs_gpiod =3D spi_dev->controller->cs_gpiods[0]; + spi_setup(spi_dev); + + txbuf[0] =3D PENSR_SPI_CMD_REGWR; + txbuf[1] =3D reg; + txbuf[2] =3D val; + txbuf[3] =3D 0; + + t[0].tx_buf =3D txbuf; + t[0].len =3D 4; + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + ret =3D spi_sync(spi_dev, &m); + return ret; +} + +static int pensr_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct pensr_device *pensr =3D + container_of(rcdev, struct pensr_device, rcdev); + struct spi_device *spi_dev =3D pensr->spi_dev; + unsigned int val; + int ret; + + spin_lock_irq(&pensr->spi_lock); + spi_dev->chip_select =3D 0; + spi_dev->cs_gpiod =3D spi_dev->controller->cs_gpiods[spi_dev->chip_select= ]; + spi_setup(spi_dev); + + ret =3D pensr_regs_read(pensr, PENSR_CTRL0_REG, &val); + if (ret) { + dev_err(&spi_dev->dev, "error reading ctrl0 reg\n"); + goto done; + } + + val |=3D BIT(6); + ret =3D pensr_regs_write(pensr, PENSR_CTRL0_REG, val); + if (ret) + dev_err(&spi_dev->dev, "error writing ctrl0 reg\n"); + +done: + spin_unlock_irq(&pensr->spi_lock); + return ret; +} + +static int pensr_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct pensr_device *pensr =3D + container_of(rcdev, struct pensr_device, rcdev); + struct spi_device *spi_dev =3D pensr->spi_dev; + unsigned int val; + int ret; + + spin_lock_irq(&pensr->spi_lock); + spi_dev->chip_select =3D 0; + spi_dev->cs_gpiod =3D spi_dev->controller->cs_gpiods[spi_dev->chip_select= ]; + spi_setup(spi_dev); + + ret =3D pensr_regs_read(pensr, PENSR_CTRL0_REG, &val); + if (ret) { + dev_err(&spi_dev->dev, "error reading ctrl0 reg\n"); + goto done; + } + + val &=3D ~BIT(6); + ret =3D pensr_regs_write(pensr, PENSR_CTRL0_REG, val); + if (ret) + dev_err(&spi_dev->dev, "error writing ctrl0 reg\n"); + +done: + spin_unlock_irq(&pensr->spi_lock); + return ret; +} + +static const struct reset_control_ops pensr_reset_ops =3D { + .assert =3D pensr_reset_assert, + .deassert =3D pensr_reset_deassert, +}; + +static int pensr_spi_probe(struct spi_device *spi_dev) +{ + struct device_node *np; + struct property *prop; + struct device *dev; + struct cdev *cdev; + const __be32 *p; + int status; + u32 num_cs; + u32 cs; + + np =3D spi_dev->dev.parent->of_node; + status =3D of_property_read_u32(np, "num-cs", &num_cs); + if (status) + return dev_err_probe(&spi_dev->dev, status, + "number of chip-selects not defined"); + + status =3D alloc_chrdev_region(&pensr_devt, 0, num_cs, "pensr"); + if (status) + return dev_err_probe(&spi_dev->dev, status, + "failed to alloc chrdev region\n"); + + pensr_class =3D class_create(THIS_MODULE, "pensr"); + if (IS_ERR(pensr_class)) { + unregister_chrdev(MAJOR(pensr_devt), "pensr"); + return dev_err_probe(&spi_dev->dev, PTR_ERR(pensr_class), + "failed to create class\n"); + } + + cdev =3D cdev_alloc(); + if (!cdev) { + dev_err(&spi_dev->dev, "allocation of cdev failed"); + status =3D -ENOMEM; + goto cdev_failed; + } + cdev->owner =3D THIS_MODULE; + cdev_init(cdev, &pensr_spi_fops); + + status =3D cdev_add(cdev, pensr_devt, num_cs); + if (status) { + dev_err(&spi_dev->dev, "register of cdev failed"); + goto cdev_delete; + } + + /* Allocate driver data */ + pensr =3D kzalloc(sizeof(*pensr), GFP_KERNEL); + if (!pensr) { + status =3D -ENOMEM; + dev_err(&spi_dev->dev, "allocate driver data failed"); + goto cdev_delete; + } + + pensr->spi_dev =3D spi_dev; + spin_lock_init(&pensr->spi_lock); + mutex_init(&pensr->buf_lock); + + /* Create a device for each chip select */ + np =3D spi_dev->dev.of_node; + of_property_for_each_u32(np, "cs", prop, p, cs) { + dev =3D device_create(pensr_class, + &spi_dev->dev, + MKDEV(MAJOR(pensr_devt), cs), + pensr, + "pensr0.%d", + cs); + if (IS_ERR(dev)) { + status =3D IS_ERR(dev); + dev_err(&spi_dev->dev, "error creating device\n"); + goto cdev_delete; + } + dev_dbg(&spi_dev->dev, "created device major %u, minor %d\n", + MAJOR(pensr_devt), cs); + } + + spi_set_drvdata(spi_dev, pensr); + + /* Register emmc hardware reset */ + pensr->rcdev.nr_resets =3D 1; + pensr->rcdev.owner =3D THIS_MODULE; + pensr->rcdev.dev =3D &spi_dev->dev; + pensr->rcdev.ops =3D &pensr_reset_ops; + pensr->rcdev.of_node =3D spi_dev->dev.of_node; + status =3D reset_controller_register(&pensr->rcdev); + if (status) + return dev_err_probe(&spi_dev->dev, status, + "failed to register reset controller\n"); + return status; + +cdev_delete: + cdev_del(cdev); +cdev_failed: + device_destroy(pensr_class, pensr_devt); + return status; +} + +static const struct of_device_id pensr_dt_match[] =3D { + { .compatible =3D "amd,pensando-sr" }, + { /* sentinel */ } +}; + +static struct spi_driver pensr_spi_driver =3D { + .probe =3D pensr_spi_probe, + .driver =3D { + .name =3D "pensando-sr", + .of_match_table =3D pensr_dt_match, + }, +}; +builtin_driver(pensr_spi_driver, spi_register_driver) --=20 2.17.1