From nobody Sun Sep 14 18:44:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DB65C38147 for ; Wed, 18 Jan 2023 23:05:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229690AbjARXFj (ORCPT ); Wed, 18 Jan 2023 18:05:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229729AbjARXFe (ORCPT ); Wed, 18 Jan 2023 18:05:34 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EFA718B29 for ; Wed, 18 Jan 2023 15:05:33 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id q8so254381wmo.5 for ; Wed, 18 Jan 2023 15:05:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j9t+nJhU1TxVP3oL4wSVLTcJWhtOVpj322EGpgkez6I=; b=Rf9IBBa2EREPtWcyRJFgglmlREzdh/V9lvpXwr+lw9TowUzVfNebwZQfbhBF51jVpV XdW591rkuoy0QDQlhRraYVH6mILifk5Mw9gTuY34hu/GNNufocJBLhhGKOn58oGsab7T K96Z8SBgBZZVFStdV3/rG5J5kB+edbrw0JWUVuGpsaFBoIuM0moNqbq9a2KezHiwZdR9 0O4CJhYXhA5YMqz5xTDqdToq92DHW90FS0WVVQ8iUQKxYxDc7Io5bXkbIpOeYFXXN1hk /uWm44zl0VZ96efkNtzqCx55tvOLBwChflpDpP5jS23GjtrCUNwoYzkS5hKa62Elr8Jq 3Lyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j9t+nJhU1TxVP3oL4wSVLTcJWhtOVpj322EGpgkez6I=; b=1g9P+7GGR2p8x8Gx/GtfPMg8DzMgrqOfVu8FbmIcOO5TAnMi2q9Ee0aShFWceiHuQL 4sx47xn75RavnhAOpHIK7umNXwK2Ipr7lE4+erxgj447yvULUiU5bmnNdVF2OT7tEAhq 6bbr6mHJIjrDMJSAVKL4ATra7tKwNdtJWDQzi2jdJRtg83bztAnWpt7H3Bqf4GbS5USl Kh4vZ/azcindtI5Xi6Kqmh1NHZGggPCA6SAWstysUUUOMtcVyPKQxvsEpbJkX7ASZxy4 QiZsBxjKUzeaR7aPdarOZxXdWQReQJcslzEad6e64ltugBI84Tg4Vl2doKdpIwd6FI9c gdKg== X-Gm-Message-State: AFqh2kr+PfG4Niy+RkVfAndlvGrcFL67OJMvbKxWN+149fhmHQi7STdS sc9aKtkKs7DXp0Nklz02Lk9sPA== X-Google-Smtp-Source: AMrXdXujBlavBknrj2BIESAMAyZqiEaNxMVrPIzX7O6pNBXfYaZK9O56WhckY5iNXknYrgasLZm8Tg== X-Received: by 2002:a05:600c:2e14:b0:3d4:a1ba:a971 with SMTP id o20-20020a05600c2e1400b003d4a1baa971mr8045714wmf.24.1674083132188; Wed, 18 Jan 2023 15:05:32 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id o2-20020a05600c510200b003c6f8d30e40sm3523314wms.31.2023.01.18.15.05.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 15:05:31 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v2 1/2] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes Date: Thu, 19 Jan 2023 01:05:25 +0200 Message-Id: <20230118230526.1499328-2-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230118230526.1499328-1-abel.vesa@linaro.org> References: <20230118230526.1499328-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PCIe controllers and PHY nodes. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 213 ++++++++++++++++++++++++++- 1 file changed, 210 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 3d47281a276b..a78068cbf95f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -646,9 +646,9 @@ gcc: clock-controller@100000 { #reset-cells =3D <1>; #power-domain-cells =3D <1>; clocks =3D <&bi_tcxo_div2>, <&sleep_clk>, - <0>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, + <&pcie_1_phy_aux_clk>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -1547,6 +1547,213 @@ mmss_noc: interconnect@1780000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + pcie0: pci@1c00000 { + device_type =3D "pci"; + compatible =3D "qcom,pcie-sm8550"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <0>; + num-lanes =3D <2>; + + interrupts =3D ; + interrupt-names =3D "msi"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int= _a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0"; + + interconnect-names =3D "pcie-mem"; + interconnects =3D <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>; + + iommus =3D <&apps_smmu 0x1400 0x7f>; + iommu-map =3D <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_default_state>; + + status =3D "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible =3D "qcom,sm8550-qmp-gen3x2-pcie-phy"; + reg =3D <0 0x01c06000 0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names =3D "aux", "cfg_ahb", "ref", "rchng", + "pipe"; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + power-domains =3D <&gcc PCIE_0_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie0_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie1: pci@1c08000 { + device_type =3D "pci"; + compatible =3D "qcom,pcie-sm8550"; + reg =3D <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <1>; + num-lanes =3D <2>; + + interrupts =3D ; + interrupt-names =3D "msi"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int= _a */ + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks =3D <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre1", + "cnoc_pcie_sf_axi"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnect-names =3D "pcie-mem"; + interconnects =3D <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>; + + iommus =3D <&apps_smmu 0x1480 0x7f>; + iommu-map =3D <0x0 &apps_smmu 0x1480 0x1>, + <0x100 &apps_smmu 0x1481 0x1>; + + resets =3D <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names =3D "pci", + "pcie_1_link_down_reset"; + + power-domains =3D <&gcc PCIE_1_GDSC>; + + phys =3D <&pcie1_phy>; + phy-names =3D "pciephy"; + + perst-gpios =3D <&tlmm 97 GPIO_ACTIVE_LOW>; + enable-gpios =3D <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_default_state>; + + status =3D "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible =3D "qcom,sm8550-qmp-gen4x2-pcie-phy"; + reg =3D <0x0 0x01c0e000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PHY_AUX_CLK>; + clock-names =3D "aux", "cfg_ahb", "ref", "rchng", + "pipe", "aux_phy"; + + resets =3D <&gcc GCC_PCIE_1_PHY_BCR>, + <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", "nocsr"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + power-domains =3D <&gcc PCIE_1_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie1_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + cryptobam: dma-controller@1dc4000 { compatible =3D "qcom,bam-v1.7.0"; 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Wed, 18 Jan 2023 15:05:33 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id o2-20020a05600c510200b003c6f8d30e40sm3523314wms.31.2023.01.18.15.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 15:05:32 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Neil Armstrong Subject: [PATCH v2 2/2] arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes Date: Thu, 19 Jan 2023 01:05:26 +0200 Message-Id: <20230118230526.1499328-3-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230118230526.1499328-1-abel.vesa@linaro.org> References: <20230118230526.1499328-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable PCIe controllers and PHYs nodes on SM8550 MTP board. Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 29 +++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8550-mtp.dts index 81fcbdc6bdc4..b69ded9c4b57 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -359,6 +359,35 @@ vreg_l3g_1p2: ldo3 { }; }; =20 +&pcie_1_phy_aux_clk { + clock-frequency =3D <1000>; +}; + +&pcie0 { + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l1e_0p88>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + status =3D "okay"; +}; + +&pcie1 { + wake-gpios =3D <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 97 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l3c_0p91>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + vdda-qref-supply =3D <&vreg_l1e_0p88>; + status =3D "okay"; +}; + &pm8550_gpios { sdc2_card_det_n: sdc2-card-det-state { pins =3D "gpio12"; --=20 2.34.1