From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D97FDC32793 for ; Wed, 18 Jan 2023 15:06:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229968AbjARPGZ (ORCPT ); Wed, 18 Jan 2023 10:06:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231305AbjARPGP (ORCPT ); Wed, 18 Jan 2023 10:06:15 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A91DA8A72; Wed, 18 Jan 2023 07:06:12 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 30IF5m4n046516; Wed, 18 Jan 2023 09:05:48 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1674054348; bh=yeMuyvf0CNYri6p9yVKI+iipvOaqkrcmBQdptZ908h4=; h=From:To:CC:Subject:Date; b=AYS1mSU4HYBKioA7ETXVx5f1W6RrC1qL7cvnV3Bnhy9/Lny6YP3YFSY2kygkk2i5J ZYS4Wu5V5iRZqPTrNrRyC+Yvy+huzucz8InyGUcdbINsfDQUayRMSyjtsylp0GmXRP uvM555Y+PGW5fqdxIMFpgJ6figt21TDUgzmX0Rb8= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 30IF5mPR090521 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 18 Jan 2023 09:05:48 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 18 Jan 2023 09:05:47 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 18 Jan 2023 09:05:47 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30IF5kUp114843; Wed, 18 Jan 2023 09:05:47 -0600 From: Achal Verma To: Tom Joseph , Lorenzo Pieralisi , Rob Herring , Krzysztof Wilczy_ski , Bjorn Helgaas , Vignesh Raghavendra CC: , , , , Achal Verma , Milind Parab Subject: [PATCH v2] PCI: cadence: Fix next function value in case of ARI Date: Wed, 18 Jan 2023 20:35:46 +0530 Message-ID: <20230118150546.3477995-1-a-verma1@ti.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jasko-EXT Wojciech Next function field in ARI_CAP_AND_CTR register for last function should be zero by default as per the PCIe spec but thats not the case, so this pat= ch clears the next function field for last function used. Signed-off-by: Jasko-EXT Wojciech Signed-off-by: Achal Verma --- drivers/pci/controller/cadence/pcie-cadence-ep.c | 14 +++++++++++++- drivers/pci/controller/cadence/pcie-cadence.h | 6 ++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci= /controller/cadence/pcie-cadence-ep.c index b8b655d4047e..8742b2f594fd 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -565,7 +565,8 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) struct cdns_pcie *pcie =3D &ep->pcie; struct device *dev =3D pcie->dev; int max_epfs =3D sizeof(epc->function_num_map) * 8; - int ret, value, epf; + int ret, epf, last_fn; + u32 reg, value; =20 /* * BIT(0) is hardwired to 1, hence function 0 is always enabled @@ -573,6 +574,17 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) */ cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, epc->function_num_map); =20 + /* + * Next function field in ARI_CAP_AND_CTR register for last function + * should be 0. + * Clearing Next Function Number field for the last function used. + */ + last_fn =3D find_last_bit(&epc->function_num_map, BITS_PER_LONG); + reg =3D CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(last_fn); + value =3D cdns_pcie_readl(pcie, reg); + value &=3D ~CDNS_PCIE_ARI_CAP_NFN_MASK; + cdns_pcie_writel(pcie, reg, value); + if (ep->quirk_disable_flr) { for (epf =3D 0; epf < max_epfs; epf++) { if (!(epc->function_num_map & BIT(epf))) diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 190786e47df9..68c4c7878111 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -130,6 +130,12 @@ #define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 #define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 =20 +/* + * Endpoint PF Registers + */ +#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) +#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) + /* * Root Port Registers (PCI configuration space for the root port function) */ --=20 2.25.1