From nobody Sun Sep 14 22:15:24 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6E88C32793 for ; Wed, 18 Jan 2023 14:24:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231341AbjAROYn (ORCPT ); Wed, 18 Jan 2023 09:24:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231286AbjAROYO (ORCPT ); Wed, 18 Jan 2023 09:24:14 -0500 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0C9A2B61D for ; Wed, 18 Jan 2023 06:08:38 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id bg13-20020a05600c3c8d00b003d9712b29d2so1497491wmb.2 for ; Wed, 18 Jan 2023 06:08:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=duqmnhR5K9247EJ6cHsWMiIh8qcMK5ejH7rRbGmIEZo=; b=o9yqird1SKP+sBzVmSQhzdijmtuLNHCGvt19o0LArmjiJRVkXULbQEQav6mPqlZ+mD FAke5jDHVaZd4uW4XMhlRioUVjyB0OVG5SbL+RqK1ulGTPBVkO1PlDDRrHw3yjQRbCvu mM12NxjpV9nU0aqt9uSkYJ6A5Lbvb38VwEyOO4Jo5E3utvPa6V7XL2/fpSTD6yxs254o QQUwHnPITKumITJEs9kdsPaF1Uzm9QWg0WRYH/3f3F/GMP25zxk8tQkiJxR8peUM1zaG MPH5URqFV9aAQCDq7Qc0+t8zHln2UXJlUvbcdi7aROyhrpX7nbn3sdHwa2ysY5Kebrjk 8dXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=duqmnhR5K9247EJ6cHsWMiIh8qcMK5ejH7rRbGmIEZo=; b=0fFcbnG0kf3Ly9RWkz9ZJy7Bs6eXW+dIrlPxtWTcGrARtPD4DPU3k0rPL8ukWuuigZ AkUyuFuBDqWIk4kS+Qf6b8jw/mbPgoIqzJ83eA9blf1sAXK/+BLSsgKhf9oFjGsE8c8P wFGGkngrqsIbtiT/V7zpy8muQH//eGt5PTJp6M/kKH/saqFRfe0awSiuvnvXZfg6sB7/ sNbUNi4K36Ta2SNrKKdbVJXwuq5Z2KDG7plj2L4402qVGlCV0X+1yvTn1sK0lMcpgmXa Qbr07gC93+T/jgacq7uylE96zfzsmO4nfOXEic7r38wUPeE+x7t9SSe8X+NbEYVvkld6 pyzw== X-Gm-Message-State: AFqh2kr9Tt6Q5I843qiDe4uZ0GxaDEDJ4eLTTChC2iVkU3jJkkODTAwO sfen+q1up3BoAV47Ca6BP1D5AQ== X-Google-Smtp-Source: AMrXdXvShQ3H2xUIhrRjSN/tfP0Gq7z372wubbadEyHCD9bfGbmOnLV97lJDpl98hUBZ8ufxP+l8TA== X-Received: by 2002:a05:600c:3551:b0:3d2:813:138a with SMTP id i17-20020a05600c355100b003d20813138amr15496357wmq.35.1674050917154; Wed, 18 Jan 2023 06:08:37 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:1866:5d91:a429:aba]) by smtp.gmail.com with ESMTPSA id m27-20020a05600c3b1b00b003db012d49b7sm3193431wms.2.2023.01.18.06.08.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 06:08:36 -0800 (PST) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shazad Hussain , Bartosz Golaszewski Subject: [PATCH v2 2/2] interconnect: qcom: add a driver for sa8775p Date: Wed, 18 Jan 2023 15:08:25 +0100 Message-Id: <20230118140825.242544-3-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230118140825.242544-1-brgl@bgdev.pl> References: <20230118140825.242544-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Shazad Hussain Introduce QTI SA8775P-specific interconnect driver. Signed-off-by: Shazad Hussain [Bartosz: made the driver ready for upstream] Co-developed-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/sa8775p.c | 2541 +++++++++++++++++++++++++++ 3 files changed, 2552 insertions(+) create mode 100644 drivers/interconnect/qcom/sa8775p.c diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index cd689b782f97..3132a03ca974 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -92,6 +92,15 @@ config INTERCONNECT_QCOM_RPMH_POSSIBLE config INTERCONNECT_QCOM_RPMH tristate =20 +config INTERCONNECT_QCOM_SA8775P + tristate "Qualcomm SA8775P interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on sa8775p-based + platforms. + config INTERCONNECT_QCOM_SC7180 tristate "Qualcomm SC7180 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 3fd4c2713c4a..75df2cf64c0b 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -13,6 +13,7 @@ qnoc-qcm2290-objs :=3D qcm2290.o qnoc-qcs404-objs :=3D qcs404.o qnoc-qdu1000-objs :=3D qdu1000.o icc-rpmh-obj :=3D icc-rpmh.o +qnoc-sa8775p-objs :=3D sa8775p.o qnoc-sc7180-objs :=3D sc7180.o qnoc-sc7280-objs :=3D sc7280.o qnoc-sc8180x-objs :=3D sc8180x.o @@ -39,6 +40,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) +=3D qnoc-qcm2290= .o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) +=3D qnoc-qcs404.o obj-$(CONFIG_INTERCONNECT_QCOM_QDU1000) +=3D qnoc-qdu1000.o obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) +=3D icc-rpmh.o +obj-$(CONFIG_INTERCONNECT_QCOM_SA8775P) +=3D qnoc-sa8775p.o obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) +=3D qnoc-sc7180.o obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) +=3D qnoc-sc7280.o obj-$(CONFIG_INTERCONNECT_QCOM_SC8180X) +=3D qnoc-sc8180x.o diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qco= m/sa8775p.c new file mode 100644 index 000000000000..da21cc31a580 --- /dev/null +++ b/drivers/interconnect/qcom/sa8775p.c @@ -0,0 +1,2541 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights re= served. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +#define SA8775P_MASTER_GPU_TCU 0 +#define SA8775P_MASTER_PCIE_TCU 1 +#define SA8775P_MASTER_SYS_TCU 2 +#define SA8775P_MASTER_APPSS_PROC 3 +#define SA8775P_MASTER_LLCC 4 +#define SA8775P_MASTER_CNOC_LPASS_AG_NOC 5 +#define SA8775P_MASTER_GIC_AHB 6 +#define SA8775P_MASTER_CDSP_NOC_CFG 7 +#define SA8775P_MASTER_CDSPB_NOC_CFG 8 +#define SA8775P_MASTER_QDSS_BAM 9 +#define SA8775P_MASTER_QUP_0 10 +#define SA8775P_MASTER_QUP_1 11 +#define SA8775P_MASTER_QUP_2 12 +#define SA8775P_MASTER_A1NOC_SNOC 13 +#define SA8775P_MASTER_A2NOC_SNOC 14 +#define SA8775P_MASTER_CAMNOC_HF 15 +#define SA8775P_MASTER_CAMNOC_ICP 16 +#define SA8775P_MASTER_CAMNOC_SF 17 +#define SA8775P_MASTER_COMPUTE_NOC 18 +#define SA8775P_MASTER_COMPUTE_NOC_1 19 +#define SA8775P_MASTER_CNOC_A2NOC 20 +#define SA8775P_MASTER_CNOC_DC_NOC 21 +#define SA8775P_MASTER_GEM_NOC_CFG 22 +#define SA8775P_MASTER_GEM_NOC_CNOC 23 +#define SA8775P_MASTER_GEM_NOC_PCIE_SNOC 24 +#define SA8775P_MASTER_GPDSP_SAIL 25 +#define SA8775P_MASTER_GFX3D 26 +#define SA8775P_MASTER_LPASS_ANOC 27 +#define SA8775P_MASTER_MDP0 28 +#define SA8775P_MASTER_MDP1 29 +#define SA8775P_MASTER_MDP_CORE1_0 30 +#define SA8775P_MASTER_MDP_CORE1_1 31 +#define SA8775P_MASTER_MNOC_HF_MEM_NOC 32 +#define SA8775P_MASTER_CNOC_MNOC_HF_CFG 33 +#define SA8775P_MASTER_MNOC_SF_MEM_NOC 34 +#define SA8775P_MASTER_CNOC_MNOC_SF_CFG 35 +#define SA8775P_MASTER_ANOC_PCIE_GEM_NOC 36 +#define SA8775P_MASTER_SNOC_CFG 37 +#define SA8775P_MASTER_SNOC_GC_MEM_NOC 38 +#define SA8775P_MASTER_SNOC_SF_MEM_NOC 39 +#define SA8775P_MASTER_VIDEO_P0 40 +#define SA8775P_MASTER_VIDEO_P1 41 +#define SA8775P_MASTER_VIDEO_PROC 42 +#define SA8775P_MASTER_VIDEO_V_PROC 43 +#define SA8775P_MASTER_QUP_CORE_0 44 +#define SA8775P_MASTER_QUP_CORE_1 45 +#define SA8775P_MASTER_QUP_CORE_2 46 +#define SA8775P_MASTER_QUP_CORE_3 47 +#define SA8775P_MASTER_CRYPTO_CORE0 48 +#define SA8775P_MASTER_CRYPTO_CORE1 49 +#define SA8775P_MASTER_DSP0 50 +#define SA8775P_MASTER_DSP1 51 +#define SA8775P_MASTER_IPA 52 +#define SA8775P_MASTER_LPASS_PROC 53 +#define SA8775P_MASTER_CDSP_PROC 54 +#define SA8775P_MASTER_CDSP_PROC_B 55 +#define SA8775P_MASTER_PIMEM 56 +#define SA8775P_MASTER_QUP_3 57 +#define SA8775P_MASTER_EMAC 58 +#define SA8775P_MASTER_EMAC_1 59 +#define SA8775P_MASTER_GIC 60 +#define SA8775P_MASTER_PCIE_0 61 +#define SA8775P_MASTER_PCIE_1 62 +#define SA8775P_MASTER_QDSS_ETR_0 63 +#define SA8775P_MASTER_QDSS_ETR_1 64 +#define SA8775P_MASTER_SDC 65 +#define SA8775P_MASTER_UFS_CARD 66 +#define SA8775P_MASTER_UFS_MEM 67 +#define SA8775P_MASTER_USB2 68 +#define SA8775P_MASTER_USB3_0 69 +#define SA8775P_MASTER_USB3_1 70 +#define SA8775P_SLAVE_EBI1 512 +#define SA8775P_SLAVE_AHB2PHY_0 513 +#define SA8775P_SLAVE_AHB2PHY_1 514 +#define SA8775P_SLAVE_AHB2PHY_2 515 +#define SA8775P_SLAVE_AHB2PHY_3 516 +#define SA8775P_SLAVE_ANOC_THROTTLE_CFG 517 +#define SA8775P_SLAVE_AOSS 518 +#define SA8775P_SLAVE_APPSS 519 +#define SA8775P_SLAVE_BOOT_ROM 520 +#define SA8775P_SLAVE_CAMERA_CFG 521 +#define SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG 522 +#define SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG 523 +#define SA8775P_SLAVE_CLK_CTL 524 +#define SA8775P_SLAVE_CDSP_CFG 525 +#define SA8775P_SLAVE_CDSP1_CFG 526 +#define SA8775P_SLAVE_RBCPR_CX_CFG 527 +#define SA8775P_SLAVE_RBCPR_MMCX_CFG 528 +#define SA8775P_SLAVE_RBCPR_MX_CFG 529 +#define SA8775P_SLAVE_CPR_NSPCX 530 +#define SA8775P_SLAVE_CRYPTO_0_CFG 531 +#define SA8775P_SLAVE_CX_RDPM 532 +#define SA8775P_SLAVE_DISPLAY_CFG 533 +#define SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG 534 +#define SA8775P_SLAVE_DISPLAY1_CFG 535 +#define SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG 536 +#define SA8775P_SLAVE_EMAC_CFG 537 +#define SA8775P_SLAVE_EMAC1_CFG 538 +#define SA8775P_SLAVE_GP_DSP0_CFG 539 +#define SA8775P_SLAVE_GP_DSP1_CFG 540 +#define SA8775P_SLAVE_GPDSP0_THROTTLE_CFG 541 +#define SA8775P_SLAVE_GPDSP1_THROTTLE_CFG 542 +#define SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG 543 +#define SA8775P_SLAVE_GFX3D_CFG 544 +#define SA8775P_SLAVE_HWKM 545 +#define SA8775P_SLAVE_IMEM_CFG 546 +#define SA8775P_SLAVE_IPA_CFG 547 +#define SA8775P_SLAVE_IPC_ROUTER_CFG 548 +#define SA8775P_SLAVE_LLCC_CFG 549 +#define SA8775P_SLAVE_LPASS 550 +#define SA8775P_SLAVE_LPASS_CORE_CFG 551 +#define SA8775P_SLAVE_LPASS_LPI_CFG 552 +#define SA8775P_SLAVE_LPASS_MPU_CFG 553 +#define SA8775P_SLAVE_LPASS_THROTTLE_CFG 554 +#define SA8775P_SLAVE_LPASS_TOP_CFG 555 +#define SA8775P_SLAVE_MX_RDPM 556 +#define SA8775P_SLAVE_MXC_RDPM 557 +#define SA8775P_SLAVE_PCIE_0_CFG 558 +#define SA8775P_SLAVE_PCIE_1_CFG 559 +#define SA8775P_SLAVE_PCIE_RSC_CFG 560 +#define SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG 561 +#define SA8775P_SLAVE_PCIE_THROTTLE_CFG 562 +#define SA8775P_SLAVE_PDM 563 +#define SA8775P_SLAVE_PIMEM_CFG 564 +#define SA8775P_SLAVE_PKA_WRAPPER_CFG 565 +#define SA8775P_SLAVE_QDSS_CFG 566 +#define SA8775P_SLAVE_QM_CFG 567 +#define SA8775P_SLAVE_QM_MPU_CFG 568 +#define SA8775P_SLAVE_QUP_0 569 +#define SA8775P_SLAVE_QUP_1 570 +#define SA8775P_SLAVE_QUP_2 571 +#define SA8775P_SLAVE_QUP_3 572 +#define SA8775P_SLAVE_SAIL_THROTTLE_CFG 573 +#define SA8775P_SLAVE_SDC1 574 +#define SA8775P_SLAVE_SECURITY 575 +#define SA8775P_SLAVE_SNOC_THROTTLE_CFG 576 +#define SA8775P_SLAVE_TCSR 577 +#define SA8775P_SLAVE_TLMM 578 +#define SA8775P_SLAVE_TSC_CFG 579 +#define SA8775P_SLAVE_UFS_CARD_CFG 580 +#define SA8775P_SLAVE_UFS_MEM_CFG 581 +#define SA8775P_SLAVE_USB2 582 +#define SA8775P_SLAVE_USB3_0 583 +#define SA8775P_SLAVE_USB3_1 584 +#define SA8775P_SLAVE_VENUS_CFG 585 +#define SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG 586 +#define SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG 587 +#define SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG 588 +#define SA8775P_SLAVE_A1NOC_SNOC 589 +#define SA8775P_SLAVE_A2NOC_SNOC 590 +#define SA8775P_SLAVE_DDRSS_CFG 591 +#define SA8775P_SLAVE_GEM_NOC_CNOC 592 +#define SA8775P_SLAVE_GEM_NOC_CFG 593 +#define SA8775P_SLAVE_SNOC_GEM_NOC_GC 594 +#define SA8775P_SLAVE_SNOC_GEM_NOC_SF 595 +#define SA8775P_SLAVE_GP_DSP_SAIL_NOC 596 +#define SA8775P_SLAVE_GPDSP_NOC_CFG 597 +#define SA8775P_SLAVE_HCP_A 598 +#define SA8775P_SLAVE_LLCC 599 +#define SA8775P_SLAVE_MNOC_HF_MEM_NOC 600 +#define SA8775P_SLAVE_MNOC_SF_MEM_NOC 601 +#define SA8775P_SLAVE_CNOC_MNOC_HF_CFG 602 +#define SA8775P_SLAVE_CNOC_MNOC_SF_CFG 603 +#define SA8775P_SLAVE_CDSP_MEM_NOC 604 +#define SA8775P_SLAVE_CDSPB_MEM_NOC 605 +#define SA8775P_SLAVE_HCP_B 606 +#define SA8775P_SLAVE_GEM_NOC_PCIE_CNOC 607 +#define SA8775P_SLAVE_PCIE_ANOC_CFG 608 +#define SA8775P_SLAVE_ANOC_PCIE_GEM_NOC 609 +#define SA8775P_SLAVE_SNOC_CFG 610 +#define SA8775P_SLAVE_LPASS_SNOC 611 +#define SA8775P_SLAVE_QUP_CORE_0 612 +#define SA8775P_SLAVE_QUP_CORE_1 613 +#define SA8775P_SLAVE_QUP_CORE_2 614 +#define SA8775P_SLAVE_QUP_CORE_3 615 +#define SA8775P_SLAVE_BOOT_IMEM 616 +#define SA8775P_SLAVE_IMEM 617 +#define SA8775P_SLAVE_PIMEM 618 +#define SA8775P_SLAVE_SERVICE_NSP_NOC 619 +#define SA8775P_SLAVE_SERVICE_NSPB_NOC 620 +#define SA8775P_SLAVE_SERVICE_GEM_NOC_1 621 +#define SA8775P_SLAVE_SERVICE_MNOC_HF 622 +#define SA8775P_SLAVE_SERVICE_MNOC_SF 623 +#define SA8775P_SLAVE_SERVICES_LPASS_AML_NOC 624 +#define SA8775P_SLAVE_SERVICE_LPASS_AG_NOC 625 +#define SA8775P_SLAVE_SERVICE_GEM_NOC_2 626 +#define SA8775P_SLAVE_SERVICE_SNOC 627 +#define SA8775P_SLAVE_SERVICE_GEM_NOC 628 +#define SA8775P_SLAVE_SERVICE_GEM_NOC2 629 +#define SA8775P_SLAVE_PCIE_0 630 +#define SA8775P_SLAVE_PCIE_1 631 +#define SA8775P_SLAVE_QDSS_STM 632 +#define SA8775P_SLAVE_TCU 633 + +static struct qcom_icc_node qxm_qup3 =3D { + .name =3D "qxm_qup3", + .id =3D SA8775P_MASTER_QUP_3, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_emac_0 =3D { + .name =3D "xm_emac_0", + .id =3D SA8775P_MASTER_EMAC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_emac_1 =3D { + .name =3D "xm_emac_1", + .id =3D SA8775P_MASTER_EMAC_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc1 =3D { + .name =3D "xm_sdc1", + .id =3D SA8775P_MASTER_SDC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .id =3D SA8775P_MASTER_UFS_MEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb2_2 =3D { + .name =3D "xm_usb2_2", + .id =3D SA8775P_MASTER_USB2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .id =3D SA8775P_MASTER_USB3_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_1 =3D { + .name =3D "xm_usb3_1", + .id =3D SA8775P_MASTER_USB3_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SA8775P_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .id =3D SA8775P_MASTER_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .id =3D SA8775P_MASTER_QUP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 =3D { + .name =3D "qhm_qup2", + .id =3D SA8775P_MASTER_QUP_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_cnoc_datapath =3D { + .name =3D "qnm_cnoc_datapath", + .id =3D SA8775P_MASTER_CNOC_A2NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto_0 =3D { + .name =3D "qxm_crypto_0", + .id =3D SA8775P_MASTER_CRYPTO_CORE0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto_1 =3D { + .name =3D "qxm_crypto_1", + .id =3D SA8775P_MASTER_CRYPTO_CORE1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .id =3D SA8775P_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 =3D { + .name =3D "xm_qdss_etr_0", + .id =3D SA8775P_MASTER_QDSS_ETR_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 =3D { + .name =3D "xm_qdss_etr_1", + .id =3D SA8775P_MASTER_QDSS_ETR_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_card =3D { + .name =3D "xm_ufs_card", + .id =3D SA8775P_MASTER_UFS_CARD, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qup0_core_master =3D { + .name =3D "qup0_core_master", + .id =3D SA8775P_MASTER_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master =3D { + .name =3D "qup1_core_master", + .id =3D SA8775P_MASTER_QUP_CORE_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qup2_core_master =3D { + .name =3D "qup2_core_master", + .id =3D SA8775P_MASTER_QUP_CORE_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_QUP_CORE_2 }, +}; + +static struct qcom_icc_node qup3_core_master =3D { + .name =3D "qup3_core_master", + .id =3D SA8775P_MASTER_QUP_CORE_3, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_QUP_CORE_3 }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc =3D { + .name =3D "qnm_gemnoc_cnoc", + .id =3D SA8775P_MASTER_GEM_NOC_CNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 82, + .links =3D { SA8775P_SLAVE_AHB2PHY_0, + SA8775P_SLAVE_AHB2PHY_1, + SA8775P_SLAVE_AHB2PHY_2, + SA8775P_SLAVE_AHB2PHY_3, + SA8775P_SLAVE_ANOC_THROTTLE_CFG, + SA8775P_SLAVE_AOSS, + SA8775P_SLAVE_APPSS, + SA8775P_SLAVE_BOOT_ROM, + SA8775P_SLAVE_CAMERA_CFG, + SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG, + SA8775P_SLAVE_CLK_CTL, + SA8775P_SLAVE_CDSP_CFG, + SA8775P_SLAVE_CDSP1_CFG, + SA8775P_SLAVE_RBCPR_CX_CFG, + SA8775P_SLAVE_RBCPR_MMCX_CFG, + SA8775P_SLAVE_RBCPR_MX_CFG, + SA8775P_SLAVE_CPR_NSPCX, + SA8775P_SLAVE_CRYPTO_0_CFG, + SA8775P_SLAVE_CX_RDPM, + SA8775P_SLAVE_DISPLAY_CFG, + SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG, + SA8775P_SLAVE_DISPLAY1_CFG, + SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG, + SA8775P_SLAVE_EMAC_CFG, + SA8775P_SLAVE_EMAC1_CFG, + SA8775P_SLAVE_GP_DSP0_CFG, + SA8775P_SLAVE_GP_DSP1_CFG, + SA8775P_SLAVE_GPDSP0_THROTTLE_CFG, + SA8775P_SLAVE_GPDSP1_THROTTLE_CFG, + SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG, + SA8775P_SLAVE_GFX3D_CFG, + SA8775P_SLAVE_HWKM, + SA8775P_SLAVE_IMEM_CFG, + SA8775P_SLAVE_IPA_CFG, + SA8775P_SLAVE_IPC_ROUTER_CFG, + SA8775P_SLAVE_LPASS, + SA8775P_SLAVE_LPASS_THROTTLE_CFG, + SA8775P_SLAVE_MX_RDPM, + SA8775P_SLAVE_MXC_RDPM, + SA8775P_SLAVE_PCIE_0_CFG, + SA8775P_SLAVE_PCIE_1_CFG, + SA8775P_SLAVE_PCIE_RSC_CFG, + SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG, + SA8775P_SLAVE_PCIE_THROTTLE_CFG, + SA8775P_SLAVE_PDM, + SA8775P_SLAVE_PIMEM_CFG, + SA8775P_SLAVE_PKA_WRAPPER_CFG, + SA8775P_SLAVE_QDSS_CFG, + SA8775P_SLAVE_QM_CFG, + SA8775P_SLAVE_QM_MPU_CFG, + SA8775P_SLAVE_QUP_0, + SA8775P_SLAVE_QUP_1, + SA8775P_SLAVE_QUP_2, + SA8775P_SLAVE_QUP_3, + SA8775P_SLAVE_SAIL_THROTTLE_CFG, + SA8775P_SLAVE_SDC1, + SA8775P_SLAVE_SECURITY, + SA8775P_SLAVE_SNOC_THROTTLE_CFG, + SA8775P_SLAVE_TCSR, + SA8775P_SLAVE_TLMM, + SA8775P_SLAVE_TSC_CFG, + SA8775P_SLAVE_UFS_CARD_CFG, + SA8775P_SLAVE_UFS_MEM_CFG, + SA8775P_SLAVE_USB2, + SA8775P_SLAVE_USB3_0, + SA8775P_SLAVE_USB3_1, + SA8775P_SLAVE_VENUS_CFG, + SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG, + SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG, + SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG, + SA8775P_SLAVE_DDRSS_CFG, + SA8775P_SLAVE_GPDSP_NOC_CFG, + SA8775P_SLAVE_CNOC_MNOC_HF_CFG, + SA8775P_SLAVE_CNOC_MNOC_SF_CFG, + SA8775P_SLAVE_PCIE_ANOC_CFG, + SA8775P_SLAVE_SNOC_CFG, + SA8775P_SLAVE_BOOT_IMEM, + SA8775P_SLAVE_IMEM, + SA8775P_SLAVE_PIMEM, + SA8775P_SLAVE_QDSS_STM, + SA8775P_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie =3D { + .name =3D "qnm_gemnoc_pcie", + .id =3D SA8775P_MASTER_GEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 2, + .links =3D { SA8775P_SLAVE_PCIE_0, + SA8775P_SLAVE_PCIE_1 + }, +}; + +static struct qcom_icc_node qnm_cnoc_dc_noc =3D { + .name =3D "qnm_cnoc_dc_noc", + .id =3D SA8775P_MASTER_CNOC_DC_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SA8775P_SLAVE_LLCC_CFG, + SA8775P_SLAVE_GEM_NOC_CFG + }, +}; + +static struct qcom_icc_node alm_gpu_tcu =3D { + .name =3D "alm_gpu_tcu", + .id =3D SA8775P_MASTER_GPU_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node alm_pcie_tcu =3D { + .name =3D "alm_pcie_tcu", + .id =3D SA8775P_MASTER_PCIE_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node alm_sys_tcu =3D { + .name =3D "alm_sys_tcu", + .id =3D SA8775P_MASTER_SYS_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node chm_apps =3D { + .name =3D "chm_apps", + .id =3D SA8775P_MASTER_APPSS_PROC, + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC, + SA8775P_SLAVE_GEM_NOC_PCIE_CNOC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc0 =3D { + .name =3D "qnm_cmpnoc0", + .id =3D SA8775P_MASTER_COMPUTE_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc1 =3D { + .name =3D "qnm_cmpnoc1", + .id =3D SA8775P_MASTER_COMPUTE_NOC_1, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_gemnoc_cfg =3D { + .name =3D "qnm_gemnoc_cfg", + .id =3D SA8775P_MASTER_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 4, + .links =3D { SA8775P_SLAVE_SERVICE_GEM_NOC_1, + SA8775P_SLAVE_SERVICE_GEM_NOC_2, + SA8775P_SLAVE_SERVICE_GEM_NOC, + SA8775P_SLAVE_SERVICE_GEM_NOC2 + }, +}; + +static struct qcom_icc_node qnm_gpdsp_sail =3D { + .name =3D "qnm_gpdsp_sail", + .id =3D SA8775P_MASTER_GPDSP_SAIL, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 2, + .links =3D { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .name =3D "qnm_gpu", + .id =3D SA8775P_MASTER_GFX3D, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .id =3D SA8775P_MASTER_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SA8775P_SLAVE_LLCC, + SA8775P_SLAVE_GEM_NOC_PCIE_CNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .id =3D SA8775P_MASTER_MNOC_SF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC, + SA8775P_SLAVE_GEM_NOC_PCIE_CNOC + }, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .name =3D "qnm_pcie", + .id =3D SA8775P_MASTER_ANOC_PCIE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SA8775P_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .id =3D SA8775P_MASTER_SNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .links =3D { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC, + SA8775P_SLAVE_GEM_NOC_PCIE_CNOC }, +}; + +static struct qcom_icc_node qxm_dsp0 =3D { + .name =3D "qxm_dsp0", + .id =3D SA8775P_MASTER_DSP0, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_GP_DSP_SAIL_NOC }, +}; + +static struct qcom_icc_node qxm_dsp1 =3D { + .name =3D "qxm_dsp1", + .id =3D SA8775P_MASTER_DSP1, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_GP_DSP_SAIL_NOC }, +}; + +static struct qcom_icc_node qhm_config_noc =3D { + .name =3D "qhm_config_noc", + .id =3D SA8775P_MASTER_CNOC_LPASS_AG_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 6, + .links =3D { SA8775P_SLAVE_LPASS_CORE_CFG, + SA8775P_SLAVE_LPASS_LPI_CFG, + SA8775P_SLAVE_LPASS_MPU_CFG, + SA8775P_SLAVE_LPASS_TOP_CFG, + SA8775P_SLAVE_SERVICES_LPASS_AML_NOC, + SA8775P_SLAVE_SERVICE_LPASS_AG_NOC + }, +}; + +static struct qcom_icc_node qxm_lpass_dsp =3D { + .name =3D "qxm_lpass_dsp", + .id =3D SA8775P_MASTER_LPASS_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 4, + .links =3D { SA8775P_SLAVE_LPASS_TOP_CFG, + SA8775P_SLAVE_LPASS_SNOC, + SA8775P_SLAVE_SERVICES_LPASS_AML_NOC, + SA8775P_SLAVE_SERVICE_LPASS_AG_NOC + }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SA8775P_MASTER_LLCC, + .channels =3D 8, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node qnm_camnoc_hf =3D { + .name =3D "qnm_camnoc_hf", + .id =3D SA8775P_MASTER_CAMNOC_HF, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_icp =3D { + .name =3D "qnm_camnoc_icp", + .id =3D SA8775P_MASTER_CAMNOC_ICP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_sf =3D { + .name =3D "qnm_camnoc_sf", + .id =3D SA8775P_MASTER_CAMNOC_SF, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp0_0 =3D { + .name =3D "qnm_mdp0_0", + .id =3D SA8775P_MASTER_MDP0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp0_1 =3D { + .name =3D "qnm_mdp0_1", + .id =3D SA8775P_MASTER_MDP1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp1_0 =3D { + .name =3D "qnm_mdp1_0", + .id =3D SA8775P_MASTER_MDP_CORE1_0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp1_1 =3D { + .name =3D "qnm_mdp1_1", + .id =3D SA8775P_MASTER_MDP_CORE1_1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf_cfg =3D { + .name =3D "qnm_mnoc_hf_cfg", + .id =3D SA8775P_MASTER_CNOC_MNOC_HF_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_SERVICE_MNOC_HF }, +}; + +static struct qcom_icc_node qnm_mnoc_sf_cfg =3D { + .name =3D "qnm_mnoc_sf_cfg", + .id =3D SA8775P_MASTER_CNOC_MNOC_SF_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_SERVICE_MNOC_SF }, +}; + +static struct qcom_icc_node qnm_video0 =3D { + .name =3D "qnm_video0", + .id =3D SA8775P_MASTER_VIDEO_P0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video1 =3D { + .name =3D "qnm_video1", + .id =3D SA8775P_MASTER_VIDEO_P1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp =3D { + .name =3D "qnm_video_cvp", + .id =3D SA8775P_MASTER_VIDEO_PROC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_v_cpu =3D { + .name =3D "qnm_video_v_cpu", + .id =3D SA8775P_MASTER_VIDEO_V_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_nsp_noc_config =3D { + .name =3D "qhm_nsp_noc_config", + .id =3D SA8775P_MASTER_CDSP_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_SERVICE_NSP_NOC }, +}; + +static struct qcom_icc_node qxm_nsp =3D { + .name =3D "qxm_nsp", + .id =3D SA8775P_MASTER_CDSP_PROC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SA8775P_SLAVE_HCP_A, SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_nspb_noc_config =3D { + .name =3D "qhm_nspb_noc_config", + .id =3D SA8775P_MASTER_CDSPB_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_SERVICE_NSPB_NOC }, +}; + +static struct qcom_icc_node qxm_nspb =3D { + .name =3D "qxm_nspb", + .id =3D SA8775P_MASTER_CDSP_PROC_B, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SA8775P_SLAVE_HCP_B, SLAVE_CDSPB_MEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_0 =3D { + .name =3D "xm_pcie3_0", + .id =3D SA8775P_MASTER_PCIE_0, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 =3D { + .name =3D "xm_pcie3_1", + .id =3D SA8775P_MASTER_PCIE_1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node qhm_gic =3D { + .name =3D "qhm_gic", + .id =3D SA8775P_MASTER_GIC_AHB, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .id =3D SA8775P_MASTER_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .id =3D SA8775P_MASTER_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_lpass_noc =3D { + .name =3D "qnm_lpass_noc", + .id =3D SA8775P_MASTER_LPASS_ANOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_snoc_cfg =3D { + .name =3D "qnm_snoc_cfg", + .id =3D SA8775P_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .id =3D SA8775P_MASTER_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .id =3D SA8775P_MASTER_GIC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .id =3D SA8775P_SLAVE_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .id =3D SA8775P_SLAVE_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qup0_core_slave =3D { + .name =3D "qup0_core_slave", + .id =3D SA8775P_SLAVE_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup1_core_slave =3D { + .name =3D "qup1_core_slave", + .id =3D SA8775P_SLAVE_QUP_CORE_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup2_core_slave =3D { + .name =3D "qup2_core_slave", + .id =3D SA8775P_SLAVE_QUP_CORE_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup3_core_slave =3D { + .name =3D "qup3_core_slave", + .id =3D SA8775P_SLAVE_QUP_CORE_3, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .id =3D SA8775P_SLAVE_AHB2PHY_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 =3D { + .name =3D "qhs_ahb2phy1", + .id =3D SA8775P_SLAVE_AHB2PHY_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 =3D { + .name =3D "qhs_ahb2phy2", + .id =3D SA8775P_SLAVE_AHB2PHY_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy3 =3D { + .name =3D "qhs_ahb2phy3", + .id =3D SA8775P_SLAVE_AHB2PHY_3, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_anoc_throttle_cfg =3D { + .name =3D "qhs_anoc_throttle_cfg", + .id =3D SA8775P_SLAVE_ANOC_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SA8775P_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SA8775P_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_boot_rom =3D { + .name =3D "qhs_boot_rom", + .id =3D SA8775P_SLAVE_BOOT_ROM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .id =3D SA8775P_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg =3D { + .name =3D "qhs_camera_nrt_throttle_cfg", + .id =3D SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_rt_throttle_cfg =3D { + .name =3D "qhs_camera_rt_throttle_cfg", + .id =3D SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SA8775P_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_compute0_cfg =3D { + .name =3D "qhs_compute0_cfg", + .id =3D SA8775P_SLAVE_CDSP_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_CDSP_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_compute1_cfg =3D { + .name =3D "qhs_compute1_cfg", + .id =3D SA8775P_SLAVE_CDSP1_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_CDSPB_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .id =3D SA8775P_SLAVE_RBCPR_CX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx =3D { + .name =3D "qhs_cpr_mmcx", + .id =3D SA8775P_SLAVE_RBCPR_MMCX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mx =3D { + .name =3D "qhs_cpr_mx", + .id =3D SA8775P_SLAVE_RBCPR_MX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_nspcx =3D { + .name =3D "qhs_cpr_nspcx", + .id =3D SA8775P_SLAVE_CPR_NSPCX, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SA8775P_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cx_rdpm =3D { + .name =3D "qhs_cx_rdpm", + .id =3D SA8775P_SLAVE_CX_RDPM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display0_cfg =3D { + .name =3D "qhs_display0_cfg", + .id =3D SA8775P_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display0_rt_throttle_cfg =3D { + .name =3D "qhs_display0_rt_throttle_cfg", + .id =3D SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display1_cfg =3D { + .name =3D "qhs_display1_cfg", + .id =3D SA8775P_SLAVE_DISPLAY1_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display1_rt_throttle_cfg =3D { + .name =3D "qhs_display1_rt_throttle_cfg", + .id =3D SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_emac0_cfg =3D { + .name =3D "qhs_emac0_cfg", + .id =3D SA8775P_SLAVE_EMAC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_emac1_cfg =3D { + .name =3D "qhs_emac1_cfg", + .id =3D SA8775P_SLAVE_EMAC1_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gp_dsp0_cfg =3D { + .name =3D "qhs_gp_dsp0_cfg", + .id =3D SA8775P_SLAVE_GP_DSP0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gp_dsp1_cfg =3D { + .name =3D "qhs_gp_dsp1_cfg", + .id =3D SA8775P_SLAVE_GP_DSP1_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpdsp0_throttle_cfg =3D { + .name =3D "qhs_gpdsp0_throttle_cfg", + .id =3D SA8775P_SLAVE_GPDSP0_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpdsp1_throttle_cfg =3D { + .name =3D "qhs_gpdsp1_throttle_cfg", + .id =3D SA8775P_SLAVE_GPDSP1_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg =3D { + .name =3D "qhs_gpu_tcu_throttle_cfg", + .id =3D SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .id =3D SA8775P_SLAVE_GFX3D_CFG, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_hwkm =3D { + .name =3D "qhs_hwkm", + .id =3D SA8775P_SLAVE_HWKM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SA8775P_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SA8775P_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipc_router =3D { + .name =3D "qhs_ipc_router", + .id =3D SA8775P_SLAVE_IPC_ROUTER_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_lpass_cfg =3D { + .name =3D "qhs_lpass_cfg", + .id =3D SA8775P_SLAVE_LPASS, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_CNOC_LPASS_AG_NOC }, +}; + +static struct qcom_icc_node qhs_lpass_throttle_cfg =3D { + .name =3D "qhs_lpass_throttle_cfg", + .id =3D SA8775P_SLAVE_LPASS_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mx_rdpm =3D { + .name =3D "qhs_mx_rdpm", + .id =3D SA8775P_SLAVE_MX_RDPM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mxc_rdpm =3D { + .name =3D "qhs_mxc_rdpm", + .id =3D SA8775P_SLAVE_MXC_RDPM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg =3D { + .name =3D "qhs_pcie0_cfg", + .id =3D SA8775P_SLAVE_PCIE_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg =3D { + .name =3D "qhs_pcie1_cfg", + .id =3D SA8775P_SLAVE_PCIE_1_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_rsc_cfg =3D { + .name =3D "qhs_pcie_rsc_cfg", + .id =3D SA8775P_SLAVE_PCIE_RSC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg =3D { + .name =3D "qhs_pcie_tcu_throttle_cfg", + .id =3D SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_throttle_cfg =3D { + .name =3D "qhs_pcie_throttle_cfg", + .id =3D SA8775P_SLAVE_PCIE_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D SA8775P_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg =3D { + .name =3D "qhs_pimem_cfg", + .id =3D SA8775P_SLAVE_PIMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pke_wrapper_cfg =3D { + .name =3D "qhs_pke_wrapper_cfg", + .id =3D SA8775P_SLAVE_PKA_WRAPPER_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SA8775P_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qm_cfg =3D { + .name =3D "qhs_qm_cfg", + .id =3D SA8775P_SLAVE_QM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qm_mpu_cfg =3D { + .name =3D "qhs_qm_mpu_cfg", + .id =3D SA8775P_SLAVE_QM_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .id =3D SA8775P_SLAVE_QUP_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .id =3D SA8775P_SLAVE_QUP_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup2 =3D { + .name =3D "qhs_qup2", + .id =3D SA8775P_SLAVE_QUP_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup3 =3D { + .name =3D "qhs_qup3", + .id =3D SA8775P_SLAVE_QUP_3, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sail_throttle_cfg =3D { + .name =3D "qhs_sail_throttle_cfg", + .id =3D SA8775P_SLAVE_SAIL_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc1 =3D { + .name =3D "qhs_sdc1", + .id =3D SA8775P_SLAVE_SDC1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_security =3D { + .name =3D "qhs_security", + .id =3D SA8775P_SLAVE_SECURITY, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_snoc_throttle_cfg =3D { + .name =3D "qhs_snoc_throttle_cfg", + .id =3D SA8775P_SLAVE_SNOC_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SA8775P_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .id =3D SA8775P_SLAVE_TLMM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tsc_cfg =3D { + .name =3D "qhs_tsc_cfg", + .id =3D SA8775P_SLAVE_TSC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg =3D { + .name =3D "qhs_ufs_card_cfg", + .id =3D SA8775P_SLAVE_UFS_CARD_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .id =3D SA8775P_SLAVE_UFS_MEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb2_0 =3D { + .name =3D "qhs_usb2_0", + .id =3D SA8775P_SLAVE_USB2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .id =3D SA8775P_SLAVE_USB3_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_1 =3D { + .name =3D "qhs_usb3_1", + .id =3D SA8775P_SLAVE_USB3_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D SA8775P_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cvp_throttle_cfg =3D { + .name =3D "qhs_venus_cvp_throttle_cfg", + .id =3D SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg =3D { + .name =3D "qhs_venus_v_cpu_throttle_cfg", + .id =3D SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg =3D { + .name =3D "qhs_venus_vcodec_throttle_cfg", + .id =3D SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_ddrss_cfg =3D { + .name =3D "qns_ddrss_cfg", + .id =3D SA8775P_SLAVE_DDRSS_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qns_gpdsp_noc_cfg =3D { + .name =3D "qns_gpdsp_noc_cfg", + .id =3D SA8775P_SLAVE_GPDSP_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_mnoc_hf_cfg =3D { + .name =3D "qns_mnoc_hf_cfg", + .id =3D SA8775P_SLAVE_CNOC_MNOC_HF_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_CNOC_MNOC_HF_CFG }, +}; + +static struct qcom_icc_node qns_mnoc_sf_cfg =3D { + .name =3D "qns_mnoc_sf_cfg", + .id =3D SA8775P_SLAVE_CNOC_MNOC_SF_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_CNOC_MNOC_SF_CFG }, +}; + +static struct qcom_icc_node qns_pcie_anoc_cfg =3D { + .name =3D "qns_pcie_anoc_cfg", + .id =3D SA8775P_SLAVE_PCIE_ANOC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_snoc_cfg =3D { + .name =3D "qns_snoc_cfg", + .id =3D SA8775P_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qxs_boot_imem =3D { + .name =3D "qxs_boot_imem", + .id =3D SA8775P_SLAVE_BOOT_IMEM, + .channels =3D 1, + .buswidth =3D 16, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SA8775P_SLAVE_IMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .id =3D SA8775P_SLAVE_PIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .id =3D SA8775P_SLAVE_PCIE_0, + .channels =3D 1, + .buswidth =3D 16, +}; + +static struct qcom_icc_node xs_pcie_1 =3D { + .name =3D "xs_pcie_1", + .id =3D SA8775P_SLAVE_PCIE_1, + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SA8775P_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SA8775P_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_llcc =3D { + .name =3D "qhs_llcc", + .id =3D SA8775P_SLAVE_LLCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_gemnoc =3D { + .name =3D "qns_gemnoc", + .id =3D SA8775P_SLAVE_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc =3D { + .name =3D "qns_gem_noc_cnoc", + .id =3D SA8775P_SLAVE_GEM_NOC_CNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_GEM_NOC_CNOC }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SA8775P_SLAVE_LLCC, + .channels =3D 6, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_pcie =3D { + .name =3D "qns_pcie", + .id =3D SA8775P_SLAVE_GEM_NOC_PCIE_CNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_even_gemnoc =3D { + .name =3D "srvc_even_gemnoc", + .id =3D SA8775P_SLAVE_SERVICE_GEM_NOC_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_odd_gemnoc =3D { + .name =3D "srvc_odd_gemnoc", + .id =3D SA8775P_SLAVE_SERVICE_GEM_NOC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc =3D { + .name =3D "srvc_sys_gemnoc", + .id =3D SA8775P_SLAVE_SERVICE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc_2 =3D { + .name =3D "srvc_sys_gemnoc_2", + .id =3D SA8775P_SLAVE_SERVICE_GEM_NOC2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_gp_dsp_sail_noc =3D { + .name =3D "qns_gp_dsp_sail_noc", + .id =3D SA8775P_SLAVE_GP_DSP_SAIL_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_GPDSP_SAIL }, +}; + +static struct qcom_icc_node qhs_lpass_core =3D { + .name =3D "qhs_lpass_core", + .id =3D SA8775P_SLAVE_LPASS_CORE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_lpass_lpi =3D { + .name =3D "qhs_lpass_lpi", + .id =3D SA8775P_SLAVE_LPASS_LPI_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_lpass_mpu =3D { + .name =3D "qhs_lpass_mpu", + .id =3D SA8775P_SLAVE_LPASS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_lpass_top =3D { + .name =3D "qhs_lpass_top", + .id =3D SA8775P_SLAVE_LPASS_TOP_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_sysnoc =3D { + .name =3D "qns_sysnoc", + .id =3D SA8775P_SLAVE_LPASS_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_LPASS_ANOC }, +}; + +static struct qcom_icc_node srvc_niu_aml_noc =3D { + .name =3D "srvc_niu_aml_noc", + .id =3D SA8775P_SLAVE_SERVICES_LPASS_AML_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_niu_lpass_agnoc =3D { + .name =3D "srvc_niu_lpass_agnoc", + .id =3D SA8775P_SLAVE_SERVICE_LPASS_AG_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SA8775P_SLAVE_EBI1, + .channels =3D 8, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .id =3D SA8775P_SLAVE_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .id =3D SA8775P_SLAVE_MNOC_SF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc_hf =3D { + .name =3D "srvc_mnoc_hf", + .id =3D SA8775P_SLAVE_SERVICE_MNOC_HF, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_mnoc_sf =3D { + .name =3D "srvc_mnoc_sf", + .id =3D SA8775P_SLAVE_SERVICE_MNOC_SF, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_hcp =3D { + .name =3D "qns_hcp", + .id =3D SA8775P_SLAVE_HCP_A, + .channels =3D 2, + .buswidth =3D 32, +}; + +static struct qcom_icc_node qns_nsp_gemnoc =3D { + .name =3D "qns_nsp_gemnoc", + .id =3D SA8775P_SLAVE_CDSP_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node service_nsp_noc =3D { + .name =3D "service_nsp_noc", + .id =3D SA8775P_SLAVE_SERVICE_NSP_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_nspb_gemnoc =3D { + .name =3D "qns_nspb_gemnoc", + .id =3D SA8775P_SLAVE_CDSPB_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_COMPUTE_NOC_1 }, +}; + +static struct qcom_icc_node qns_nspb_hcp =3D { + .name =3D "qns_nspb_hcp", + .id =3D SA8775P_SLAVE_HCP_B, + .channels =3D 2, + .buswidth =3D 32, +}; + +static struct qcom_icc_node service_nspb_noc =3D { + .name =3D "service_nspb_noc", + .id =3D SA8775P_SLAVE_SERVICE_NSPB_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_pcie_mem_noc =3D { + .name =3D "qns_pcie_mem_noc", + .id =3D SA8775P_SLAVE_ANOC_PCIE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_gc =3D { + .name =3D "qns_gemnoc_gc", + .id =3D SA8775P_SLAVE_SNOC_GEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .id =3D SA8775P_SLAVE_SNOC_GEM_NOC_SF, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SA8775P_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SA8775P_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .num_nodes =3D 2, + .nodes =3D { &qxm_crypto_0, &qxm_crypto_1 }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .keepalive =3D true, + .num_nodes =3D 2, + .nodes =3D { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_cn1 =3D { + .name =3D "CN1", + .num_nodes =3D 76, + .nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_ahb2phy2, &qhs_ahb2phy3, + &qhs_anoc_throttle_cfg, &qhs_aoss, + &qhs_apss, &qhs_boot_rom, + &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, + &qhs_compute0_cfg, &qhs_compute1_cfg, + &qhs_cpr_cx, &qhs_cpr_mmcx, + &qhs_cpr_mx, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg, + &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg, + &qhs_emac0_cfg, &qhs_emac1_cfg, + &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg, + &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg, + &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg, + &qhs_hwkm, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_lpass_throttle_cfg, + &qhs_mx_rdpm, &qhs_mxc_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg, + &qhs_pcie_throttle_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_pke_wrapper_cfg, + &qhs_qdss_cfg, &qhs_qm_cfg, + &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg, + &qhs_sdc1, &qhs_security, + &qhs_snoc_throttle_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_tsc_cfg, + &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, + &qhs_usb2_0, &qhs_usb3_0, + &qhs_usb3_1, &qhs_venus_cfg, + &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg, + &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg, + &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg, + &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg, + &qns_snoc_cfg, &qxs_boot_imem, + &qxs_imem, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_cn2 =3D { + .name =3D "CN2", + .num_nodes =3D 4, + .nodes =3D { &qhs_qup0, &qhs_qup1, + &qhs_qup2, &qhs_qup3 }, +}; + +static struct qcom_icc_bcm bcm_cn3 =3D { + .name =3D "CN3", + .num_nodes =3D 2, + .nodes =3D { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_bcm bcm_gna0 =3D { + .name =3D "GNA0", + .num_nodes =3D 1, + .nodes =3D { &qxm_dsp0 }, +}; + +static struct qcom_icc_bcm bcm_gnb0 =3D { + .name =3D "GNB0", + .num_nodes =3D 1, + .nodes =3D { &qxm_dsp1 }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .keepalive =3D true, + .num_nodes =3D 5, + .nodes =3D { &qnm_camnoc_hf, &qnm_mdp0_0, + &qnm_mdp0_1, &qnm_mdp1_0, + &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .num_nodes =3D 7, + .nodes =3D { &qnm_camnoc_icp, &qnm_camnoc_sf, + &qnm_video0, &qnm_video1, + &qnm_video_cvp, &qnm_video_v_cpu, + &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_nsa0 =3D { + .name =3D "NSA0", + .num_nodes =3D 2, + .nodes =3D { &qns_hcp, &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_nsa1 =3D { + .name =3D "NSA1", + .num_nodes =3D 1, + .nodes =3D { &qxm_nsp }, +}; + +static struct qcom_icc_bcm bcm_nsb0 =3D { + .name =3D "NSB0", + .num_nodes =3D 2, + .nodes =3D { &qns_nspb_gemnoc, &qns_nspb_hcp }, +}; + +static struct qcom_icc_bcm bcm_nsb1 =3D { + .name =3D "NSB1", + .num_nodes =3D 1, + .nodes =3D { &qxm_nspb }, +}; + +static struct qcom_icc_bcm bcm_pci0 =3D { + .name =3D "PCI0", + .num_nodes =3D 1, + .nodes =3D { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 =3D { + .name =3D "QUP1", + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 =3D { + .name =3D "QUP2", + .vote_scale =3D 1, + .num_nodes =3D 2, + .nodes =3D { &qup2_core_slave, &qup3_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh2 =3D { + .name =3D "SH2", + .num_nodes =3D 1, + .nodes =3D { &chm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .num_nodes =3D 1, + .nodes =3D { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .num_nodes =3D 2, + .nodes =3D { &qns_a1noc_snoc, &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .num_nodes =3D 2, + .nodes =3D { &qns_a2noc_snoc, &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn9 =3D { + .name =3D "SN9", + .num_nodes =3D 2, + .nodes =3D { &qns_sysnoc, &qnm_lpass_noc }, +}; + +static struct qcom_icc_bcm bcm_sn10 =3D { + .name =3D "SN10", + .num_nodes =3D 1, + .nodes =3D { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm *aggre1_noc_bcms[] =3D { + &bcm_sn3, +}; + +static struct qcom_icc_node *aggre1_noc_nodes[] =3D { + [MASTER_QUP_3] =3D &qxm_qup3, + [MASTER_EMAC] =3D &xm_emac_0, + [MASTER_EMAC_1] =3D &xm_emac_1, + [MASTER_SDC] =3D &xm_sdc1, + [MASTER_UFS_MEM] =3D &xm_ufs_mem, + [MASTER_USB2] =3D &xm_usb2_2, + [MASTER_USB3_0] =3D &xm_usb3_0, + [MASTER_USB3_1] =3D &xm_usb3_1, + [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, +}; + +static const struct qcom_icc_desc sa8775p_aggre1_noc =3D { + .nodes =3D aggre1_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), + .bcms =3D aggre1_noc_bcms, + .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), +}; + +static struct qcom_icc_bcm *aggre2_noc_bcms[] =3D { + &bcm_ce0, + &bcm_sn4, +}; + +static struct qcom_icc_node *aggre2_noc_nodes[] =3D { + [MASTER_QDSS_BAM] =3D &qhm_qdss_bam, + [MASTER_QUP_0] =3D &qhm_qup0, + [MASTER_QUP_1] =3D &qhm_qup1, + [MASTER_QUP_2] =3D &qhm_qup2, + [MASTER_CNOC_A2NOC] =3D &qnm_cnoc_datapath, + [MASTER_CRYPTO_CORE0] =3D &qxm_crypto_0, + [MASTER_CRYPTO_CORE1] =3D &qxm_crypto_1, + [MASTER_IPA] =3D &qxm_ipa, + [MASTER_QDSS_ETR_0] =3D &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] =3D &xm_qdss_etr_1, + [MASTER_UFS_CARD] =3D &xm_ufs_card, + [SLAVE_A2NOC_SNOC] =3D &qns_a2noc_snoc, +}; + +static const struct qcom_icc_desc sa8775p_aggre2_noc =3D { + .nodes =3D aggre2_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), + .bcms =3D aggre2_noc_bcms, + .num_bcms =3D ARRAY_SIZE(aggre2_noc_bcms), +}; + +static struct qcom_icc_bcm *clk_virt_bcms[] =3D { + &bcm_qup0, + &bcm_qup1, + &bcm_qup2, +}; + +static struct qcom_icc_node *clk_virt_nodes[] =3D { + [MASTER_QUP_CORE_0] =3D &qup0_core_master, + [MASTER_QUP_CORE_1] =3D &qup1_core_master, + [MASTER_QUP_CORE_2] =3D &qup2_core_master, + [MASTER_QUP_CORE_3] =3D &qup3_core_master, + [SLAVE_QUP_CORE_0] =3D &qup0_core_slave, + [SLAVE_QUP_CORE_1] =3D &qup1_core_slave, + [SLAVE_QUP_CORE_2] =3D &qup2_core_slave, + [SLAVE_QUP_CORE_3] =3D &qup3_core_slave, +}; + +static const struct qcom_icc_desc sa8775p_clk_virt =3D { + .nodes =3D clk_virt_nodes, + .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), + .bcms =3D clk_virt_bcms, + .num_bcms =3D ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm *config_noc_bcms[] =3D { + &bcm_cn0, + &bcm_cn1, + &bcm_cn2, + &bcm_cn3, + &bcm_sn2, + &bcm_sn10, +}; + +static struct qcom_icc_node *config_noc_nodes[] =3D { + [MASTER_GEM_NOC_CNOC] =3D &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] =3D &qnm_gemnoc_pcie, + [SLAVE_AHB2PHY_0] =3D &qhs_ahb2phy0, + [SLAVE_AHB2PHY_1] =3D &qhs_ahb2phy1, + [SLAVE_AHB2PHY_2] =3D &qhs_ahb2phy2, + [SLAVE_AHB2PHY_3] =3D &qhs_ahb2phy3, + [SLAVE_ANOC_THROTTLE_CFG] =3D &qhs_anoc_throttle_cfg, + [SLAVE_AOSS] =3D &qhs_aoss, + [SLAVE_APPSS] =3D &qhs_apss, + [SLAVE_BOOT_ROM] =3D &qhs_boot_rom, + [SLAVE_CAMERA_CFG] =3D &qhs_camera_cfg, + [SLAVE_CAMERA_NRT_THROTTLE_CFG] =3D &qhs_camera_nrt_throttle_cfg, + [SLAVE_CAMERA_RT_THROTTLE_CFG] =3D &qhs_camera_rt_throttle_cfg, + [SLAVE_CLK_CTL] =3D &qhs_clk_ctl, + [SLAVE_CDSP_CFG] =3D &qhs_compute0_cfg, + [SLAVE_CDSP1_CFG] =3D &qhs_compute1_cfg, + [SLAVE_RBCPR_CX_CFG] =3D &qhs_cpr_cx, + [SLAVE_RBCPR_MMCX_CFG] =3D &qhs_cpr_mmcx, + [SLAVE_RBCPR_MX_CFG] =3D &qhs_cpr_mx, + [SLAVE_CPR_NSPCX] =3D &qhs_cpr_nspcx, + [SLAVE_CRYPTO_0_CFG] =3D &qhs_crypto0_cfg, + [SLAVE_CX_RDPM] =3D &qhs_cx_rdpm, + [SLAVE_DISPLAY_CFG] =3D &qhs_display0_cfg, + [SLAVE_DISPLAY_RT_THROTTLE_CFG] =3D &qhs_display0_rt_throttle_cfg, + [SLAVE_DISPLAY1_CFG] =3D &qhs_display1_cfg, + [SLAVE_DISPLAY1_RT_THROTTLE_CFG] =3D &qhs_display1_rt_throttle_cfg, + [SLAVE_EMAC_CFG] =3D &qhs_emac0_cfg, + [SLAVE_EMAC1_CFG] =3D &qhs_emac1_cfg, + [SLAVE_GP_DSP0_CFG] =3D &qhs_gp_dsp0_cfg, + [SLAVE_GP_DSP1_CFG] =3D &qhs_gp_dsp1_cfg, + [SLAVE_GPDSP0_THROTTLE_CFG] =3D &qhs_gpdsp0_throttle_cfg, + [SLAVE_GPDSP1_THROTTLE_CFG] =3D &qhs_gpdsp1_throttle_cfg, + [SLAVE_GPU_TCU_THROTTLE_CFG] =3D &qhs_gpu_tcu_throttle_cfg, + [SLAVE_GFX3D_CFG] =3D &qhs_gpuss_cfg, + [SLAVE_HWKM] =3D &qhs_hwkm, + [SLAVE_IMEM_CFG] =3D &qhs_imem_cfg, + [SLAVE_IPA_CFG] =3D &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] =3D &qhs_ipc_router, + [SLAVE_LPASS] =3D &qhs_lpass_cfg, + [SLAVE_LPASS_THROTTLE_CFG] =3D &qhs_lpass_throttle_cfg, + [SLAVE_MX_RDPM] =3D &qhs_mx_rdpm, + [SLAVE_MXC_RDPM] =3D &qhs_mxc_rdpm, + [SLAVE_PCIE_0_CFG] =3D &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] =3D &qhs_pcie1_cfg, + [SLAVE_PCIE_RSC_CFG] =3D &qhs_pcie_rsc_cfg, + [SLAVE_PCIE_TCU_THROTTLE_CFG] =3D &qhs_pcie_tcu_throttle_cfg, + [SLAVE_PCIE_THROTTLE_CFG] =3D &qhs_pcie_throttle_cfg, + [SLAVE_PDM] =3D &qhs_pdm, + [SLAVE_PIMEM_CFG] =3D &qhs_pimem_cfg, + [SLAVE_PKA_WRAPPER_CFG] =3D &qhs_pke_wrapper_cfg, + [SLAVE_QDSS_CFG] =3D &qhs_qdss_cfg, + [SLAVE_QM_CFG] =3D &qhs_qm_cfg, + [SLAVE_QM_MPU_CFG] =3D &qhs_qm_mpu_cfg, + [SLAVE_QUP_0] =3D &qhs_qup0, + [SLAVE_QUP_1] =3D &qhs_qup1, + [SLAVE_QUP_2] =3D &qhs_qup2, + [SLAVE_QUP_3] =3D &qhs_qup3, + [SLAVE_SAIL_THROTTLE_CFG] =3D &qhs_sail_throttle_cfg, + [SLAVE_SDC1] =3D &qhs_sdc1, + [SLAVE_SECURITY] =3D &qhs_security, + [SLAVE_SNOC_THROTTLE_CFG] =3D &qhs_snoc_throttle_cfg, + [SLAVE_TCSR] =3D &qhs_tcsr, + [SLAVE_TLMM] =3D &qhs_tlmm, + [SLAVE_TSC_CFG] =3D &qhs_tsc_cfg, + [SLAVE_UFS_CARD_CFG] =3D &qhs_ufs_card_cfg, + [SLAVE_UFS_MEM_CFG] =3D &qhs_ufs_mem_cfg, + [SLAVE_USB2] =3D &qhs_usb2_0, + [SLAVE_USB3_0] =3D &qhs_usb3_0, + [SLAVE_USB3_1] =3D &qhs_usb3_1, + [SLAVE_VENUS_CFG] =3D &qhs_venus_cfg, + [SLAVE_VENUS_CVP_THROTTLE_CFG] =3D &qhs_venus_cvp_throttle_cfg, + [SLAVE_VENUS_V_CPU_THROTTLE_CFG] =3D &qhs_venus_v_cpu_throttle_cfg, + [SLAVE_VENUS_VCODEC_THROTTLE_CFG] =3D &qhs_venus_vcodec_throttle_cfg, + [SLAVE_DDRSS_CFG] =3D &qns_ddrss_cfg, + [SLAVE_GPDSP_NOC_CFG] =3D &qns_gpdsp_noc_cfg, + [SLAVE_CNOC_MNOC_HF_CFG] =3D &qns_mnoc_hf_cfg, + [SLAVE_CNOC_MNOC_SF_CFG] =3D &qns_mnoc_sf_cfg, + [SLAVE_PCIE_ANOC_CFG] =3D &qns_pcie_anoc_cfg, + [SLAVE_SNOC_CFG] =3D &qns_snoc_cfg, + [SLAVE_BOOT_IMEM] =3D &qxs_boot_imem, + [SLAVE_IMEM] =3D &qxs_imem, + [SLAVE_PIMEM] =3D &qxs_pimem, + [SLAVE_PCIE_0] =3D &xs_pcie_0, + [SLAVE_PCIE_1] =3D &xs_pcie_1, + [SLAVE_QDSS_STM] =3D &xs_qdss_stm, + [SLAVE_TCU] =3D &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc sa8775p_config_noc =3D { + .nodes =3D config_noc_nodes, + .num_nodes =3D ARRAY_SIZE(config_noc_nodes), + .bcms =3D config_noc_bcms, + .num_bcms =3D ARRAY_SIZE(config_noc_bcms), +}; + +static struct qcom_icc_bcm *dc_noc_bcms[] =3D { +}; + +static struct qcom_icc_node *dc_noc_nodes[] =3D { + [MASTER_CNOC_DC_NOC] =3D &qnm_cnoc_dc_noc, + [SLAVE_LLCC_CFG] =3D &qhs_llcc, + [SLAVE_GEM_NOC_CFG] =3D &qns_gemnoc, +}; + +static const struct qcom_icc_desc sa8775p_dc_noc =3D { + .nodes =3D dc_noc_nodes, + .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), + .bcms =3D dc_noc_bcms, + .num_bcms =3D ARRAY_SIZE(dc_noc_bcms), +}; + +static struct qcom_icc_bcm *gem_noc_bcms[] =3D { + &bcm_sh0, + &bcm_sh2, +}; + +static struct qcom_icc_node *gem_noc_nodes[] =3D { + [MASTER_GPU_TCU] =3D &alm_gpu_tcu, + [MASTER_PCIE_TCU] =3D &alm_pcie_tcu, + [MASTER_SYS_TCU] =3D &alm_sys_tcu, + [MASTER_APPSS_PROC] =3D &chm_apps, + [MASTER_COMPUTE_NOC] =3D &qnm_cmpnoc0, + [MASTER_COMPUTE_NOC_1] =3D &qnm_cmpnoc1, + [MASTER_GEM_NOC_CFG] =3D &qnm_gemnoc_cfg, + [MASTER_GPDSP_SAIL] =3D &qnm_gpdsp_sail, + [MASTER_GFX3D] =3D &qnm_gpu, + [MASTER_MNOC_HF_MEM_NOC] =3D &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] =3D &qnm_mnoc_sf, + [MASTER_ANOC_PCIE_GEM_NOC] =3D &qnm_pcie, + [MASTER_SNOC_GC_MEM_NOC] =3D &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] =3D &qnm_snoc_sf, + [SLAVE_GEM_NOC_CNOC] =3D &qns_gem_noc_cnoc, + [SLAVE_LLCC] =3D &qns_llcc, + [SLAVE_GEM_NOC_PCIE_CNOC] =3D &qns_pcie, + [SLAVE_SERVICE_GEM_NOC_1] =3D &srvc_even_gemnoc, + [SLAVE_SERVICE_GEM_NOC_2] =3D &srvc_odd_gemnoc, + [SLAVE_SERVICE_GEM_NOC] =3D &srvc_sys_gemnoc, + [SLAVE_SERVICE_GEM_NOC2] =3D &srvc_sys_gemnoc_2, +}; + +static const struct qcom_icc_desc sa8775p_gem_noc =3D { + .nodes =3D gem_noc_nodes, + .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), + .bcms =3D gem_noc_bcms, + .num_bcms =3D ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm *gpdsp_anoc_bcms[] =3D { + &bcm_gna0, + &bcm_gnb0, +}; + +static struct qcom_icc_node *gpdsp_anoc_nodes[] =3D { + [MASTER_DSP0] =3D &qxm_dsp0, + [MASTER_DSP1] =3D &qxm_dsp1, + [SLAVE_GP_DSP_SAIL_NOC] =3D &qns_gp_dsp_sail_noc, +}; + +static const struct qcom_icc_desc sa8775p_gpdsp_anoc =3D { + .nodes =3D gpdsp_anoc_nodes, + .num_nodes =3D ARRAY_SIZE(gpdsp_anoc_nodes), + .bcms =3D gpdsp_anoc_bcms, + .num_bcms =3D ARRAY_SIZE(gpdsp_anoc_bcms), +}; + +static struct qcom_icc_bcm *lpass_ag_noc_bcms[] =3D { + &bcm_sn9, +}; + +static struct qcom_icc_node *lpass_ag_noc_nodes[] =3D { + [MASTER_CNOC_LPASS_AG_NOC] =3D &qhm_config_noc, + [MASTER_LPASS_PROC] =3D &qxm_lpass_dsp, + [SLAVE_LPASS_CORE_CFG] =3D &qhs_lpass_core, + [SLAVE_LPASS_LPI_CFG] =3D &qhs_lpass_lpi, + [SLAVE_LPASS_MPU_CFG] =3D &qhs_lpass_mpu, + [SLAVE_LPASS_TOP_CFG] =3D &qhs_lpass_top, + [SLAVE_LPASS_SNOC] =3D &qns_sysnoc, + [SLAVE_SERVICES_LPASS_AML_NOC] =3D &srvc_niu_aml_noc, + [SLAVE_SERVICE_LPASS_AG_NOC] =3D &srvc_niu_lpass_agnoc, +}; + +static const struct qcom_icc_desc sa8775p_lpass_ag_noc =3D { + .nodes =3D lpass_ag_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), + .bcms =3D lpass_ag_noc_bcms, + .num_bcms =3D ARRAY_SIZE(lpass_ag_noc_bcms), +}; + +static struct qcom_icc_bcm *mc_virt_bcms[] =3D { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node *mc_virt_nodes[] =3D { + [MASTER_LLCC] =3D &llcc_mc, + [SLAVE_EBI1] =3D &ebi, +}; + +static const struct qcom_icc_desc sa8775p_mc_virt =3D { + .nodes =3D mc_virt_nodes, + .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), + .bcms =3D mc_virt_bcms, + .num_bcms =3D ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm *mmss_noc_bcms[] =3D { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node *mmss_noc_nodes[] =3D { + [MASTER_CAMNOC_HF] =3D &qnm_camnoc_hf, + [MASTER_CAMNOC_ICP] =3D &qnm_camnoc_icp, + [MASTER_CAMNOC_SF] =3D &qnm_camnoc_sf, + [MASTER_MDP0] =3D &qnm_mdp0_0, + [MASTER_MDP1] =3D &qnm_mdp0_1, + [MASTER_MDP_CORE1_0] =3D &qnm_mdp1_0, + [MASTER_MDP_CORE1_1] =3D &qnm_mdp1_1, + [MASTER_CNOC_MNOC_HF_CFG] =3D &qnm_mnoc_hf_cfg, + [MASTER_CNOC_MNOC_SF_CFG] =3D &qnm_mnoc_sf_cfg, + [MASTER_VIDEO_P0] =3D &qnm_video0, + [MASTER_VIDEO_P1] =3D &qnm_video1, + [MASTER_VIDEO_PROC] =3D &qnm_video_cvp, + [MASTER_VIDEO_V_PROC] =3D &qnm_video_v_cpu, + [SLAVE_MNOC_HF_MEM_NOC] =3D &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] =3D &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC_HF] =3D &srvc_mnoc_hf, + [SLAVE_SERVICE_MNOC_SF] =3D &srvc_mnoc_sf, +}; + +static const struct qcom_icc_desc sa8775p_mmss_noc =3D { + .nodes =3D mmss_noc_nodes, + .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), + .bcms =3D mmss_noc_bcms, + .num_bcms =3D ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm *nspa_noc_bcms[] =3D { + &bcm_nsa0, + &bcm_nsa1, +}; + +static struct qcom_icc_node *nspa_noc_nodes[] =3D { + [MASTER_CDSP_NOC_CFG] =3D &qhm_nsp_noc_config, + [MASTER_CDSP_PROC] =3D &qxm_nsp, + [SLAVE_HCP_A] =3D &qns_hcp, + [SLAVE_CDSP_MEM_NOC] =3D &qns_nsp_gemnoc, + [SLAVE_SERVICE_NSP_NOC] =3D &service_nsp_noc, +}; + +static const struct qcom_icc_desc sa8775p_nspa_noc =3D { + .nodes =3D nspa_noc_nodes, + .num_nodes =3D ARRAY_SIZE(nspa_noc_nodes), + .bcms =3D nspa_noc_bcms, + .num_bcms =3D ARRAY_SIZE(nspa_noc_bcms), +}; + +static struct qcom_icc_bcm *nspb_noc_bcms[] =3D { + &bcm_nsb0, + &bcm_nsb1, +}; + +static struct qcom_icc_node *nspb_noc_nodes[] =3D { + [MASTER_CDSPB_NOC_CFG] =3D &qhm_nspb_noc_config, + [MASTER_CDSP_PROC_B] =3D &qxm_nspb, + [SLAVE_CDSPB_MEM_NOC] =3D &qns_nspb_gemnoc, + [SLAVE_HCP_B] =3D &qns_nspb_hcp, + [SLAVE_SERVICE_NSPB_NOC] =3D &service_nspb_noc, +}; + +static const struct qcom_icc_desc sa8775p_nspb_noc =3D { + .nodes =3D nspb_noc_nodes, + .num_nodes =3D ARRAY_SIZE(nspb_noc_nodes), + .bcms =3D nspb_noc_bcms, + .num_bcms =3D ARRAY_SIZE(nspb_noc_bcms), +}; + +static struct qcom_icc_bcm *pcie_anoc_bcms[] =3D { + &bcm_pci0, +}; + +static struct qcom_icc_node *pcie_anoc_nodes[] =3D { + [MASTER_PCIE_0] =3D &xm_pcie3_0, + [MASTER_PCIE_1] =3D &xm_pcie3_1, + [SLAVE_ANOC_PCIE_GEM_NOC] =3D &qns_pcie_mem_noc, +}; + +static const struct qcom_icc_desc sa8775p_pcie_anoc =3D { + .nodes =3D pcie_anoc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), + .bcms =3D pcie_anoc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_anoc_bcms), +}; + +static struct qcom_icc_bcm *system_noc_bcms[] =3D { + &bcm_sn0, + &bcm_sn1, + &bcm_sn3, + &bcm_sn4, + &bcm_sn9, +}; + +static struct qcom_icc_node *system_noc_nodes[] =3D { + [MASTER_GIC_AHB] =3D &qhm_gic, + [MASTER_A1NOC_SNOC] =3D &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] =3D &qnm_aggre2_noc, + [MASTER_LPASS_ANOC] =3D &qnm_lpass_noc, + [MASTER_SNOC_CFG] =3D &qnm_snoc_cfg, + [MASTER_PIMEM] =3D &qxm_pimem, + [MASTER_GIC] =3D &xm_gic, + [SLAVE_SNOC_GEM_NOC_GC] =3D &qns_gemnoc_gc, + [SLAVE_SNOC_GEM_NOC_SF] =3D &qns_gemnoc_sf, + [SLAVE_SERVICE_SNOC] =3D &srvc_snoc, +}; + +static const struct qcom_icc_desc sa8775p_system_noc =3D { + .nodes =3D system_noc_nodes, + .num_nodes =3D ARRAY_SIZE(system_noc_nodes), + .bcms =3D system_noc_bcms, + .num_bcms =3D ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] =3D { + { .compatible =3D "qcom,sa8775p-aggre1-noc", .data =3D &sa8775p_aggre1_no= c, }, + { .compatible =3D "qcom,sa8775p-aggre2-noc", .data =3D &sa8775p_aggre2_no= c, }, + { .compatible =3D "qcom,sa8775p-clk-virt", .data =3D &sa8775p_clk_virt, }, + { .compatible =3D "qcom,sa8775p-config-noc", .data =3D &sa8775p_config_no= c, }, + { .compatible =3D "qcom,sa8775p-dc-noc", .data =3D &sa8775p_dc_noc, }, + { .compatible =3D "qcom,sa8775p-gem-noc", .data =3D &sa8775p_gem_noc, }, + { .compatible =3D "qcom,sa8775p-gpdsp-anoc", .data =3D &sa8775p_gpdsp_ano= c, }, + { .compatible =3D "qcom,sa8775p-lpass-ag-noc", .data =3D &sa8775p_lpass_a= g_noc, }, + { .compatible =3D "qcom,sa8775p-mc-virt", .data =3D &sa8775p_mc_virt, }, + { .compatible =3D "qcom,sa8775p-mmss-noc", .data =3D &sa8775p_mmss_noc, }, + { .compatible =3D "qcom,sa8775p-nspa-noc", .data =3D &sa8775p_nspa_noc, }, + { .compatible =3D "qcom,sa8775p-nspb-noc", .data =3D &sa8775p_nspb_noc, }, + { .compatible =3D "qcom,sa8775p-pcie-anoc", .data =3D &sa8775p_pcie_anoc,= }, + { .compatible =3D "qcom,sa8775p-system-noc", .data =3D &sa8775p_system_no= c, }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver =3D { + .probe =3D qcom_icc_rpmh_probe, + .remove =3D qcom_icc_rpmh_remove, + .driver =3D { + .name =3D "qnoc-sa8775p", + .of_match_table =3D qnoc_of_match, + .sync_state =3D icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SA8775P NoC driver"); +MODULE_LICENSE("GPL"); --=20 2.37.2