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charset="utf-8" Add DT schema for the pinctrl driver of NXP S32 SoC family. Signed-off-by: Larisa Grigore Signed-off-by: Ghennadi Procopciuc Signed-off-by: Chester Lin Reviewed-by: Rob Herring --- Changes in v4: - Change the representation of available slew-rate DT values from register values to real frequencies. .../pinctrl/nxp,s32g2-siul2-pinctrl.yaml | 123 ++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siu= l2-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctr= l.yaml new file mode 100644 index 000000000000..d49aafd8c5f4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2022 NXP +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G2 pin controller + +maintainers: + - Ghennadi Procopciuc + - Chester Lin + +description: | + S32G2 pinmux is implemented in SIUL2 (System Integration Unit Lite2), + whose memory map is split into two regions: + SIUL2_0 @ 0x4009c000 + SIUL2_1 @ 0x44010000 + + Every SIUL2 region has multiple register types, and here only MSCR and + IMCR registers need to be revealed for kernel to configure pinmux. + + Please note that some register indexes are reserved in S32G2, such as + MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429. + +properties: + compatible: + enum: + - nxp,s32g2-siul2-pinctrl + + reg: + description: | + A list of MSCR/IMCR register regions to be reserved. + - MSCR (Multiplexed Signal Configuration Register) + An MSCR register can configure the associated pin as either a GPIO= pin + or a function output pin depends on the selected signal source. + - IMCR (Input Multiplexed Signal Configuration Register) + An IMCR register can configure the associated pin as function input + pin depends on the selected signal source. + items: + - description: MSCR registers group 0 in SIUL2_0 + - description: MSCR registers group 1 in SIUL2_1 + - description: MSCR registers group 2 in SIUL2_1 + - description: IMCR registers group 0 in SIUL2_0 + - description: IMCR registers group 1 in SIUL2_1 + - description: IMCR registers group 2 in SIUL2_1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '-grp[0-9]$': + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + description: | + Pinctrl node's client devices specify pin muxes using subnodes, + which in turn use the standard properties below. + + properties: + bias-disable: true + bias-high-impedance: true + bias-pull-up: true + bias-pull-down: true + drive-open-drain: true + input-enable: true + output-enable: true + + pinmux: + description: | + An integer array for representing pinmux configurations of + a device. Each integer consists of a PIN_ID and a 4-bit + selected signal source(SSS) as IOMUX setting, which is + calculated as: pinmux =3D (PIN_ID << 4 | SSS) + + slew-rate: + description: Supported slew rate based on Fmax values (MHz) + enum: [83, 133, 150, 166, 208] + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@4009c240 { + compatible =3D "nxp,s32g2-siul2-pinctrl"; + + /* MSCR0-MSCR101 registers on siul2_0 */ + reg =3D <0x4009c240 0x198>, + /* MSCR112-MSCR122 registers on siul2_1 */ + <0x44010400 0x2c>, + /* MSCR144-MSCR190 registers on siul2_1 */ + <0x44010480 0xbc>, + /* IMCR0-IMCR83 registers on siul2_0 */ + <0x4009ca40 0x150>, + /* IMCR119-IMCR397 registers on siul2_1 */ + <0x44010c1c 0x45c>, + /* IMCR430-IMCR495 registers on siul2_1 */ + <0x440110f8 0x108>; + + llce-can0-pins { + llce-can0-grp0 { + pinmux =3D <0x2b0>; + input-enable; + slew-rate =3D <208>; + }; + + llce-can0-grp1 { + pinmux =3D <0x2c2>; + output-enable; + slew-rate =3D <208>; + }; + }; + }; +... --=20 2.37.3 From nobody Sun Sep 14 20:44:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F72EC32793 for ; Wed, 18 Jan 2023 10:46:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229726AbjARKqX (ORCPT ); Wed, 18 Jan 2023 05:46:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229904AbjARKm5 (ORCPT ); Wed, 18 Jan 2023 05:42:57 -0500 Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-he1eur01on2049.outbound.protection.outlook.com [40.107.13.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B126610F0; Wed, 18 Jan 2023 01:48:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; 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charset="utf-8" Add the pinctrl driver for NXP S32 SoC family. This driver is mainly based on NXP's downstream implementation on nxp-auto-linux repo[1]. [1] https://github.com/nxp-auto-linux/linux/tree/bsp35.0-5.15.73-rt/drivers= /pinctrl/freescale Signed-off-by: Matthew Nunez Signed-off-by: Phu Luu An Signed-off-by: Stefan-Gabriel Mirea Signed-off-by: Larisa Grigore Signed-off-by: Ghennadi Procopciuc Signed-off-by: Andrei Stefanescu Signed-off-by: Radu Pirea Signed-off-by: Chester Lin --- Changes in v4: - Add a mapping table for converting the slew rates to register settings. - Move driver files into an independent folder drivers/pinctrl/nxp drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/nxp/Kconfig | 14 + drivers/pinctrl/nxp/Makefile | 4 + drivers/pinctrl/nxp/pinctrl-s32.h | 76 ++ drivers/pinctrl/nxp/pinctrl-s32cc.c | 1004 +++++++++++++++++++++++++++ drivers/pinctrl/nxp/pinctrl-s32g2.c | 773 +++++++++++++++++++++ 7 files changed, 1873 insertions(+) create mode 100644 drivers/pinctrl/nxp/Kconfig create mode 100644 drivers/pinctrl/nxp/Makefile create mode 100644 drivers/pinctrl/nxp/pinctrl-s32.h create mode 100644 drivers/pinctrl/nxp/pinctrl-s32cc.c create mode 100644 drivers/pinctrl/nxp/pinctrl-s32g2.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7d5f5458c72e..2ac142884b98 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -535,6 +535,7 @@ source "drivers/pinctrl/meson/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nomadik/Kconfig" source "drivers/pinctrl/nuvoton/Kconfig" +source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/ralink/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d5939840bb2a..c40397af024b 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_PINCTRL_MESON) +=3D meson/ obj-y +=3D mvebu/ obj-y +=3D nomadik/ obj-y +=3D nuvoton/ +obj-y +=3D nxp/ obj-$(CONFIG_PINCTRL_PXA) +=3D pxa/ obj-$(CONFIG_ARCH_QCOM) +=3D qcom/ obj-$(CONFIG_PINCTRL_RALINK) +=3D ralink/ diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig new file mode 100644 index 000000000000..4b5a36e66719 --- /dev/null +++ b/drivers/pinctrl/nxp/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +config PINCTRL_S32CC + bool + depends on ARCH_S32 && OF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + +config PINCTRL_S32G2 + depends on ARCH_S32 && OF + bool "NXP S32G2 pinctrl driver" + select PINCTRL_S32CC + help + Say Y here to enable the pinctrl driver for NXP S32G2 family SoCs diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile new file mode 100644 index 000000000000..c1cff4870b02 --- /dev/null +++ b/drivers/pinctrl/nxp/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# NXP pin control +obj-$(CONFIG_PINCTRL_S32CC) +=3D pinctrl-s32cc.o +obj-$(CONFIG_PINCTRL_S32G2) +=3D pinctrl-s32g2.o diff --git a/drivers/pinctrl/nxp/pinctrl-s32.h b/drivers/pinctrl/nxp/pinctr= l-s32.h new file mode 100644 index 000000000000..5481d51686df --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-s32.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * S32 pinmux core definitions + * + * Copyright 2016-2020, 2022 NXP + * Copyright (C) 2022 SUSE LLC + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro Ltd. + */ + +#ifndef __DRIVERS_PINCTRL_S32_H +#define __DRIVERS_PINCTRL_S32_H + +struct platform_device; + +/** + * struct s32_pin_group - describes an S32 pin group + * @name: the name of this specific pin group + * @npins: the number of pins in this group array, i.e. the number of + * elements in pin_ids and pin_sss so we can iterate over that arr= ay + * @pin_ids: an array of pin IDs in this group + * @pin_sss: an array of source signal select configs paired with pin_ids + */ +struct s32_pin_group { + const char *name; + unsigned int npins; + unsigned int *pin_ids; + unsigned int *pin_sss; +}; + +/** + * struct s32_pmx_func - describes S32 pinmux functions + * @name: the name of this specific function + * @groups: corresponding pin groups + * @num_groups: the number of groups + */ +struct s32_pmx_func { + const char *name; + const char **groups; + unsigned int num_groups; +}; + +/** + * struct s32_pin_range - pin ID range for each memory region. + * @start: start pin ID + * @end: end pin ID + */ +struct s32_pin_range { + unsigned int start; + unsigned int end; +}; + +struct s32_pinctrl_soc_info { + struct device *dev; + const struct pinctrl_pin_desc *pins; + unsigned int npins; + struct s32_pin_group *groups; + unsigned int ngroups; + struct s32_pmx_func *functions; + unsigned int nfunctions; + unsigned int grp_index; + const struct s32_pin_range *mem_pin_ranges; + unsigned int mem_regions; +}; + +#define S32_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) +#define S32_PAD_CONFIG(idx) ((idx) * 4) +#define S32_PIN_RANGE(_start, _end) { .start =3D _start, .end =3D _end } + +int s32_pinctrl_probe(struct platform_device *pdev, + struct s32_pinctrl_soc_info *info); +#ifdef CONFIG_PM_SLEEP +int s32_pinctrl_resume(struct device *dev); +int s32_pinctrl_suspend(struct device *dev); +#endif +#endif /* __DRIVERS_PINCTRL_S32_H */ diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinc= trl-s32cc.c new file mode 100644 index 000000000000..daf65dd73689 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -0,0 +1,1004 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Core driver for the S32 CC (Common Chassis) pin controller + * + * Copyright 2017-2022 NXP + * Copyright (C) 2022 SUSE LLC + * Copyright 2015-2016 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" +#include "pinctrl-s32.h" + +#define S32CC_PIN_NO_SHIFT 4 + +#define S32_MSCR_SSS_MASK GENMASK(2, 0) +#define S32_MSCR_PUS BIT(12) +#define S32_MSCR_PUE BIT(13) +#define S32_MSCR_SRE(X) (((X) & GENMASK(3, 0)) << 14) +#define S32_MSCR_IBE BIT(19) +#define S32_MSCR_ODE BIT(20) +#define S32_MSCR_OBE BIT(21) + +static u32 get_pin_no(u32 pinmux) +{ + return pinmux >> S32CC_PIN_NO_SHIFT; +} + +static u32 get_pin_func(u32 pinmux) +{ + return pinmux & GENMASK(3, 0); +} + +struct s32_pinctrl_mem_region { + void __iomem *base; + const struct s32_pin_range *pin_range; +}; + +/* + * Holds pin configuration for GPIO's. + * @pin_id: Pin ID for this GPIO + * @config: Pin settings + * @list: Linked list entry for each gpio pin + */ +struct gpio_pin_config { + unsigned int pin_id; + unsigned int config; + struct list_head list; +}; + +/* + * Pad config save/restore for power suspend/resume. + */ +struct s32_pinctrl_context { + unsigned long *pads; +}; + +/* + * @dev: a pointer back to containing device + * @pctl: a pointer to the pinctrl device structure + * @regions: reserved memory regions with start/end pin + * @info: structure containing information about the pin + * @gpio_configs: Saved configurations for GPIO pins + * @gpiop_configs_lock: lock for the `gpio_configs` list + * @s32_pinctrl_context: Configuration saved over system sleep + * @reg_lock: lock for the `mscr/imcrs` registers + */ +struct s32_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + struct s32_pinctrl_mem_region *regions; + struct s32_pinctrl_soc_info *info; + struct list_head gpio_configs; + spinlock_t gpio_configs_lock; +#ifdef CONFIG_PM_SLEEP + struct s32_pinctrl_context saved_context; +#endif + spinlock_t reg_lock; +}; + +static struct s32_pinctrl_mem_region * +s32_get_region(struct pinctrl_dev *pctldev, unsigned int pin) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct s32_pin_range *pin_range; + unsigned int mem_regions =3D ipctl->info->mem_regions; + unsigned int i; + + for (i =3D 0; i < mem_regions; ++i) { + pin_range =3D ipctl->regions[i].pin_range; + if (pin >=3D pin_range->start && pin <=3D pin_range->end) + return &ipctl->regions[i]; + } + + return NULL; +} + +static inline int s32_check_pin(struct pinctrl_dev *pctldev, + unsigned int pin) +{ + return s32_get_region(pctldev, pin) ? 0 : -EINVAL; +} + +static inline int s32_pinctrl_readl_nolock(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + struct s32_pinctrl_mem_region *region; + unsigned int offset; + + region =3D s32_get_region(pctldev, pin); + if (!region) + return -EINVAL; + + offset =3D pin - region->pin_range->start; + + *config =3D readl(region->base + S32_PAD_CONFIG(offset)); + + return 0; +} + +static inline int s32_pinctrl_readl(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + unsigned long flags; + int ret; + + spin_lock_irqsave(&ipctl->reg_lock, flags); + ret =3D s32_pinctrl_readl_nolock(pctldev, pin, config); + spin_unlock_irqrestore(&ipctl->reg_lock, flags); + + return ret; +} + +static inline int s32_pinctrl_writel_nolock(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long config) +{ + struct s32_pinctrl_mem_region *region; + unsigned int offset; + + region =3D s32_get_region(pctldev, pin); + if (!region) + return -EINVAL; + + offset =3D pin - region->pin_range->start; + + writel(config, region->base + S32_PAD_CONFIG(offset)); + + return 0; + +} + +static inline int s32_pinctrl_writel(unsigned long config, + struct pinctrl_dev *pctldev, + unsigned int pin) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + unsigned long flags; + int ret; + + spin_lock_irqsave(&ipctl->reg_lock, flags); + ret =3D s32_pinctrl_writel_nolock(pctldev, pin, config); + spin_unlock_irqrestore(&ipctl->reg_lock, flags); + + return ret; +} + +static int s32_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct s32_pinctrl_soc_info *info =3D ipctl->info; + + return info->ngroups; +} + +static const char *s32_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct s32_pinctrl_soc_info *info =3D ipctl->info; + + return info->groups[selector].name; +} + +static int s32_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, const unsigned int **pins, + unsigned int *npins) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct s32_pinctrl_soc_info *info =3D ipctl->info; + + *pins =3D info->groups[selector].pin_ids; + *npins =3D info->groups[selector].npins; + + return 0; +} + +static void s32_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file = *s, + unsigned int offset) +{ + seq_printf(s, "%s", dev_name(pctldev->dev)); +} + +static int s32_dt_group_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *reserved_maps, + unsigned int *num_maps, + const char *func_name) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + struct device *dev =3D ipctl->dev; + unsigned long *cfgs =3D NULL; + unsigned int n_cfgs, reserve =3D 1; + int n_pins, ret; + + n_pins =3D of_property_count_elems_of_size(np, "pinmux", sizeof(u32)); + if (n_pins < 0) { + dev_warn(dev, "Unable to find 'pinmux' property in node %s.\n", + np->name); + } else if (!n_pins) { + return -EINVAL; + } + + ret =3D pinconf_generic_parse_dt_config(np, pctldev, &cfgs, &n_cfgs); + if (ret) { + dev_err(dev, "%pOF: could not parse node property\n", np); + return ret; + } + + if (n_cfgs) + reserve++; + + ret =3D pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, + reserve); + if (ret < 0) + goto free_cfgs; + + ret =3D pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, + np->name, func_name); + if (ret < 0) + goto free_cfgs; + + if (n_cfgs) { + ret =3D pinctrl_utils_add_map_configs(pctldev, map, reserved_maps, + num_maps, np->name, cfgs, n_cfgs, + PIN_MAP_TYPE_CONFIGS_GROUP); + if (ret < 0) + goto free_cfgs; + } + +free_cfgs: + kfree(cfgs); + return ret; +} + +static int s32_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + unsigned int reserved_maps; + struct device_node *np; + int ret =3D 0; + + reserved_maps =3D 0; + *map =3D NULL; + *num_maps =3D 0; + + for_each_available_child_of_node(np_config, np) { + ret =3D s32_dt_group_node_to_map(pctldev, np, map, + &reserved_maps, num_maps, + np_config->name); + if (ret < 0) + break; + } + + if (ret) + pinctrl_utils_free_map(pctldev, *map, *num_maps); + + return ret; + +} + +static const struct pinctrl_ops s32_pctrl_ops =3D { + .get_groups_count =3D s32_get_groups_count, + .get_group_name =3D s32_get_group_name, + .get_group_pins =3D s32_get_group_pins, + .pin_dbg_show =3D s32_pin_dbg_show, + .dt_node_to_map =3D s32_dt_node_to_map, + .dt_free_map =3D pinctrl_utils_free_map, +}; + +static int s32_update_pin_mscr(struct pinctrl_dev *pctldev, unsigned int p= in, + unsigned long mask, unsigned long new_mask) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + unsigned long config, flags; + int ret; + + spin_lock_irqsave(&ipctl->reg_lock, flags); + + ret =3D s32_pinctrl_readl_nolock(pctldev, pin, &config); + if (ret) + goto unlock; + + config &=3D ~mask; + config |=3D new_mask; + + ret =3D s32_pinctrl_writel_nolock(pctldev, pin, config); + if (ret) + goto unlock; + +unlock: + spin_unlock_irqrestore(&ipctl->reg_lock, flags); + + return ret; +} + +static int s32_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector, + unsigned int group) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct s32_pinctrl_soc_info *info =3D ipctl->info; + int i, ret; + struct s32_pin_group *grp; + + /* + * Configure the mux mode for each pin in the group for a specific + * function. + */ + grp =3D &info->groups[group]; + + dev_dbg(ipctl->dev, "set mux for function %s group %s\n", + info->functions[selector].name, grp->name); + + /* Check beforehand so we don't have a partial config. */ + for (i =3D 0; i < grp->npins; ++i) { + if (s32_check_pin(pctldev, grp->pin_ids[i]) !=3D 0) { + dev_err(info->dev, "invalid pin: %d in group: %d\n", + grp->pin_ids[i], group); + return -EINVAL; + } + } + + for (i =3D 0, ret =3D 0; i < grp->npins && !ret; ++i) { + ret =3D s32_update_pin_mscr(pctldev, grp->pin_ids[i], + S32_MSCR_SSS_MASK, grp->pin_sss[i]); + } + + return ret; +} + +static int s32_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct s32_pinctrl_soc_info *info =3D ipctl->info; + + return info->nfunctions; +} + +static const char *s32_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct s32_pinctrl_soc_info *info =3D ipctl->info; + + return info->functions[selector].name; +} + +static int s32_pmx_get_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct s32_pinctrl_soc_info *info =3D ipctl->info; + + *groups =3D info->functions[selector].groups; + *num_groups =3D info->functions[selector].num_groups; + + return 0; +} + +static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + unsigned long config; + struct gpio_pin_config *gpio_pin; + unsigned long flags; + int ret; + + ret =3D s32_pinctrl_readl(pctldev, offset, &config); + if (ret !=3D 0) + return -EINVAL; + + /* Save current configuration */ + gpio_pin =3D kmalloc(sizeof(*gpio_pin), GFP_KERNEL); + if (!gpio_pin) + return -ENOMEM; + + gpio_pin->pin_id =3D offset; + gpio_pin->config =3D config; + + spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); + list_add(&(gpio_pin->list), &(ipctl->gpio_configs)); + spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); + + /* GPIO pin means SSS =3D 0 */ + config &=3D ~S32_MSCR_SSS_MASK; + + return s32_pinctrl_writel(config, pctldev, offset); +} + +static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + struct list_head *pos, *tmp; + struct gpio_pin_config *gpio_pin; + unsigned long flags; + int ret; + + spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); + + list_for_each_safe(pos, tmp, &ipctl->gpio_configs) { + gpio_pin =3D list_entry(pos, struct gpio_pin_config, list); + + if (gpio_pin->pin_id =3D=3D offset) { + ret =3D s32_pinctrl_writel(gpio_pin->config, pctldev, + gpio_pin->pin_id); + if (ret !=3D 0) + goto unlock; + + list_del(pos); + kfree(gpio_pin); + break; + } + } + +unlock: + spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); +} + +static int s32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset, + bool input) +{ + unsigned long config; + int ret; + + ret =3D s32_pinctrl_readl(pctldev, offset, &config); + if (ret !=3D 0) + return -EINVAL; + + if (input) { + /* Disable output buffer and enable input buffer */ + config &=3D ~S32_MSCR_OBE; + config |=3D S32_MSCR_IBE; + } else { + /* Disable input buffer and enable output buffer */ + config &=3D ~S32_MSCR_IBE; + config |=3D S32_MSCR_OBE; + } + + return s32_pinctrl_writel(config, pctldev, offset); +} + +static const struct pinmux_ops s32_pmx_ops =3D { + .get_functions_count =3D s32_pmx_get_funcs_count, + .get_function_name =3D s32_pmx_get_func_name, + .get_function_groups =3D s32_pmx_get_groups, + .set_mux =3D s32_pmx_set, + .gpio_request_enable =3D s32_pmx_gpio_request_enable, + .gpio_disable_free =3D s32_pmx_gpio_disable_free, + .gpio_set_direction =3D s32_pmx_gpio_set_direction, +}; + +static int s32_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin_id, + unsigned long *config) +{ + int ret =3D s32_pinctrl_readl(pctldev, pin_id, config); + + if (ret) + return -EINVAL; + + return 0; +} + +/* Set the reserved elements as -1 */ +static const int support_slew[] =3D {208, -1, -1, -1, 166, 150, 133, 83}; + +static int s32_get_slew_regval(int arg) +{ + int i; + /* Translate a real slew rate (MHz) to a register value */ + for (i =3D 0; i < ARRAY_SIZE(support_slew); i++) { + if (arg =3D=3D support_slew[i]) + return i; + } + + return -EINVAL; +} + +static int s32_get_pin_conf(enum pin_config_param param, u32 arg, + unsigned long *mask, unsigned long *config) +{ + int ret; + + switch (param) { + /* All pins are persistent over suspend */ + case PIN_CONFIG_PERSIST_STATE: + return 0; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + *config |=3D S32_MSCR_ODE; + *mask |=3D S32_MSCR_ODE; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + if (arg) + *config |=3D S32_MSCR_OBE; + else + *config &=3D ~S32_MSCR_OBE; + *mask |=3D S32_MSCR_OBE; + break; + case PIN_CONFIG_INPUT_ENABLE: + if (arg) + *config |=3D S32_MSCR_IBE; + else + *config &=3D ~S32_MSCR_IBE; + *mask |=3D S32_MSCR_IBE; + break; + case PIN_CONFIG_SLEW_RATE: + ret =3D s32_get_slew_regval(arg); + if (ret < 0) + return ret; + *config |=3D S32_MSCR_SRE((u32)ret); + *mask |=3D S32_MSCR_SRE(~0); + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg) + *config |=3D S32_MSCR_PUS; + else + *config &=3D ~S32_MSCR_PUS; + fallthrough; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg) + *config |=3D S32_MSCR_PUE; + else + *config &=3D ~S32_MSCR_PUE; + *mask |=3D S32_MSCR_PUE | S32_MSCR_PUS; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + *config &=3D ~(S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE); + *mask |=3D S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE; + fallthrough; + case PIN_CONFIG_BIAS_DISABLE: + *config &=3D ~(S32_MSCR_PUS | S32_MSCR_PUE); + *mask |=3D S32_MSCR_PUS | S32_MSCR_PUE; + break; + default: + return -EOPNOTSUPP; + } + + return 0; +} + +static int s32_pinconf_mscr_modify_write(struct pinctrl_dev *pctldev, + unsigned int pin_id, + unsigned long *configs, + unsigned int num_configs, bool write) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + unsigned long config =3D 0, mask =3D 0; + int i, ret; + + if (s32_check_pin(pctldev, pin_id) !=3D 0) + return -EINVAL; + + dev_dbg(ipctl->dev, "pinconf set pin %s with %d configs\n", + pin_get_name(pctldev, pin_id), num_configs); + + for (i =3D 0; i < num_configs; i++) { + ret =3D s32_get_pin_conf(pinconf_to_config_param(configs[i]), + pinconf_to_config_argument(configs[i]), + &mask, &config); + if (ret) + return ret; + } + + /* If the MSCR configuration has to be written, + * the SSS field should not be touched. + */ + if (write) + mask =3D ~S32_MSCR_SSS_MASK; + + if (!config && !mask) + return 0; + + ret =3D s32_update_pin_mscr(pctldev, pin_id, mask, config); + + dev_dbg(ipctl->dev, "%s: pin %d cfg 0x%lx\n", + write ? "set" : "update", pin_id, config); + + return ret; +} + +static int s32_pinconf_mscr_write(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *configs, + unsigned int num_configs) +{ + return s32_pinconf_mscr_modify_write(pctldev, pin_id, configs, + num_configs, true); +} + +static int s32_pinconf_mscr_modify(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *configs, + unsigned int num_configs) +{ + return s32_pinconf_mscr_modify_write(pctldev, pin_id, configs, + num_configs, false); +} + +static int s32_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *configs, + unsigned int num_configs) +{ + return s32_pinconf_mscr_modify(pctldev, pin_id, configs, num_configs); +} + +static int s32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int s= elector, + unsigned long *configs, unsigned int num_configs) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct s32_pinctrl_soc_info *info =3D ipctl->info; + struct s32_pin_group *grp; + int i, ret; + + grp =3D &info->groups[selector]; + for (i =3D 0; i < grp->npins; i++) { + ret =3D s32_pinconf_mscr_write(pctldev, grp->pin_ids[i], + configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static void s32_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin_id) +{ + unsigned long config; + int ret =3D s32_pinctrl_readl(pctldev, pin_id, &config); + + if (!ret) + seq_printf(s, "0x%lx", config); +} + +static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int selector) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct s32_pinctrl_soc_info *info =3D ipctl->info; + struct s32_pin_group *grp; + unsigned long config; + const char *name; + int i, ret; + + seq_puts(s, "\n"); + grp =3D &info->groups[selector]; + for (i =3D 0; i < grp->npins; i++) { + name =3D pin_get_name(pctldev, grp->pin_ids[i]); + ret =3D s32_pinconf_get(pctldev, grp->pin_ids[i], &config); + if (ret) + return; + seq_printf(s, "%s: 0x%lx\n", name, config); + } +} + +static const struct pinconf_ops s32_pinconf_ops =3D { + .pin_config_get =3D s32_pinconf_get, + .pin_config_set =3D s32_pinconf_set, + .pin_config_group_set =3D s32_pconf_group_set, + .pin_config_dbg_show =3D s32_pinconf_dbg_show, + .pin_config_group_dbg_show =3D s32_pinconf_group_dbg_show, +}; + +#ifdef CONFIG_PM_SLEEP +static bool s32_pinctrl_should_save(struct s32_pinctrl *ipctl, + unsigned int pin) +{ + const struct pin_desc *pd =3D pin_desc_get(ipctl->pctl, pin); + + if (!pd) + return false; + + /* + * Only restore the pin if it is actually in use by the kernel (or + * by userspace). + */ + if (pd->mux_owner || pd->gpio_owner) + return true; + + return false; +} + +int s32_pinctrl_suspend(struct device *dev) +{ + struct platform_device *pdev =3D to_platform_device(dev); + struct s32_pinctrl *ipctl =3D platform_get_drvdata(pdev); + const struct pinctrl_pin_desc *pin; + const struct s32_pinctrl_soc_info *info =3D ipctl->info; + struct s32_pinctrl_context *saved_context =3D &ipctl->saved_context; + int i; + int ret; + unsigned long config; + + for (i =3D 0; i < info->npins; i++) { + pin =3D &info->pins[i]; + + if (!s32_pinctrl_should_save(ipctl, pin->number)) + continue; + + ret =3D s32_pinctrl_readl(ipctl->pctl, pin->number, &config); + if (ret) + return -EINVAL; + + saved_context->pads[i] =3D config; + } + + return 0; +} + +int s32_pinctrl_resume(struct device *dev) +{ + struct platform_device *pdev =3D to_platform_device(dev); + struct s32_pinctrl *ipctl =3D platform_get_drvdata(pdev); + const struct s32_pinctrl_soc_info *info =3D ipctl->info; + const struct pinctrl_pin_desc *pin; + struct s32_pinctrl_context *saved_context =3D &ipctl->saved_context; + int ret, i; + + for (i =3D 0; i < info->npins; i++) { + pin =3D &info->pins[i]; + + if (!s32_pinctrl_should_save(ipctl, pin->number)) + continue; + + ret =3D s32_pinctrl_writel(saved_context->pads[i], + ipctl->pctl, pin->number); + if (ret) + return ret; + } + + return 0; +} +#endif + +static void s32_pinctrl_parse_groups(struct device_node *np, + struct s32_pin_group *grp, + struct s32_pinctrl_soc_info *info) +{ + const __be32 *p; + struct device *dev; + struct property *prop; + int i, npins; + u32 pinmux; + + dev =3D info->dev; + + dev_dbg(dev, "group: %s\n", np->name); + + /* Initialise group */ + grp->name =3D np->name; + + npins =3D of_property_count_elems_of_size(np, "pinmux", sizeof(u32)); + + if (npins < 0) { + dev_err(dev, "Failed to read 'pinmux' property in node %s.\n", + np->name); + return; + } + if (!npins) { + dev_err(dev, "The group %s has no pins.\n", np->name); + return; + } + + grp->npins =3D npins; + + grp->pin_ids =3D devm_kcalloc(info->dev, grp->npins, + sizeof(unsigned int), GFP_KERNEL); + grp->pin_sss =3D devm_kcalloc(info->dev, grp->npins, + sizeof(unsigned int), GFP_KERNEL); + + if (!grp->pin_ids || !grp->pin_sss) { + dev_err(dev, "Failed to allocate memory for the group %s.\n", + np->name); + return; + } + + i =3D 0; + of_property_for_each_u32(np, "pinmux", prop, p, pinmux) { + grp->pin_ids[i] =3D get_pin_no(pinmux); + grp->pin_sss[i] =3D get_pin_func(pinmux); + + dev_dbg(info->dev, "pin-id: 0x%x, sss: 0x%x", + grp->pin_ids[i], grp->pin_sss[i]); + i++; + } +} + +static void s32_pinctrl_parse_functions(struct device_node *np, + struct s32_pinctrl_soc_info *info, + u32 index) +{ + struct device_node *child; + struct s32_pmx_func *func; + struct s32_pin_group *grp; + u32 i =3D 0; + + dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); + + func =3D &info->functions[index]; + + /* Initialise function */ + func->name =3D np->name; + func->num_groups =3D of_get_child_count(np); + if (func->num_groups =3D=3D 0) { + dev_err(info->dev, "no groups defined in %s\n", np->full_name); + return; + } + func->groups =3D devm_kzalloc(info->dev, + func->num_groups * sizeof(char *), GFP_KERNEL); + + for_each_child_of_node(np, child) { + func->groups[i] =3D child->name; + grp =3D &info->groups[info->grp_index++]; + s32_pinctrl_parse_groups(child, grp, info); + i++; + } +} + +static int s32_pinctrl_probe_dt(struct platform_device *pdev, + struct s32_pinctrl *ipctl) +{ + struct s32_pinctrl_soc_info *info =3D ipctl->info; + struct device_node *np =3D pdev->dev.of_node; + struct device_node *child; + struct resource *res; + int mem_regions =3D info->mem_regions; + u32 nfuncs =3D 0; + u32 i =3D 0; + + if (!np) + return -ENODEV; + + if (mem_regions =3D=3D 0) { + dev_err(&pdev->dev, "mem_regions is 0\n"); + return -EINVAL; + } + + ipctl->regions =3D devm_kzalloc(&pdev->dev, + mem_regions * sizeof(*(ipctl->regions)), + GFP_KERNEL); + if (!ipctl->regions) + return -ENOMEM; + + for (i =3D 0; i < mem_regions; ++i) { + res =3D platform_get_resource(pdev, IORESOURCE_MEM, i); + if (!res) { + dev_err(&pdev->dev, "reg index:%u not found\n", i); + return -EINVAL; + } + + ipctl->regions[i].base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(ipctl->regions[i].base)) + return PTR_ERR(ipctl->regions[i].base); + + ipctl->regions[i].pin_range =3D &info->mem_pin_ranges[i]; + } + + nfuncs =3D of_get_child_count(np); + if (nfuncs <=3D 0) { + dev_err(&pdev->dev, "no functions defined\n"); + return -EINVAL; + } + + info->nfunctions =3D nfuncs; + info->functions =3D devm_kzalloc(&pdev->dev, + nfuncs * sizeof(struct s32_pmx_func), + GFP_KERNEL); + if (!info->functions) + return -ENOMEM; + + info->ngroups =3D 0; + for_each_child_of_node(np, child) + info->ngroups +=3D of_get_child_count(child); + info->groups =3D devm_kzalloc(&pdev->dev, + info->ngroups * sizeof(struct s32_pin_group), + GFP_KERNEL); + if (!info->groups) + return -ENOMEM; + + i =3D 0; + for_each_child_of_node(np, child) + s32_pinctrl_parse_functions(child, info, i++); + + return 0; +} + +int s32_pinctrl_probe(struct platform_device *pdev, + struct s32_pinctrl_soc_info *info) +{ + struct s32_pinctrl *ipctl; + int ret; + struct pinctrl_desc *s32_pinctrl_desc; +#ifdef CONFIG_PM_SLEEP + struct s32_pinctrl_context *saved_context; +#endif + + if (!info || !info->pins || !info->npins) { + dev_err(&pdev->dev, "wrong pinctrl info\n"); + return -EINVAL; + } + + info->dev =3D &pdev->dev; + + /* Create state holders etc for this driver */ + ipctl =3D devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); + if (!ipctl) + return -ENOMEM; + + ipctl->info =3D info; + ipctl->dev =3D info->dev; + platform_set_drvdata(pdev, ipctl); + + INIT_LIST_HEAD(&ipctl->gpio_configs); + spin_lock_init(&ipctl->gpio_configs_lock); + spin_lock_init(&ipctl->reg_lock); + + s32_pinctrl_desc =3D + devm_kmalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL); + if (!s32_pinctrl_desc) + return -ENOMEM; + + s32_pinctrl_desc->name =3D dev_name(&pdev->dev); + s32_pinctrl_desc->pins =3D info->pins; + s32_pinctrl_desc->npins =3D info->npins; + s32_pinctrl_desc->pctlops =3D &s32_pctrl_ops; + s32_pinctrl_desc->pmxops =3D &s32_pmx_ops; + s32_pinctrl_desc->confops =3D &s32_pinconf_ops; + s32_pinctrl_desc->owner =3D THIS_MODULE; + + ret =3D s32_pinctrl_probe_dt(pdev, ipctl); + if (ret) { + dev_err(&pdev->dev, "fail to probe dt properties\n"); + return ret; + } + + ipctl->pctl =3D devm_pinctrl_register(&pdev->dev, s32_pinctrl_desc, + ipctl); + + if (IS_ERR(ipctl->pctl)) { + dev_err(&pdev->dev, "could not register s32 pinctrl driver\n"); + return PTR_ERR(ipctl->pctl); + } + +#ifdef CONFIG_PM_SLEEP + saved_context =3D &ipctl->saved_context; + saved_context->pads =3D + devm_kcalloc(&pdev->dev, info->npins, + sizeof(*saved_context->pads), + GFP_KERNEL); + if (!saved_context->pads) + return -ENOMEM; +#endif + + dev_info(&pdev->dev, "initialized s32 pinctrl driver\n"); + + return 0; +} diff --git a/drivers/pinctrl/nxp/pinctrl-s32g2.c b/drivers/pinctrl/nxp/pinc= trl-s32g2.c new file mode 100644 index 000000000000..7dd0b4f8904d --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-s32g2.c @@ -0,0 +1,773 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * NXP S32G pinctrl driver + * + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018, 2020-2022 NXP + * Copyright (C) 2022 SUSE LLC + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-s32.h" + +enum s32_pins { + S32G_MSCR_PA_00 =3D 0, + S32G_MSCR_PA_01 =3D 1, + S32G_MSCR_PA_02 =3D 2, + S32G_MSCR_PA_03 =3D 3, + S32G_MSCR_PA_04 =3D 4, + S32G_MSCR_PA_05 =3D 5, + S32G_MSCR_PA_06 =3D 6, + S32G_MSCR_PA_07 =3D 7, + S32G_MSCR_PA_08 =3D 8, + S32G_MSCR_PA_09 =3D 9, + S32G_MSCR_PA_10 =3D 10, + S32G_MSCR_PA_11 =3D 11, + S32G_MSCR_PA_12 =3D 12, + S32G_MSCR_PA_13 =3D 13, + S32G_MSCR_PA_14 =3D 14, + S32G_MSCR_PA_15 =3D 15, + S32G_MSCR_PB_00 =3D 16, + S32G_MSCR_PB_01 =3D 17, + S32G_MSCR_PB_02 =3D 18, + S32G_MSCR_PB_03 =3D 19, + S32G_MSCR_PB_04 =3D 20, + S32G_MSCR_PB_05 =3D 21, + S32G_MSCR_PB_06 =3D 22, + S32G_MSCR_PB_07 =3D 23, + S32G_MSCR_PB_08 =3D 24, + S32G_MSCR_PB_09 =3D 25, + S32G_MSCR_PB_10 =3D 26, + S32G_MSCR_PB_11 =3D 27, + S32G_MSCR_PB_12 =3D 28, + S32G_MSCR_PB_13 =3D 29, + S32G_MSCR_PB_14 =3D 30, + S32G_MSCR_PB_15 =3D 31, + S32G_MSCR_PC_00 =3D 32, + S32G_MSCR_PC_01 =3D 33, + S32G_MSCR_PC_02 =3D 34, + S32G_MSCR_PC_03 =3D 35, + S32G_MSCR_PC_04 =3D 36, + S32G_MSCR_PC_05 =3D 37, + S32G_MSCR_PC_06 =3D 38, + S32G_MSCR_PC_07 =3D 39, + S32G_MSCR_PC_08 =3D 40, + S32G_MSCR_PC_09 =3D 41, + S32G_MSCR_PC_10 =3D 42, + S32G_MSCR_PC_11 =3D 43, + S32G_MSCR_PC_12 =3D 44, + S32G_MSCR_PC_13 =3D 45, + S32G_MSCR_PC_14 =3D 46, + S32G_MSCR_PC_15 =3D 47, + S32G_MSCR_PD_00 =3D 48, + S32G_MSCR_PD_01 =3D 49, + S32G_MSCR_PD_02 =3D 50, + S32G_MSCR_PD_03 =3D 51, + S32G_MSCR_PD_04 =3D 52, + S32G_MSCR_PD_05 =3D 53, + S32G_MSCR_PD_06 =3D 54, + S32G_MSCR_PD_07 =3D 55, + S32G_MSCR_PD_08 =3D 56, + S32G_MSCR_PD_09 =3D 57, + S32G_MSCR_PD_10 =3D 58, + S32G_MSCR_PD_11 =3D 59, + S32G_MSCR_PD_12 =3D 60, + S32G_MSCR_PD_13 =3D 61, + S32G_MSCR_PD_14 =3D 62, + S32G_MSCR_PD_15 =3D 63, + S32G_MSCR_PE_00 =3D 64, + S32G_MSCR_PE_01 =3D 65, + S32G_MSCR_PE_02 =3D 66, + S32G_MSCR_PE_03 =3D 67, + S32G_MSCR_PE_04 =3D 68, + S32G_MSCR_PE_05 =3D 69, + S32G_MSCR_PE_06 =3D 70, + S32G_MSCR_PE_07 =3D 71, + S32G_MSCR_PE_08 =3D 72, + S32G_MSCR_PE_09 =3D 73, + S32G_MSCR_PE_10 =3D 74, + S32G_MSCR_PE_11 =3D 75, + S32G_MSCR_PE_12 =3D 76, + S32G_MSCR_PE_13 =3D 77, + S32G_MSCR_PE_14 =3D 78, + S32G_MSCR_PE_15 =3D 79, + S32G_MSCR_PF_00 =3D 80, + S32G_MSCR_PF_01 =3D 81, + S32G_MSCR_PF_02 =3D 82, + S32G_MSCR_PF_03 =3D 83, + S32G_MSCR_PF_04 =3D 84, + S32G_MSCR_PF_05 =3D 85, + S32G_MSCR_PF_06 =3D 86, + S32G_MSCR_PF_07 =3D 87, + S32G_MSCR_PF_08 =3D 88, + S32G_MSCR_PF_09 =3D 89, + S32G_MSCR_PF_10 =3D 90, + S32G_MSCR_PF_11 =3D 91, + S32G_MSCR_PF_12 =3D 92, + S32G_MSCR_PF_13 =3D 93, + S32G_MSCR_PF_14 =3D 94, + S32G_MSCR_PF_15 =3D 95, + S32G_MSCR_PG_00 =3D 96, + S32G_MSCR_PG_01 =3D 97, + S32G_MSCR_PG_02 =3D 98, + S32G_MSCR_PG_03 =3D 99, + S32G_MSCR_PG_04 =3D 100, + S32G_MSCR_PG_05 =3D 101, + S32G_MSCR_PH_00 =3D 112, + S32G_MSCR_PH_01 =3D 113, + S32G_MSCR_PH_02 =3D 114, + S32G_MSCR_PH_03 =3D 115, + S32G_MSCR_PH_04 =3D 116, + S32G_MSCR_PH_05 =3D 117, + S32G_MSCR_PH_06 =3D 118, + S32G_MSCR_PH_07 =3D 119, + S32G_MSCR_PH_08 =3D 120, + S32G_MSCR_PH_09 =3D 121, + S32G_MSCR_PH_10 =3D 122, + S32G_MSCR_PJ_00 =3D 144, + S32G_MSCR_PJ_01 =3D 145, + S32G_MSCR_PJ_02 =3D 146, + S32G_MSCR_PJ_03 =3D 147, + S32G_MSCR_PJ_04 =3D 148, + S32G_MSCR_PJ_05 =3D 149, + S32G_MSCR_PJ_06 =3D 150, + S32G_MSCR_PJ_07 =3D 151, + S32G_MSCR_PJ_08 =3D 152, + S32G_MSCR_PJ_09 =3D 153, + S32G_MSCR_PJ_10 =3D 154, + S32G_MSCR_PJ_11 =3D 155, + S32G_MSCR_PJ_12 =3D 156, + S32G_MSCR_PJ_13 =3D 157, + S32G_MSCR_PJ_14 =3D 158, + S32G_MSCR_PJ_15 =3D 159, + S32G_MSCR_PK_00 =3D 160, + S32G_MSCR_PK_01 =3D 161, + S32G_MSCR_PK_02 =3D 162, + S32G_MSCR_PK_03 =3D 163, + S32G_MSCR_PK_04 =3D 164, + S32G_MSCR_PK_05 =3D 165, + S32G_MSCR_PK_06 =3D 166, + S32G_MSCR_PK_07 =3D 167, + S32G_MSCR_PK_08 =3D 168, + S32G_MSCR_PK_09 =3D 169, + S32G_MSCR_PK_10 =3D 170, + S32G_MSCR_PK_11 =3D 171, + S32G_MSCR_PK_12 =3D 172, + S32G_MSCR_PK_13 =3D 173, + S32G_MSCR_PK_14 =3D 174, + S32G_MSCR_PK_15 =3D 175, + S32G_MSCR_PL_00 =3D 176, + S32G_MSCR_PL_01 =3D 177, + S32G_MSCR_PL_02 =3D 178, + S32G_MSCR_PL_03 =3D 179, + S32G_MSCR_PL_04 =3D 180, + S32G_MSCR_PL_05 =3D 181, + S32G_MSCR_PL_06 =3D 182, + S32G_MSCR_PL_07 =3D 183, + S32G_MSCR_PL_08 =3D 184, + S32G_MSCR_PL_09 =3D 185, + S32G_MSCR_PL_10 =3D 186, + S32G_MSCR_PL_11 =3D 187, + S32G_MSCR_PL_12 =3D 188, + S32G_MSCR_PL_13 =3D 189, + S32G_MSCR_PL_14 =3D 190, + + S32G_IMCR_QSPI_A_DATA0 =3D 540, + S32G_IMCR_QSPI_A_DATA1 =3D 541, + S32G_IMCR_QSPI_A_DATA2 =3D 542, + S32G_IMCR_QSPI_A_DATA3 =3D 543, + S32G_IMCR_QSPI_A_DATA4 =3D 544, + S32G_IMCR_QSPI_A_DATA5 =3D 545, + S32G_IMCR_QSPI_A_DATA6 =3D 546, + S32G_IMCR_QSPI_A_DATA7 =3D 547, + S32G_IMCR_QSPI_DQS_A =3D 548, + S32G_IMCR_QSPI_B_DATA0 =3D 552, + S32G_IMCR_QSPI_B_DATA1 =3D 554, + S32G_IMCR_QSPI_B_DATA2 =3D 551, + S32G_IMCR_QSPI_B_DATA3 =3D 553, + S32G_IMCR_QSPI_B_DATA4 =3D 557, + S32G_IMCR_QSPI_B_DATA5 =3D 550, + S32G_IMCR_QSPI_B_DATA6 =3D 556, + S32G_IMCR_QSPI_B_DATA7 =3D 555, + S32G_IMCR_QSPI_DQS_B =3D 558, + S32G_IMCR_BOOT_BOOTMOD0 =3D 560, + S32G_IMCR_BOOT_BOOTMOD1 =3D 561, + S32G_IMCR_I2C0_SCL =3D 566, + S32G_IMCR_I2C0_SDA =3D 565, + S32G_IMCR_LIN0_RX =3D 512, + S32G_IMCR_USDHC_CMD =3D 515, + S32G_IMCR_USDHC_DAT0 =3D 516, + S32G_IMCR_USDHC_DAT1 =3D 517, + S32G_IMCR_USDHC_DAT2 =3D 520, + S32G_IMCR_USDHC_DAT3 =3D 521, + S32G_IMCR_USDHC_DAT4 =3D 522, + S32G_IMCR_USDHC_DAT5 =3D 523, + S32G_IMCR_USDHC_DAT6 =3D 519, + S32G_IMCR_USDHC_DAT7 =3D 518, + S32G_IMCR_USDHC_DQS =3D 524, + S32G_IMCR_CAN0_RXD =3D 513, + S32G_IMCR_CAN1_RXD =3D 631, + S32G_IMCR_CAN2_RXD =3D 632, + S32G_IMCR_CAN3_RXD =3D 633, + /* GMAC0 */ + S32G_IMCR_Ethernet_MDIO =3D 527, + S32G_IMCR_Ethernet_CRS =3D 526, + S32G_IMCR_Ethernet_COL =3D 525, + S32G_IMCR_Ethernet_RX_D0 =3D 531, + S32G_IMCR_Ethernet_RX_D1 =3D 532, + S32G_IMCR_Ethernet_RX_D2 =3D 533, + S32G_IMCR_Ethernet_RX_D3 =3D 534, + S32G_IMCR_Ethernet_RX_ER =3D 528, + S32G_IMCR_Ethernet_RX_CLK =3D 529, + S32G_IMCR_Ethernet_RX_DV =3D 530, + S32G_IMCR_Ethernet_TX_CLK =3D 538, + S32G_IMCR_Ethernet_REF_CLK =3D 535, + /* PFE EMAC 0 MII */ + /* PFE EMAC 1 MII */ + S32G_IMCR_PFE_EMAC_1_MDIO =3D 857, + S32G_IMCR_PFE_EMAC_1_CRS =3D 856, + S32G_IMCR_PFE_EMAC_1_COL =3D 855, + S32G_IMCR_PFE_EMAC_1_RX_D0 =3D 861, + S32G_IMCR_PFE_EMAC_1_RX_D1 =3D 862, + S32G_IMCR_PFE_EMAC_1_RX_D2 =3D 863, + S32G_IMCR_PFE_EMAC_1_RX_D3 =3D 864, + S32G_IMCR_PFE_EMAC_1_RX_ER =3D 860, + S32G_IMCR_PFE_EMAC_1_RX_CLK =3D 859, + S32G_IMCR_PFE_EMAC_1_RX_DV =3D 865, + S32G_IMCR_PFE_EMAC_1_TX_CLK =3D 866, + S32G_IMCR_PFE_EMAC_1_REF_CLK =3D 858, + /* PFE EMAC 2 MII */ + S32G_IMCR_PFE_EMAC_2_MDIO =3D 877, + S32G_IMCR_PFE_EMAC_2_CRS =3D 876, + S32G_IMCR_PFE_EMAC_2_COL =3D 875, + S32G_IMCR_PFE_EMAC_2_RX_D0 =3D 881, + S32G_IMCR_PFE_EMAC_2_RX_D1 =3D 882, + S32G_IMCR_PFE_EMAC_2_RX_D2 =3D 883, + S32G_IMCR_PFE_EMAC_2_RX_D3 =3D 884, + S32G_IMCR_PFE_EMAC_2_RX_ER =3D 880, + S32G_IMCR_PFE_EMAC_2_RX_CLK =3D 879, + S32G_IMCR_PFE_EMAC_2_RX_DV =3D 885, + S32G_IMCR_PFE_EMAC_2_TX_CLK =3D 886, + S32G_IMCR_PFE_EMAC_2_REF_CLK =3D 878, + + S32G_IMCR_FlexRay0_A_RX =3D 785, + S32G_IMCR_FlexRay0_B_RX =3D 786, + S32G_IMCR_FlexTimer0_CH0 =3D 655, + S32G_IMCR_FlexTimer1_CH0 =3D 665, + S32G_IMCR_FlexTimer0_CH1 =3D 656, + S32G_IMCR_FlexTimer1_CH1 =3D 666, + S32G_IMCR_FlexTimer0_CH2 =3D 657, + S32G_IMCR_FlexTimer1_CH2 =3D 667, + S32G_IMCR_FlexTimer0_CH3 =3D 658, + S32G_IMCR_FlexTimer1_CH3 =3D 668, + S32G_IMCR_FlexTimer0_CH4 =3D 659, + S32G_IMCR_FlexTimer1_CH4 =3D 669, + S32G_IMCR_FlexTimer0_CH5 =3D 660, + S32G_IMCR_FlexTimer1_CH5 =3D 670, + S32G_IMCR_FlexTimer0_EXTCLK =3D 661, + S32G_IMCR_FlexTimer1_EXTCLK =3D 671, + S32G_IMCR_I2C1_SCL =3D 717, + S32G_IMCR_I2C1_SDA =3D 718, + S32G_IMCR_I2C2_SCL =3D 719, + S32G_IMCR_I2C2_SDA =3D 720, + S32G_IMCR_I2C3_SCL =3D 721, + S32G_IMCR_I2C3_SDA =3D 722, + S32G_IMCR_I2C4_SCL =3D 723, + S32G_IMCR_I2C4_SDA =3D 724, + S32G_IMCR_LIN1_RX =3D 736, + S32G_IMCR_LIN2_RX =3D 737, + S32G_IMCR_DSPI0_PCS0 =3D 980, + S32G_IMCR_DSPI0_SCK =3D 981, + S32G_IMCR_DSPI0_SIN =3D 982, + S32G_IMCR_DSPI1_PCS0 =3D 985, + S32G_IMCR_DSPI1_SCK =3D 986, + S32G_IMCR_DSPI1_SIN =3D 987, + S32G_IMCR_DSPI2_PCS0 =3D 990, + S32G_IMCR_DSPI2_SCK =3D 991, + S32G_IMCR_DSPI2_SIN =3D 992, + S32G_IMCR_DSPI3_PCS0 =3D 995, + S32G_IMCR_DSPI3_SCK =3D 996, + S32G_IMCR_DSPI3_SIN =3D 997, + S32G_IMCR_DSPI4_PCS0 =3D 1000, + S32G_IMCR_DSPI4_SCK =3D 1001, + S32G_IMCR_DSPI4_SIN =3D 1002, + S32G_IMCR_DSPI5_PCS0 =3D 1005, + S32G_IMCR_DSPI5_SCK =3D 1006, + S32G_IMCR_DSPI5_SIN =3D 1007, + S32G_IMCR_LLCE_CAN0_RXD =3D 745, + S32G_IMCR_LLCE_CAN1_RXD =3D 746, + S32G_IMCR_LLCE_CAN2_RXD =3D 747, + S32G_IMCR_LLCE_CAN3_RXD =3D 748, + S32G_IMCR_LLCE_CAN4_RXD =3D 749, + S32G_IMCR_LLCE_CAN5_RXD =3D 750, + S32G_IMCR_LLCE_CAN6_RXD =3D 751, + S32G_IMCR_LLCE_CAN7_RXD =3D 752, + S32G_IMCR_LLCE_CAN8_RXD =3D 753, + S32G_IMCR_LLCE_CAN9_RXD =3D 754, + S32G_IMCR_LLCE_CAN10_RXD =3D 755, + S32G_IMCR_LLCE_CAN11_RXD =3D 756, + S32G_IMCR_LLCE_CAN12_RXD =3D 757, + S32G_IMCR_LLCE_CAN13_RXD =3D 758, + S32G_IMCR_LLCE_CAN14_RXD =3D 759, + S32G_IMCR_LLCE_CAN15_RXD =3D 760, + S32G_IMCR_USB_CLK =3D 895, + S32G_IMCR_USB_DATA0 =3D 896, + S32G_IMCR_USB_DATA1 =3D 897, + S32G_IMCR_USB_DATA2 =3D 898, + S32G_IMCR_USB_DATA3 =3D 899, + S32G_IMCR_USB_DATA4 =3D 900, + S32G_IMCR_USB_DATA5 =3D 901, + S32G_IMCR_USB_DATA6 =3D 902, + S32G_IMCR_USB_DATA7 =3D 903, + S32G_IMCR_USB_DIR =3D 904, + S32G_IMCR_USB_NXT =3D 905, + + S32G_IMCR_SIUL_EIRQ0 =3D 910, + S32G_IMCR_SIUL_EIRQ1 =3D 911, + S32G_IMCR_SIUL_EIRQ2 =3D 912, + S32G_IMCR_SIUL_EIRQ3 =3D 913, + S32G_IMCR_SIUL_EIRQ4 =3D 914, + S32G_IMCR_SIUL_EIRQ5 =3D 915, + S32G_IMCR_SIUL_EIRQ6 =3D 916, + S32G_IMCR_SIUL_EIRQ7 =3D 917, + S32G_IMCR_SIUL_EIRQ8 =3D 918, + S32G_IMCR_SIUL_EIRQ9 =3D 919, + S32G_IMCR_SIUL_EIRQ10 =3D 920, + S32G_IMCR_SIUL_EIRQ11 =3D 921, + S32G_IMCR_SIUL_EIRQ12 =3D 922, + S32G_IMCR_SIUL_EIRQ13 =3D 923, + S32G_IMCR_SIUL_EIRQ14 =3D 924, + S32G_IMCR_SIUL_EIRQ15 =3D 925, + S32G_IMCR_SIUL_EIRQ16 =3D 926, + S32G_IMCR_SIUL_EIRQ17 =3D 927, + S32G_IMCR_SIUL_EIRQ18 =3D 928, + S32G_IMCR_SIUL_EIRQ19 =3D 929, + S32G_IMCR_SIUL_EIRQ20 =3D 930, + S32G_IMCR_SIUL_EIRQ21 =3D 931, + S32G_IMCR_SIUL_EIRQ22 =3D 932, + S32G_IMCR_SIUL_EIRQ23 =3D 933, + S32G_IMCR_SIUL_EIRQ24 =3D 934, + S32G_IMCR_SIUL_EIRQ25 =3D 935, + S32G_IMCR_SIUL_EIRQ26 =3D 936, + S32G_IMCR_SIUL_EIRQ27 =3D 937, + S32G_IMCR_SIUL_EIRQ28 =3D 938, + S32G_IMCR_SIUL_EIRQ29 =3D 939, + S32G_IMCR_SIUL_EIRQ30 =3D 940, + S32G_IMCR_SIUL_EIRQ31 =3D 941, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] =3D { + + /* SIUL2_0 pins. */ + + S32_PINCTRL_PIN(S32G_MSCR_PA_00), + S32_PINCTRL_PIN(S32G_MSCR_PA_01), + S32_PINCTRL_PIN(S32G_MSCR_PA_02), + S32_PINCTRL_PIN(S32G_MSCR_PA_03), + S32_PINCTRL_PIN(S32G_MSCR_PA_04), + S32_PINCTRL_PIN(S32G_MSCR_PA_05), + S32_PINCTRL_PIN(S32G_MSCR_PA_06), + S32_PINCTRL_PIN(S32G_MSCR_PA_07), + S32_PINCTRL_PIN(S32G_MSCR_PA_08), + S32_PINCTRL_PIN(S32G_MSCR_PA_09), + S32_PINCTRL_PIN(S32G_MSCR_PA_10), + S32_PINCTRL_PIN(S32G_MSCR_PA_11), + S32_PINCTRL_PIN(S32G_MSCR_PA_12), + S32_PINCTRL_PIN(S32G_MSCR_PA_13), + S32_PINCTRL_PIN(S32G_MSCR_PA_14), + S32_PINCTRL_PIN(S32G_MSCR_PA_15), + S32_PINCTRL_PIN(S32G_MSCR_PB_00), + S32_PINCTRL_PIN(S32G_MSCR_PB_01), + S32_PINCTRL_PIN(S32G_MSCR_PB_02), + S32_PINCTRL_PIN(S32G_MSCR_PB_03), + S32_PINCTRL_PIN(S32G_MSCR_PB_04), + S32_PINCTRL_PIN(S32G_MSCR_PB_05), + S32_PINCTRL_PIN(S32G_MSCR_PB_06), + S32_PINCTRL_PIN(S32G_MSCR_PB_07), + S32_PINCTRL_PIN(S32G_MSCR_PB_08), + S32_PINCTRL_PIN(S32G_MSCR_PB_09), + S32_PINCTRL_PIN(S32G_MSCR_PB_10), + S32_PINCTRL_PIN(S32G_MSCR_PB_11), + S32_PINCTRL_PIN(S32G_MSCR_PB_12), + S32_PINCTRL_PIN(S32G_MSCR_PB_13), + S32_PINCTRL_PIN(S32G_MSCR_PB_14), + S32_PINCTRL_PIN(S32G_MSCR_PB_15), + S32_PINCTRL_PIN(S32G_MSCR_PC_00), + S32_PINCTRL_PIN(S32G_MSCR_PC_01), + S32_PINCTRL_PIN(S32G_MSCR_PC_02), + S32_PINCTRL_PIN(S32G_MSCR_PC_03), + S32_PINCTRL_PIN(S32G_MSCR_PC_04), + S32_PINCTRL_PIN(S32G_MSCR_PC_05), + S32_PINCTRL_PIN(S32G_MSCR_PC_06), + S32_PINCTRL_PIN(S32G_MSCR_PC_07), + S32_PINCTRL_PIN(S32G_MSCR_PC_08), + S32_PINCTRL_PIN(S32G_MSCR_PC_09), + S32_PINCTRL_PIN(S32G_MSCR_PC_10), + S32_PINCTRL_PIN(S32G_MSCR_PC_11), + S32_PINCTRL_PIN(S32G_MSCR_PC_12), + S32_PINCTRL_PIN(S32G_MSCR_PC_13), + S32_PINCTRL_PIN(S32G_MSCR_PC_14), + S32_PINCTRL_PIN(S32G_MSCR_PC_15), + S32_PINCTRL_PIN(S32G_MSCR_PD_00), + S32_PINCTRL_PIN(S32G_MSCR_PD_01), + S32_PINCTRL_PIN(S32G_MSCR_PD_02), + S32_PINCTRL_PIN(S32G_MSCR_PD_03), + S32_PINCTRL_PIN(S32G_MSCR_PD_04), + S32_PINCTRL_PIN(S32G_MSCR_PD_05), + S32_PINCTRL_PIN(S32G_MSCR_PD_06), + S32_PINCTRL_PIN(S32G_MSCR_PD_07), + S32_PINCTRL_PIN(S32G_MSCR_PD_08), + S32_PINCTRL_PIN(S32G_MSCR_PD_09), + S32_PINCTRL_PIN(S32G_MSCR_PD_10), + S32_PINCTRL_PIN(S32G_MSCR_PD_11), + S32_PINCTRL_PIN(S32G_MSCR_PD_12), + S32_PINCTRL_PIN(S32G_MSCR_PD_13), + S32_PINCTRL_PIN(S32G_MSCR_PD_14), + S32_PINCTRL_PIN(S32G_MSCR_PD_15), + S32_PINCTRL_PIN(S32G_MSCR_PE_00), + S32_PINCTRL_PIN(S32G_MSCR_PE_01), + S32_PINCTRL_PIN(S32G_MSCR_PE_02), + S32_PINCTRL_PIN(S32G_MSCR_PE_03), + S32_PINCTRL_PIN(S32G_MSCR_PE_04), + S32_PINCTRL_PIN(S32G_MSCR_PE_05), + S32_PINCTRL_PIN(S32G_MSCR_PE_06), + S32_PINCTRL_PIN(S32G_MSCR_PE_07), + S32_PINCTRL_PIN(S32G_MSCR_PE_08), + S32_PINCTRL_PIN(S32G_MSCR_PE_09), + S32_PINCTRL_PIN(S32G_MSCR_PE_10), + S32_PINCTRL_PIN(S32G_MSCR_PE_11), + S32_PINCTRL_PIN(S32G_MSCR_PE_12), + S32_PINCTRL_PIN(S32G_MSCR_PE_13), + S32_PINCTRL_PIN(S32G_MSCR_PE_14), + S32_PINCTRL_PIN(S32G_MSCR_PE_15), + S32_PINCTRL_PIN(S32G_MSCR_PF_00), + S32_PINCTRL_PIN(S32G_MSCR_PF_01), + S32_PINCTRL_PIN(S32G_MSCR_PF_02), + S32_PINCTRL_PIN(S32G_MSCR_PF_03), + S32_PINCTRL_PIN(S32G_MSCR_PF_04), + S32_PINCTRL_PIN(S32G_MSCR_PF_05), + S32_PINCTRL_PIN(S32G_MSCR_PF_06), + S32_PINCTRL_PIN(S32G_MSCR_PF_07), + S32_PINCTRL_PIN(S32G_MSCR_PF_08), + S32_PINCTRL_PIN(S32G_MSCR_PF_09), + S32_PINCTRL_PIN(S32G_MSCR_PF_10), + S32_PINCTRL_PIN(S32G_MSCR_PF_11), + S32_PINCTRL_PIN(S32G_MSCR_PF_12), + S32_PINCTRL_PIN(S32G_MSCR_PF_13), + S32_PINCTRL_PIN(S32G_MSCR_PF_14), + S32_PINCTRL_PIN(S32G_MSCR_PF_15), + S32_PINCTRL_PIN(S32G_MSCR_PG_00), + S32_PINCTRL_PIN(S32G_MSCR_PG_01), + S32_PINCTRL_PIN(S32G_MSCR_PG_02), + S32_PINCTRL_PIN(S32G_MSCR_PG_03), + S32_PINCTRL_PIN(S32G_MSCR_PG_04), + S32_PINCTRL_PIN(S32G_MSCR_PG_05), + + S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA0), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA1), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA2), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA3), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA4), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA5), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA6), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA7), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_DQS_A), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA0), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA1), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA2), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA3), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA4), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA5), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA6), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA7), + S32_PINCTRL_PIN(S32G_IMCR_QSPI_DQS_B), + S32_PINCTRL_PIN(S32G_IMCR_I2C0_SCL), + S32_PINCTRL_PIN(S32G_IMCR_I2C0_SDA), + S32_PINCTRL_PIN(S32G_IMCR_LIN0_RX), + S32_PINCTRL_PIN(S32G_IMCR_USDHC_CMD), + S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT0), + S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT1), + S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT2), + S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT3), + S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT4), + S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT5), + S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT6), + S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT7), + S32_PINCTRL_PIN(S32G_IMCR_USDHC_DQS), + S32_PINCTRL_PIN(S32G_IMCR_CAN0_RXD), + /* GMAC0 */ + S32_PINCTRL_PIN(S32G_IMCR_Ethernet_MDIO), + S32_PINCTRL_PIN(S32G_IMCR_Ethernet_CRS), + S32_PINCTRL_PIN(S32G_IMCR_Ethernet_COL), + S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_D0), + S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_D1), + S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_D2), + S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_D3), + S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_ER), + S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_CLK), + S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_DV), + S32_PINCTRL_PIN(S32G_IMCR_Ethernet_TX_CLK), + S32_PINCTRL_PIN(S32G_IMCR_Ethernet_REF_CLK), + + /* SIUL2_1 pins. */ + + S32_PINCTRL_PIN(S32G_MSCR_PH_00), + S32_PINCTRL_PIN(S32G_MSCR_PH_01), + S32_PINCTRL_PIN(S32G_MSCR_PH_02), + S32_PINCTRL_PIN(S32G_MSCR_PH_03), + S32_PINCTRL_PIN(S32G_MSCR_PH_04), + S32_PINCTRL_PIN(S32G_MSCR_PH_05), + S32_PINCTRL_PIN(S32G_MSCR_PH_06), + S32_PINCTRL_PIN(S32G_MSCR_PH_07), + S32_PINCTRL_PIN(S32G_MSCR_PH_08), + S32_PINCTRL_PIN(S32G_MSCR_PH_09), + S32_PINCTRL_PIN(S32G_MSCR_PH_10), + S32_PINCTRL_PIN(S32G_MSCR_PJ_00), + S32_PINCTRL_PIN(S32G_MSCR_PJ_01), + S32_PINCTRL_PIN(S32G_MSCR_PJ_02), + S32_PINCTRL_PIN(S32G_MSCR_PJ_03), + S32_PINCTRL_PIN(S32G_MSCR_PJ_04), + S32_PINCTRL_PIN(S32G_MSCR_PJ_05), + S32_PINCTRL_PIN(S32G_MSCR_PJ_06), + S32_PINCTRL_PIN(S32G_MSCR_PJ_07), + S32_PINCTRL_PIN(S32G_MSCR_PJ_08), + S32_PINCTRL_PIN(S32G_MSCR_PJ_09), + S32_PINCTRL_PIN(S32G_MSCR_PJ_10), + S32_PINCTRL_PIN(S32G_MSCR_PJ_11), + S32_PINCTRL_PIN(S32G_MSCR_PJ_12), + S32_PINCTRL_PIN(S32G_MSCR_PJ_13), + S32_PINCTRL_PIN(S32G_MSCR_PJ_14), + S32_PINCTRL_PIN(S32G_MSCR_PJ_15), + S32_PINCTRL_PIN(S32G_MSCR_PK_00), + S32_PINCTRL_PIN(S32G_MSCR_PK_01), + S32_PINCTRL_PIN(S32G_MSCR_PK_02), + S32_PINCTRL_PIN(S32G_MSCR_PK_03), + S32_PINCTRL_PIN(S32G_MSCR_PK_04), + S32_PINCTRL_PIN(S32G_MSCR_PK_05), + S32_PINCTRL_PIN(S32G_MSCR_PK_06), + S32_PINCTRL_PIN(S32G_MSCR_PK_07), + S32_PINCTRL_PIN(S32G_MSCR_PK_08), + S32_PINCTRL_PIN(S32G_MSCR_PK_09), + S32_PINCTRL_PIN(S32G_MSCR_PK_10), + S32_PINCTRL_PIN(S32G_MSCR_PK_11), + S32_PINCTRL_PIN(S32G_MSCR_PK_12), + S32_PINCTRL_PIN(S32G_MSCR_PK_13), + S32_PINCTRL_PIN(S32G_MSCR_PK_14), + S32_PINCTRL_PIN(S32G_MSCR_PK_15), + S32_PINCTRL_PIN(S32G_MSCR_PL_00), + S32_PINCTRL_PIN(S32G_MSCR_PL_01), + S32_PINCTRL_PIN(S32G_MSCR_PL_02), + S32_PINCTRL_PIN(S32G_MSCR_PL_03), + S32_PINCTRL_PIN(S32G_MSCR_PL_04), + S32_PINCTRL_PIN(S32G_MSCR_PL_05), + S32_PINCTRL_PIN(S32G_MSCR_PL_06), + S32_PINCTRL_PIN(S32G_MSCR_PL_07), + S32_PINCTRL_PIN(S32G_MSCR_PL_08), + S32_PINCTRL_PIN(S32G_MSCR_PL_09), + S32_PINCTRL_PIN(S32G_MSCR_PL_10), + S32_PINCTRL_PIN(S32G_MSCR_PL_11), + S32_PINCTRL_PIN(S32G_MSCR_PL_12), + S32_PINCTRL_PIN(S32G_MSCR_PL_13), + S32_PINCTRL_PIN(S32G_MSCR_PL_14), + + S32_PINCTRL_PIN(S32G_IMCR_FlexRay0_A_RX), + S32_PINCTRL_PIN(S32G_IMCR_FlexRay0_B_RX), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH0), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH0), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH1), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH1), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH2), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH2), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH3), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH3), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH4), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH4), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH5), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH5), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_EXTCLK), + S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_EXTCLK), + S32_PINCTRL_PIN(S32G_IMCR_I2C1_SCL), + S32_PINCTRL_PIN(S32G_IMCR_I2C1_SDA), + S32_PINCTRL_PIN(S32G_IMCR_I2C2_SCL), + S32_PINCTRL_PIN(S32G_IMCR_I2C2_SDA), + S32_PINCTRL_PIN(S32G_IMCR_I2C3_SCL), + S32_PINCTRL_PIN(S32G_IMCR_I2C3_SDA), + S32_PINCTRL_PIN(S32G_IMCR_I2C4_SCL), + S32_PINCTRL_PIN(S32G_IMCR_I2C4_SDA), + S32_PINCTRL_PIN(S32G_IMCR_LIN1_RX), + S32_PINCTRL_PIN(S32G_IMCR_LIN2_RX), + S32_PINCTRL_PIN(S32G_IMCR_DSPI0_PCS0), + S32_PINCTRL_PIN(S32G_IMCR_DSPI0_SCK), + S32_PINCTRL_PIN(S32G_IMCR_DSPI0_SIN), + S32_PINCTRL_PIN(S32G_IMCR_DSPI1_PCS0), + S32_PINCTRL_PIN(S32G_IMCR_DSPI1_SCK), + S32_PINCTRL_PIN(S32G_IMCR_DSPI1_SIN), + S32_PINCTRL_PIN(S32G_IMCR_DSPI2_PCS0), + S32_PINCTRL_PIN(S32G_IMCR_DSPI2_SCK), + S32_PINCTRL_PIN(S32G_IMCR_DSPI2_SIN), + S32_PINCTRL_PIN(S32G_IMCR_DSPI3_PCS0), + S32_PINCTRL_PIN(S32G_IMCR_DSPI3_SCK), + S32_PINCTRL_PIN(S32G_IMCR_DSPI3_SIN), + S32_PINCTRL_PIN(S32G_IMCR_DSPI4_PCS0), + S32_PINCTRL_PIN(S32G_IMCR_DSPI4_SCK), + S32_PINCTRL_PIN(S32G_IMCR_DSPI4_SIN), + S32_PINCTRL_PIN(S32G_IMCR_DSPI5_PCS0), + S32_PINCTRL_PIN(S32G_IMCR_DSPI5_SCK), + S32_PINCTRL_PIN(S32G_IMCR_DSPI5_SIN), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN0_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN1_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN2_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN3_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN4_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN5_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN6_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN7_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN8_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN9_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN10_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN11_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN12_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN13_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN14_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN15_RXD), + S32_PINCTRL_PIN(S32G_IMCR_CAN1_RXD), + S32_PINCTRL_PIN(S32G_IMCR_CAN2_RXD), + S32_PINCTRL_PIN(S32G_IMCR_CAN3_RXD), + S32_PINCTRL_PIN(S32G_IMCR_USB_CLK), + S32_PINCTRL_PIN(S32G_IMCR_USB_DATA0), + S32_PINCTRL_PIN(S32G_IMCR_USB_DATA1), + S32_PINCTRL_PIN(S32G_IMCR_USB_DATA2), + S32_PINCTRL_PIN(S32G_IMCR_USB_DATA3), + S32_PINCTRL_PIN(S32G_IMCR_USB_DATA4), + S32_PINCTRL_PIN(S32G_IMCR_USB_DATA5), + S32_PINCTRL_PIN(S32G_IMCR_USB_DATA6), + S32_PINCTRL_PIN(S32G_IMCR_USB_DATA7), + S32_PINCTRL_PIN(S32G_IMCR_USB_DIR), + S32_PINCTRL_PIN(S32G_IMCR_USB_NXT), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_MDIO), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_CRS), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_COL), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_D0), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_D1), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_D2), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_D3), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_ER), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_CLK), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_DV), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_TX_CLK), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_REF_CLK), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_MDIO), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_CRS), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_COL), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_D0), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_D1), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_D2), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_D3), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_ER), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_CLK), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_DV), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_TX_CLK), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_REF_CLK), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ0), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ1), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ2), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ3), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ4), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ5), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ6), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ7), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ8), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ9), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ10), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ11), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ12), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ13), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ14), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ15), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ16), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ17), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ18), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ19), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ20), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ21), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ22), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ23), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ24), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ25), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ26), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ27), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ28), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ29), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ30), + S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ31), +}; + +static const struct s32_pin_range s32_pin_ranges_siul2[] =3D { + /* MSCR pin ID ranges */ + S32_PIN_RANGE(0, 101), + S32_PIN_RANGE(112, 122), + S32_PIN_RANGE(144, 190), + /* IMCR pin ID ranges */ + S32_PIN_RANGE(512, 595), + S32_PIN_RANGE(631, 909), + S32_PIN_RANGE(942, 1007), +}; + +static struct s32_pinctrl_soc_info s32_pinctrl_info =3D { + .pins =3D s32_pinctrl_pads_siul2, + .npins =3D ARRAY_SIZE(s32_pinctrl_pads_siul2), + .mem_pin_ranges =3D s32_pin_ranges_siul2, + .mem_regions =3D ARRAY_SIZE(s32_pin_ranges_siul2), +}; + +static const struct of_device_id s32_pinctrl_of_match[] =3D { + { + + .compatible =3D "nxp,s32g2-siul2-pinctrl", + .data =3D (void *) &s32_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, s32_pinctrl_of_match); + +static int s32g_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id =3D + of_match_device(s32_pinctrl_of_match, &pdev->dev); + + if (!of_id) + return -ENODEV; + + return s32_pinctrl_probe + (pdev, (struct s32_pinctrl_soc_info *) of_id->data); +} + +static const struct dev_pm_ops s32g_pinctrl_pm_ops =3D { + SET_LATE_SYSTEM_SLEEP_PM_OPS(s32_pinctrl_suspend, + s32_pinctrl_resume) +}; + +static struct platform_driver s32g_pinctrl_driver =3D { + .driver =3D { + .name =3D "s32g-siul2-pinctrl", + .owner =3D THIS_MODULE, + .of_match_table =3D s32_pinctrl_of_match, + .pm =3D &s32g_pinctrl_pm_ops, + .suppress_bind_attrs =3D true, + }, + .probe =3D s32g_pinctrl_probe, +}; + +builtin_platform_driver(s32g_pinctrl_driver); + +MODULE_AUTHOR("Matthew Nunez "); +MODULE_DESCRIPTION("NXP S32G pinctrl driver"); +MODULE_LICENSE("GPL"); --=20 2.37.3 From nobody Sun Sep 14 20:44:25 2025 Return-Path: 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Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ik+r5uFNC8q9lclorAaTlrutQpKCbeIyr5dJfFZp4G06677JqXHDwFEvkZCuerN2 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8829 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add myself as a maintainer and add NXP S32 Linux Team as a review group for S32 pinctrl patches. Signed-off-by: Chester Lin --- Changes in v4: - The initial version in this series. MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 42fc47c6edfd..9c9850194891 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16551,6 +16551,14 @@ S: Supported F: drivers/gpio/gpio-sama5d2-piobu.c F: drivers/pinctrl/pinctrl-at91* =20 +PIN CONTROLLER - NXP S32 +M: Chester Lin +R: NXP S32 Linux Team +L: linux-gpio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/nxp,s32* +F: drivers/pinctrl/nxp/ + PIN CONTROLLER - QUALCOMM M: Bjorn Andersson L: linux-arm-msm@vger.kernel.org --=20 2.37.3