From nobody Sat Sep 21 08:47:01 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F0D0C32793 for ; Wed, 18 Jan 2023 10:14:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230170AbjARKOD (ORCPT ); Wed, 18 Jan 2023 05:14:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229934AbjARKL1 (ORCPT ); Wed, 18 Jan 2023 05:11:27 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 488169AAA8; Wed, 18 Jan 2023 01:18:41 -0800 (PST) X-UUID: 16a63abc971111eda06fc9ecc4dadd91-20230118 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=oh4oRdNlHNgbza+c+8Rhh1Wn/lUdxGCskSZ1itRi5RQ=; b=EyZZgVrifTbf2rxlYyXNkQ44Sy2K5B5EUL9FE2EA9YNl489ptObRLMAbUNRuqHgRWD4taL5SK4vEVZOZK4Nw2Xhe4L2AWFKMpnkxOSWGLF1F37YhA5BvL0liQVVX9/rrDeIGlliX2NftzFpzqIbzyhcVrO+h5olvnuVu7o3rhgI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:5415e641-82df-48e7-9455-bda8afcca49f,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.18,REQID:5415e641-82df-48e7-9455-bda8afcca49f,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:3ca2d6b,CLOUDID:824b0055-dd49-462e-a4be-2143a3ddc739,B ulkID:23011817183745DS3BNO,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0 X-CID-BVR: 0,NGT X-UUID: 16a63abc971111eda06fc9ecc4dadd91-20230118 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1609305406; Wed, 18 Jan 2023 17:18:36 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 18 Jan 2023 17:18:35 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 18 Jan 2023 17:18:35 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Stephen Boyd , AngeloGioacchino Del Regno , CC: , , , , , , Allen-KH Cheng Subject: [PATCH v2 7/9] arm64: dts: mediatek: mt8186: Add DPI node Date: Wed, 18 Jan 2023 17:18:27 +0800 Message-ID: <20230118091829.755-8-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230118091829.755-1-allen-kh.cheng@mediatek.com> References: <20230118091829.755-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DPI node for MT8186 SoC. Signed-off-by: Allen-KH Cheng Tested-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index c52f9be1e750..45b9d6777929 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1230,6 +1230,23 @@ power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; }; =20 + dpi: dpi@1400a000 { + compatible =3D "mediatek,mt8186-dpi"; + reg =3D <0 0x1400a000 0 0x1000>; + clocks =3D <&topckgen CLK_TOP_DPI>, + <&mmsys CLK_MM_DISP_DPI>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names =3D "pixel", "engine", "pll"; + assigned-clocks =3D <&topckgen CLK_TOP_DPI>; + assigned-clock-parents =3D <&topckgen CLK_TOP_TVDPLL_D2>; + interrupts =3D ; + status =3D "disabled"; + + port { + dpi_out: endpoint { }; + }; + }; + dsi0: dsi@14013000 { compatible =3D "mediatek,mt8186-dsi"; reg =3D <0 0x14013000 0 0x1000>; --=20 2.18.0