From nobody Sat Sep 21 08:18:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BBFDC004D4 for ; Wed, 18 Jan 2023 10:14:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230225AbjARKO3 (ORCPT ); Wed, 18 Jan 2023 05:14:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230117AbjARKL1 (ORCPT ); Wed, 18 Jan 2023 05:11:27 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49C0B9577D; Wed, 18 Jan 2023 01:18:42 -0800 (PST) X-UUID: 170fc892971111eda06fc9ecc4dadd91-20230118 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=v8dqe35PIjJM4g0zIru+4r9kftuAYVrE3lGfLmI9emw=; b=WOI3LnKRwLDZhGsLwxLcDmeEWWVAe3gvxEdWLW/4nDoZl4kxwcAvdOlw4zuU/5XrQnWFrzrbelxmyudMUUi/3h78lUH8M0ZcHiKjN8FnnltgYTs20u/O49+f/0BDef22xNnyXILashJkHX5BcpXS/8fa7jxefm1MHESfNqQyPQg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:7ea8f6f1-5e2b-49ab-8e40-50f0107fa943,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:3ca2d6b,CLOUDID:c8379b8c-8530-4eff-9f77-222cf6e2895b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0 X-UUID: 170fc892971111eda06fc9ecc4dadd91-20230118 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 231727774; Wed, 18 Jan 2023 17:18:37 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 18 Jan 2023 17:18:36 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 18 Jan 2023 17:18:36 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Stephen Boyd , AngeloGioacchino Del Regno , CC: , , , , , , Allen-KH Cheng Subject: [PATCH v2 9/9] arm64: dts: mediatek: mt8186: Add display nodes Date: Wed, 18 Jan 2023 17:18:29 +0800 Message-ID: <20230118091829.755-10-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230118091829.755-1-allen-kh.cheng@mediatek.com> References: <20230118091829.755-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add display nodes and GCE info for MT8186 SoC. Also, add GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which is required for operating the display. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 135 +++++++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 45b9d6777929..90d1b631bc8f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -5,6 +5,7 @@ */ /dts-v1/; #include +#include #include #include #include @@ -19,6 +20,13 @@ #address-cells =3D <2>; #size-cells =3D <2>; =20 + aliases { + ovl =3D &ovl; + ovl_2l=3D &ovl_2l; + rdma0 =3D &rdma0; + rdma1 =3D &rdma1; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -632,6 +640,15 @@ clocks =3D <&clk13m>; }; =20 + gce: mailbox@1022c000 { + compatible =3D "mediatek,mt8186-gce"; + reg =3D <0 0X1022c000 0 0x4000>; + clocks =3D <&infracfg_ao CLK_INFRA_AO_GCE>; + clock-names =3D "gce"; + interrupts =3D ; + #mbox-cells =3D <2>; + }; + scp: scp@10500000 { compatible =3D "mediatek,mt8186-scp"; reg =3D <0 0x10500000 0 0x40000>, @@ -1197,6 +1214,20 @@ reg =3D <0 0x14000000 0 0x1000>; #clock-cells =3D <1>; #reset-cells =3D <1>; + mboxes =3D <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + mutex: mutex@14001000 { + compatible =3D "mediatek,mt8186-disp-mutex"; + reg =3D <0 0x14001000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_MUTEX0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; }; =20 smi_common: smi@14002000 { @@ -1230,6 +1261,49 @@ power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; }; =20 + ovl: ovl@14005000 { + compatible =3D "mediatek,mt8186-disp-ovl", + "mediatek,mt8192-disp-ovl"; + reg =3D <0 0x14005000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_OVL0>; + interrupts =3D ; + iommus =3D <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + ovl_2l: ovl@14006000 { + compatible =3D "mediatek,mt8186-disp-ovl-2l", + "mediatek,mt8192-disp-ovl-2l"; + reg =3D <0 0x14006000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_OVL0_2L>; + interrupts =3D ; + iommus =3D <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + rdma0: rdma@14007000 { + compatible =3D "mediatek,mt8186-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x14007000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; + interrupts =3D ; + iommus =3D <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + color: color@14009000 { + compatible =3D "mediatek,mt8186-disp-color", + "mediatek,mt8173-disp-color"; + reg =3D <0 0x14009000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_COLOR0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dpi: dpi@1400a000 { compatible =3D "mediatek,mt8186-dpi"; reg =3D <0 0x1400a000 0 0x1000>; @@ -1247,6 +1321,56 @@ }; }; =20 + ccorr: ccorr@1400b000 { + compatible =3D "mediatek,mt8186-disp-ccorr", + "mediatek,mt8192-disp-ccorr"; + reg =3D <0 0x1400b000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_CCORR0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + aal: aal@1400c000 { + compatible =3D "mediatek,mt8186-disp-aal", + "mediatek,mt8183-disp-aal"; + reg =3D <0 0x1400c000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_AAL0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + gamma: gamma@1400d000 { + compatible =3D "mediatek,mt8186-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg =3D <0 0x1400d000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_GAMMA0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + postmask: postmask@1400e000 { + compatible =3D "mediatek,mt8186-disp-postmask", + "mediatek,mt8192-disp-postmask"; + reg =3D <0 0x1400e000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_POSTMASK0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + dither: dither@1400f000 { + compatible =3D "mediatek,mt8186-disp-dither", + "mediatek,mt8183-disp-dither"; + reg =3D <0 0x1400f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_DITHER0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dsi0: dsi@14013000 { compatible =3D "mediatek,mt8186-dsi"; reg =3D <0 0x14013000 0 0x1000>; @@ -1280,6 +1404,17 @@ #iommu-cells =3D <1>; }; =20 + rdma1: rdma@1401f000 { + compatible =3D "mediatek,mt8186-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x1401f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA1>; + interrupts =3D ; + iommus =3D <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0xf000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + wpesys: clock-controller@14020000 { compatible =3D "mediatek,mt8186-wpesys"; reg =3D <0 0x14020000 0 0x1000>; --=20 2.18.0