From nobody Sat Sep 21 07:22:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A5FCC00A5A for ; Wed, 18 Jan 2023 03:21:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229683AbjARDVh (ORCPT ); Tue, 17 Jan 2023 22:21:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229482AbjARDVd (ORCPT ); Tue, 17 Jan 2023 22:21:33 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2F7F4FCFD; Tue, 17 Jan 2023 19:21:29 -0800 (PST) X-UUID: 2f9834a896df11eda06fc9ecc4dadd91-20230118 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=xQVMUD7okQLHVM5bRj5IZzkMbKVUxbpiSB0vJMJlbZA=; b=e4d54YS/YkTw+L2mPsyWR5AxgBR917aUOPB3wtVEYxpswgUFbopPCrpX9okBQ3TqpT9fwafO0Y1/iEsOVF+wA3JPtLrVsZnvkakMp13LL0XqDcIt0lPZxAJRFYY+kpnMlcIOc/iBOjo+JCQcfPyDKQ/efohoFKhe2TJvX0MgfWM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:c020b425-29ec-4bf1-80dd-a8e1c69949d9,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.18,REQID:c020b425-29ec-4bf1-80dd-a8e1c69949d9,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:3ca2d6b,CLOUDID:032820f6-ff42-4fb0-b929-626456a83c14,B ulkID:2301181121245EBAODC3,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0 X-CID-BVR: 0 X-UUID: 2f9834a896df11eda06fc9ecc4dadd91-20230118 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1404739570; Wed, 18 Jan 2023 11:21:23 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 18 Jan 2023 11:21:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 18 Jan 2023 11:21:23 +0800 From: Moudy Ho To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Michael Turquette , Stephen Boyd CC: , , , , , , Moudy Ho Subject: [PATCH v6 3/6] arm64: dts: mediatek: mt8195: add MUTEX configuration for VPPSYS Date: Wed, 18 Jan 2023 11:21:19 +0800 Message-ID: <20230118032122.29956-4-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230118032122.29956-1-moudy.ho@mediatek.com> References: <20230118032122.29956-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In MT8195, the MMSYS has two Video Processor Pipepline Subsystems named VPPSYS0 and VPPSYS1, each with specific MUTEX to control Start of Frame(SOF) and End of Frame (EOF) signals. Before working with them, the addresses, interrupts, clocks and power domains need to be set up in dts. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 8bc38700b945..206dd534c3f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1706,6 +1706,15 @@ #clock-cells =3D <1>; }; =20 + mutex@1400f000 { + compatible =3D "mediatek,mt8195-vpp-mutex"; + reg =3D <0 0x1400f000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MUTEX>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { compatible =3D "mediatek,mt8195-smi-sub-common"; reg =3D <0 0x14010000 0 0x1000>; @@ -1811,6 +1820,15 @@ #clock-cells =3D <1>; }; =20 + mutex@14f01000 { + compatible =3D "mediatek,mt8195-vpp-mutex"; + reg =3D <0 0x14f01000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_DISP_MUTEX>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + larb5: larb@14f02000 { compatible =3D "mediatek,mt8195-smi-larb"; reg =3D <0 0x14f02000 0 0x1000>; --=20 2.18.0