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Add relevant DT include definitions as well. Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sa8775p-gcc.yaml | 79 +++++ include/dt-bindings/clock/qcom,sa8775p-gcc.h | 320 ++++++++++++++++++ 2 files changed, 399 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-gc= c.yaml create mode 100644 include/dt-bindings/clock/qcom,sa8775p-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml = b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml new file mode 100644 index 000000000000..dae65ebc5557 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on sa8775p + +maintainers: + - Bartosz Golaszewski + +description: | + Qualcomm global clock control module provides the clocks, resets and + power domains on sa8775p. + + See also:: include/dt-bindings/clock/qcom,sa8775p-gcc.h + +properties: + compatible: + const: qcom,sa8775p-gcc + + clocks: + items: + - description: XO reference clock + - description: Sleep clock + - description: UFS memory first RX symbol clock + - description: UFS memory second RX symbol clock + - description: UFS memory first TX symbol clock + - description: UFS card first RX symbol clock + - description: UFS card second RX symbol clock + - description: UFS card first TX symbol clock + - description: Primary USB3 PHY wrapper pipe clock + - description: Secondary USB3 PHY wrapper pipe clock + - description: PCIe 0 pipe clock + - description: PCIe 1 pipe clock + - description: PCIe PHY clock + - description: First EMAC controller reference clock + - description: Second EMAC controller reference clock + + protected-clocks: + maxItems: 240 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + gcc: clock-controller@100000 { + compatible =3D "qcom,sa8775p-gcc"; + reg =3D <0x100000 0xc7018>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&ufs_card_rx_symbol_0_clk>, + <&ufs_card_rx_symbol_1_clk>, + <&ufs_card_tx_symbol_0_clk>, + <&usb_0_ssphy>, + <&usb_1_ssphy>, + <&pcie_0_pipe_clk>, + <&pcie_1_pipe_clk>, + <&pcie_phy_pipe_clk>, + <&rxc0_ref_clk>, + <&rxc1_ref_clk>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sa8775p-gcc.h b/include/dt-bind= ings/clock/qcom,sa8775p-gcc.h new file mode 100644 index 000000000000..01f54234963d --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-gcc.h @@ -0,0 +1,320 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H + +/* GCC clocks */ +#define GCC_GPLL0 0 +#define GCC_GPLL0_OUT_EVEN 1 +#define GCC_GPLL1 2 +#define GCC_GPLL4 3 +#define GCC_GPLL5 4 +#define GCC_GPLL7 5 +#define GCC_GPLL9 6 +#define GCC_AGGRE_NOC_QUPV3_AXI_CLK 7 +#define GCC_AGGRE_UFS_CARD_AXI_CLK 8 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 9 +#define GCC_AGGRE_USB2_PRIM_AXI_CLK 10 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 11 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 12 +#define GCC_AHB2PHY0_CLK 13 +#define GCC_AHB2PHY2_CLK 14 +#define GCC_AHB2PHY3_CLK 15 +#define GCC_BOOT_ROM_AHB_CLK 16 +#define GCC_CAMERA_AHB_CLK 17 +#define GCC_CAMERA_HF_AXI_CLK 18 +#define GCC_CAMERA_SF_AXI_CLK 19 +#define GCC_CAMERA_THROTTLE_XO_CLK 20 +#define GCC_CAMERA_XO_CLK 21 +#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 22 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 24 +#define GCC_DDRSS_GPU_AXI_CLK 25 +#define GCC_DISP1_AHB_CLK 26 +#define GCC_DISP1_HF_AXI_CLK 27 +#define GCC_DISP1_XO_CLK 28 +#define GCC_DISP_AHB_CLK 29 +#define GCC_DISP_HF_AXI_CLK 30 +#define GCC_DISP_XO_CLK 31 +#define GCC_EDP_REF_CLKREF_EN 32 +#define GCC_EMAC0_AXI_CLK 33 +#define GCC_EMAC0_PHY_AUX_CLK 34 +#define GCC_EMAC0_PHY_AUX_CLK_SRC 35 +#define GCC_EMAC0_PTP_CLK 36 +#define GCC_EMAC0_PTP_CLK_SRC 37 +#define GCC_EMAC0_RGMII_CLK 38 +#define GCC_EMAC0_RGMII_CLK_SRC 39 +#define GCC_EMAC0_SLV_AHB_CLK 40 +#define GCC_EMAC1_AXI_CLK 41 +#define GCC_EMAC1_PHY_AUX_CLK 42 +#define GCC_EMAC1_PHY_AUX_CLK_SRC 43 +#define GCC_EMAC1_PTP_CLK 44 +#define GCC_EMAC1_PTP_CLK_SRC 45 +#define GCC_EMAC1_RGMII_CLK 46 +#define GCC_EMAC1_RGMII_CLK_SRC 47 +#define GCC_EMAC1_SLV_AHB_CLK 48 +#define GCC_GP1_CLK 49 +#define GCC_GP1_CLK_SRC 50 +#define GCC_GP2_CLK 51 +#define GCC_GP2_CLK_SRC 52 +#define GCC_GP3_CLK 53 +#define GCC_GP3_CLK_SRC 54 +#define GCC_GP4_CLK 55 +#define GCC_GP4_CLK_SRC 56 +#define GCC_GP5_CLK 57 +#define GCC_GP5_CLK_SRC 58 +#define GCC_GPU_CFG_AHB_CLK 59 +#define GCC_GPU_GPLL0_CLK_SRC 60 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 61 +#define GCC_GPU_MEMNOC_GFX_CLK 62 +#define GCC_GPU_SNOC_DVM_GFX_CLK 63 +#define GCC_GPU_TCU_THROTTLE_AHB_CLK 64 +#define GCC_GPU_TCU_THROTTLE_CLK 65 +#define GCC_PCIE_0_AUX_CLK 66 +#define GCC_PCIE_0_AUX_CLK_SRC 67 +#define GCC_PCIE_0_CFG_AHB_CLK 68 +#define GCC_PCIE_0_MSTR_AXI_CLK 69 +#define GCC_PCIE_0_PHY_AUX_CLK 70 +#define GCC_PCIE_0_PHY_AUX_CLK_SRC 71 +#define GCC_PCIE_0_PHY_RCHNG_CLK 72 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 73 +#define GCC_PCIE_0_PIPE_CLK 74 +#define GCC_PCIE_0_PIPE_CLK_SRC 75 +#define GCC_PCIE_0_PIPE_DIV_CLK_SRC 76 +#define GCC_PCIE_0_PIPEDIV2_CLK 77 +#define GCC_PCIE_0_SLV_AXI_CLK 78 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 79 +#define GCC_PCIE_1_AUX_CLK 80 +#define GCC_PCIE_1_AUX_CLK_SRC 81 +#define GCC_PCIE_1_CFG_AHB_CLK 82 +#define GCC_PCIE_1_MSTR_AXI_CLK 83 +#define GCC_PCIE_1_PHY_AUX_CLK 84 +#define GCC_PCIE_1_PHY_AUX_CLK_SRC 85 +#define GCC_PCIE_1_PHY_RCHNG_CLK 86 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 87 +#define GCC_PCIE_1_PIPE_CLK 88 +#define GCC_PCIE_1_PIPE_CLK_SRC 89 +#define GCC_PCIE_1_PIPE_DIV_CLK_SRC 90 +#define GCC_PCIE_1_PIPEDIV2_CLK 91 +#define GCC_PCIE_1_SLV_AXI_CLK 92 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 93 +#define GCC_PCIE_CLKREF_EN 94 +#define GCC_PCIE_THROTTLE_CFG_CLK 95 +#define GCC_PDM2_CLK 96 +#define GCC_PDM2_CLK_SRC 97 +#define GCC_PDM_AHB_CLK 98 +#define GCC_PDM_XO4_CLK 99 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 100 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 101 +#define GCC_QMIP_DISP1_AHB_CLK 102 +#define GCC_QMIP_DISP1_ROT_AHB_CLK 103 +#define GCC_QMIP_DISP_AHB_CLK 104 +#define GCC_QMIP_DISP_ROT_AHB_CLK 105 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 106 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 107 +#define GCC_QMIP_VIDEO_VCPU_AHB_CLK 108 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 109 +#define GCC_QUPV3_WRAP0_CORE_CLK 110 +#define GCC_QUPV3_WRAP0_S0_CLK 111 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 112 +#define GCC_QUPV3_WRAP0_S1_CLK 113 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 114 +#define GCC_QUPV3_WRAP0_S2_CLK 115 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 116 +#define GCC_QUPV3_WRAP0_S3_CLK 117 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 118 +#define GCC_QUPV3_WRAP0_S4_CLK 119 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 120 +#define GCC_QUPV3_WRAP0_S5_CLK 121 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 122 +#define GCC_QUPV3_WRAP0_S6_CLK 123 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 124 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 125 +#define GCC_QUPV3_WRAP1_CORE_CLK 126 +#define GCC_QUPV3_WRAP1_S0_CLK 127 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 128 +#define GCC_QUPV3_WRAP1_S1_CLK 129 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 130 +#define GCC_QUPV3_WRAP1_S2_CLK 131 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 132 +#define GCC_QUPV3_WRAP1_S3_CLK 133 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 134 +#define GCC_QUPV3_WRAP1_S4_CLK 135 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 136 +#define GCC_QUPV3_WRAP1_S5_CLK 137 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 138 +#define GCC_QUPV3_WRAP1_S6_CLK 139 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 140 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 141 +#define GCC_QUPV3_WRAP2_CORE_CLK 142 +#define GCC_QUPV3_WRAP2_S0_CLK 143 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 144 +#define GCC_QUPV3_WRAP2_S1_CLK 145 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 146 +#define GCC_QUPV3_WRAP2_S2_CLK 147 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 148 +#define GCC_QUPV3_WRAP2_S3_CLK 149 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 150 +#define GCC_QUPV3_WRAP2_S4_CLK 151 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 152 +#define GCC_QUPV3_WRAP2_S5_CLK 153 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 154 +#define GCC_QUPV3_WRAP2_S6_CLK 155 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 156 +#define GCC_QUPV3_WRAP3_CORE_2X_CLK 157 +#define GCC_QUPV3_WRAP3_CORE_CLK 158 +#define GCC_QUPV3_WRAP3_QSPI_CLK 159 +#define GCC_QUPV3_WRAP3_S0_CLK 160 +#define GCC_QUPV3_WRAP3_S0_CLK_SRC 161 +#define GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC 162 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 163 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 164 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 165 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 166 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 167 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 168 +#define GCC_QUPV3_WRAP_3_M_AHB_CLK 169 +#define GCC_QUPV3_WRAP_3_S_AHB_CLK 170 +#define GCC_SDCC1_AHB_CLK 171 +#define GCC_SDCC1_APPS_CLK 172 +#define GCC_SDCC1_APPS_CLK_SRC 173 +#define GCC_SDCC1_ICE_CORE_CLK 174 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 175 +#define GCC_SGMI_CLKREF_EN 176 +#define GCC_TSCSS_AHB_CLK 177 +#define GCC_TSCSS_CNTR_CLK_SRC 178 +#define GCC_TSCSS_ETU_CLK 179 +#define GCC_TSCSS_GLOBAL_CNTR_CLK 180 +#define GCC_UFS_CARD_AHB_CLK 181 +#define GCC_UFS_CARD_AXI_CLK 182 +#define GCC_UFS_CARD_AXI_CLK_SRC 183 +#define GCC_UFS_CARD_ICE_CORE_CLK 184 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 185 +#define GCC_UFS_CARD_PHY_AUX_CLK 186 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 187 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 188 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 189 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 190 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 191 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 192 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 193 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 194 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 195 +#define GCC_UFS_PHY_AHB_CLK 196 +#define GCC_UFS_PHY_AXI_CLK 197 +#define GCC_UFS_PHY_AXI_CLK_SRC 198 +#define GCC_UFS_PHY_ICE_CORE_CLK 199 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 200 +#define GCC_UFS_PHY_PHY_AUX_CLK 201 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 202 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 203 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 204 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 205 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 206 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 207 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 208 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 209 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 210 +#define GCC_USB20_MASTER_CLK 211 +#define GCC_USB20_MASTER_CLK_SRC 212 +#define GCC_USB20_MOCK_UTMI_CLK 213 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 214 +#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 215 +#define GCC_USB20_SLEEP_CLK 216 +#define GCC_USB30_PRIM_MASTER_CLK 217 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 218 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 219 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 220 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 221 +#define GCC_USB30_PRIM_SLEEP_CLK 222 +#define GCC_USB30_SEC_MASTER_CLK 223 +#define GCC_USB30_SEC_MASTER_CLK_SRC 224 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 225 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 226 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 227 +#define GCC_USB30_SEC_SLEEP_CLK 228 +#define GCC_USB3_PRIM_PHY_AUX_CLK 229 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 230 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 231 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 232 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 233 +#define GCC_USB3_SEC_PHY_AUX_CLK 234 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 235 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 236 +#define GCC_USB3_SEC_PHY_PIPE_CLK 237 +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 238 +#define GCC_USB_CLKREF_EN 239 +#define GCC_VIDEO_AHB_CLK 240 +#define GCC_VIDEO_AXI0_CLK 241 +#define GCC_VIDEO_AXI1_CLK 242 +#define GCC_VIDEO_XO_CLK 243 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 244 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 245 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 246 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 247 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 248 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY1_BCR 1 +#define GCC_DISPLAY_BCR 2 +#define GCC_EMAC0_BCR 3 +#define GCC_EMAC1_BCR 4 +#define GCC_GPU_BCR 5 +#define GCC_MMSS_BCR 6 +#define GCC_PCIE_0_BCR 7 +#define GCC_PCIE_0_LINK_DOWN_BCR 8 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 9 +#define GCC_PCIE_0_PHY_BCR 10 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 11 +#define GCC_PCIE_1_BCR 12 +#define GCC_PCIE_1_LINK_DOWN_BCR 13 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 14 +#define GCC_PCIE_1_PHY_BCR 15 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 16 +#define GCC_PDM_BCR 17 +#define GCC_QUPV3_WRAPPER_0_BCR 18 +#define GCC_QUPV3_WRAPPER_1_BCR 19 +#define GCC_QUPV3_WRAPPER_2_BCR 20 +#define GCC_QUPV3_WRAPPER_3_BCR 21 +#define GCC_SDCC1_BCR 22 +#define GCC_TSCSS_BCR 23 +#define GCC_UFS_CARD_BCR 24 +#define GCC_UFS_PHY_BCR 25 +#define GCC_USB20_PRIM_BCR 26 +#define GCC_USB2_PHY_PRIM_BCR 27 +#define GCC_USB2_PHY_SEC_BCR 28 +#define GCC_USB30_PRIM_BCR 29 +#define GCC_USB30_SEC_BCR 30 +#define GCC_USB3_DP_PHY_PRIM_BCR 31 +#define GCC_USB3_DP_PHY_SEC_BCR 32 +#define GCC_USB3_PHY_PRIM_BCR 33 +#define GCC_USB3_PHY_SEC_BCR 34 +#define GCC_USB3_PHY_TERT_BCR 35 +#define GCC_USB3_UNIPHY_MP0_BCR 36 +#define GCC_USB3_UNIPHY_MP1_BCR 37 +#define GCC_USB3PHY_PHY_PRIM_BCR 38 +#define GCC_USB3PHY_PHY_SEC_BCR 39 +#define GCC_USB3UNIPHY_PHY_MP0_BCR 40 +#define GCC_USB3UNIPHY_PHY_MP1_BCR 41 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42 +#define GCC_VIDEO_BCR 43 +#define GCC_VIDEO_AXI0_CLK_ARES 44 +#define GCC_VIDEO_AXI1_CLK_ARES 45 + +/* GCC GDSCs */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 +#define UFS_CARD_GDSC 2 +#define UFS_PHY_GDSC 3 +#define USB20_PRIM_GDSC 4 +#define USB30_PRIM_GDSC 5 +#define USB30_SEC_GDSC 6 +#define EMAC0_GDSC 7 +#define EMAC1_GDSC 8 + +#endif /* _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H */ --=20 2.37.2 From nobody Sun Sep 14 22:36:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F650C678D7 for ; Tue, 17 Jan 2023 18:41:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235040AbjAQSji (ORCPT ); Tue, 17 Jan 2023 13:39:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232686AbjAQSdA (ORCPT ); Tue, 17 Jan 2023 13:33:00 -0500 Received: from mail-wr1-x42e.google.com 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([2a01:cb1d:334:ac00:9236:abcb:4905:a64e]) by smtp.gmail.com with ESMTPSA id bp28-20020a5d5a9c000000b00273cd321a1bsm29356681wrb.107.2023.01.17.10.04.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 10:04:41 -0800 (PST) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Shazad Hussain , Bartosz Golaszewski Subject: [PATCH v2 2/2] clk: qcom: add the GCC driver for sa8775p Date: Tue, 17 Jan 2023 19:04:29 +0100 Message-Id: <20230117180429.305266-3-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230117180429.305266-1-brgl@bgdev.pl> References: <20230117180429.305266-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Shazad Hussain Add support for the Global Clock Controller found in the QTI SA8775P platforms. Signed-off-by: Shazad Hussain [Bartosz: made the driver ready for upstream] Co-developed-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sa8775p.c | 4805 ++++++++++++++++++++++++++++++++ 3 files changed, 4815 insertions(+) create mode 100644 drivers/clk/qcom/gcc-sa8775p.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 1b6615fe1dba..33a220aae618 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -410,6 +410,15 @@ config SC_DISPCC_8280XP Say Y if you want to support display devices and functionality such as splash screen. =20 +config SA_GCC_8775P + tristate "SA8775 Global Clock Controller" + select QCOM_GDSC + depends on COMMON_CLK_QCOM + help + Support for the global clock controller on SA8775 devices. + Say Y if you want to use peripheral devices such as UART, SPI, + I2C, USB, UFS, SDCC, etc. + config SC_GCC_7180 tristate "SC7180 Global Clock Controller" select QCOM_GDSC diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 6c589f671003..fd4a531d9bc9 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_SC_CAMCC_7280) +=3D camcc-sc7280.o obj-$(CONFIG_SC_DISPCC_7180) +=3D dispcc-sc7180.o obj-$(CONFIG_SC_DISPCC_7280) +=3D dispcc-sc7280.o obj-$(CONFIG_SC_DISPCC_8280XP) +=3D dispcc-sc8280xp.o +obj-$(CONFIG_SA_GCC_8775P) +=3D gcc-sa8775p.o obj-$(CONFIG_SC_GCC_7180) +=3D gcc-sc7180.o obj-$(CONFIG_SC_GCC_7280) +=3D gcc-sc7280.o obj-$(CONFIG_SC_GCC_8180X) +=3D gcc-sc8180x.o diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c new file mode 100644 index 000000000000..b5da7e0b2eaf --- /dev/null +++ b/drivers/clk/qcom/gcc-sa8775p.c @@ -0,0 +1,4805 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights re= served. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +/* Need to match the order of clocks in DT binding */ +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_UFS_PHY_RX_SYMBOL_0_CLK, + DT_UFS_PHY_RX_SYMBOL_1_CLK, + DT_UFS_PHY_TX_SYMBOL_0_CLK, + DT_UFS_CARD_RX_SYMBOL_0_CLK, + DT_UFS_CARD_RX_SYMBOL_1_CLK, + DT_UFS_CARD_TX_SYMBOL_0_CLK, + DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, + DT_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, + DT_PCIE_0_PIPE_CLK, + DT_PCIE_1_PIPE_CLK, + DT_PCIE_PHY_AUX_CLK, + DT_RXC0_REF_CLK, + DT_RXC1_REF_CLK, +}; + +enum { + P_BI_TCXO, + P_GCC_GPLL0_OUT_EVEN, + P_GCC_GPLL0_OUT_MAIN, + P_GCC_GPLL1_OUT_MAIN, + P_GCC_GPLL4_OUT_MAIN, + P_GCC_GPLL5_OUT_MAIN, + P_GCC_GPLL7_OUT_MAIN, + P_GCC_GPLL9_OUT_MAIN, + P_PCIE_0_PIPE_CLK, + P_PCIE_1_PIPE_CLK, + P_PCIE_PHY_AUX_CLK, + P_RXC0_REF_CLK, + P_RXC1_REF_CLK, + P_SLEEP_CLK, + P_UFS_CARD_RX_SYMBOL_0_CLK, + P_UFS_CARD_RX_SYMBOL_1_CLK, + P_UFS_CARD_TX_SYMBOL_0_CLK, + P_UFS_PHY_RX_SYMBOL_0_CLK, + P_UFS_PHY_RX_SYMBOL_1_CLK, + P_UFS_PHY_TX_SYMBOL_0_CLK, + P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, + P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, +}; + +static const struct clk_parent_data gcc_parent_data_tcxo =3D { .index =3D = DT_BI_TCXO }; + +static struct clk_alpha_pll gcc_gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x4b028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gpll0", + .parent_data =3D &gcc_parent_data_tcxo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gcc_gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gcc_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static struct clk_alpha_pll gcc_gpll1 =3D { + .offset =3D 0x1000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x4b028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gpll1", + .parent_data =3D &gcc_parent_data_tcxo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll4 =3D { + .offset =3D 0x4000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x4b028, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gpll4", + .parent_data =3D &gcc_parent_data_tcxo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll5 =3D { + .offset =3D 0x5000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x4b028, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gpll5", + .parent_data =3D &gcc_parent_data_tcxo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll7 =3D { + .offset =3D 0x7000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x4b028, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gpll7", + .parent_data =3D &gcc_parent_data_tcxo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll9 =3D { + .offset =3D 0x9000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x4b028, + .enable_mask =3D BIT(9), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gpll9", + .parent_data =3D &gcc_parent_data_tcxo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL1_OUT_MAIN, 4 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll1.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL7_OUT_MAIN, 2 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll7.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_7[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL7_OUT_MAIN, 2 }, + { P_RXC0_REF_CLK, 3 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_7[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll7.clkr.hw }, + { .index =3D DT_RXC0_REF_CLK }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_8[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL7_OUT_MAIN, 2 }, + { P_RXC1_REF_CLK, 3 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_8[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll7.clkr.hw }, + { .index =3D DT_RXC1_REF_CLK }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_9[] =3D { + { P_PCIE_PHY_AUX_CLK, 1 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_9[] =3D { + { .index =3D DT_PCIE_PHY_AUX_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_10[] =3D { + { P_PCIE_0_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_10[] =3D { + { .index =3D DT_PCIE_0_PIPE_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_11[] =3D { + { P_PCIE_PHY_AUX_CLK, 1 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_11[] =3D { + { .index =3D DT_PCIE_PHY_AUX_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_12[] =3D { + { P_PCIE_1_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_12[] =3D { + { .index =3D DT_PCIE_1_PIPE_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_13[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL9_OUT_MAIN, 2 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_13[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll9.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_14[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data gcc_parent_data_14[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_15[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL7_OUT_MAIN, 2 }, + { P_GCC_GPLL5_OUT_MAIN, 3 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_15[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll7.clkr.hw }, + { .hw =3D &gcc_gpll5.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_16[] =3D { + { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_16[] =3D { + { .index =3D DT_UFS_CARD_RX_SYMBOL_0_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_17[] =3D { + { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_17[] =3D { + { .index =3D DT_UFS_CARD_RX_SYMBOL_1_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_18[] =3D { + { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_18[] =3D { + { .index =3D DT_UFS_CARD_TX_SYMBOL_0_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_19[] =3D { + { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_19[] =3D { + { .index =3D DT_UFS_PHY_RX_SYMBOL_0_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_20[] =3D { + { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_20[] =3D { + { .index =3D DT_UFS_PHY_RX_SYMBOL_1_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_21[] =3D { + { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_21[] =3D { + { .index =3D DT_UFS_PHY_TX_SYMBOL_0_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_22[] =3D { + { P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_22[] =3D { + { .index =3D DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_23[] =3D { + { P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_23[] =3D { + { .index =3D DT_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src =3D { + .reg =3D 0xa9074, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_9, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_0_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_9, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_9), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src =3D { + .reg =3D 0xa906c, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_0_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_PCIE_0_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src =3D { + .reg =3D 0x77074, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_11, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_1_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_11, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_11), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src =3D { + .reg =3D 0x7706c, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_1_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE_1_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src =3D { + .reg =3D 0x81060, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_16, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_rx_symbol_0_clk_src", + .parent_data =3D gcc_parent_data_16, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_16), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src =3D { + .reg =3D 0x810d0, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_17, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_rx_symbol_1_clk_src", + .parent_data =3D gcc_parent_data_17, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_17), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src =3D { + .reg =3D 0x81050, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_18, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_tx_symbol_0_clk_src", + .parent_data =3D gcc_parent_data_18, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_18), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src =3D { + .reg =3D 0x83060, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_19, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_rx_symbol_0_clk_src", + .parent_data =3D gcc_parent_data_19, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_19), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src =3D { + .reg =3D 0x830d0, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_20, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_rx_symbol_1_clk_src", + .parent_data =3D gcc_parent_data_20, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_20), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src =3D { + .reg =3D 0x83050, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_21, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_tx_symbol_0_clk_src", + .parent_data =3D gcc_parent_data_21, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_21), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src =3D { + .reg =3D 0x1b068, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_22, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_pipe_clk_src", + .parent_data =3D gcc_parent_data_22, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_22), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src =3D { + .reg =3D 0x2f068, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_23, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb3_sec_phy_pipe_clk_src", + .parent_data =3D gcc_parent_data_23, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_23), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0xb6028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac0_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] =3D { + F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0), + F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_ptp_clk_src =3D { + .cmd_rcgr =3D 0xb6060, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_6, + .freq_tbl =3D ftbl_gcc_emac0_ptp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac0_ptp_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] =3D { + F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0), + F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_rgmii_clk_src =3D { + .cmd_rcgr =3D 0xb6048, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_7, + .freq_tbl =3D ftbl_gcc_emac0_rgmii_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac0_rgmii_clk_src", + .parent_data =3D gcc_parent_data_7, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_7), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_emac1_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0xb4028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac1_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_emac1_ptp_clk_src =3D { + .cmd_rcgr =3D 0xb4060, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_6, + .freq_tbl =3D ftbl_gcc_emac0_ptp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac1_ptp_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_emac1_rgmii_clk_src =3D { + .cmd_rcgr =3D 0xb4048, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_8, + .freq_tbl =3D ftbl_gcc_emac0_rgmii_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac1_rgmii_clk_src", + .parent_data =3D gcc_parent_data_8, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] =3D { + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x70004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gp1_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x71004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gp2_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src =3D { + .cmd_rcgr =3D 0x62004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gp3_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp4_clk_src =3D { + .cmd_rcgr =3D 0x1e004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gp4_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp5_clk_src =3D { + .cmd_rcgr =3D 0x1f004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gp5_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_0_aux_clk_src =3D { + .cmd_rcgr =3D 0xa9078, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_0_aux_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] =3D { + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0xa9054, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_0_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_1_aux_clk_src =3D { + .cmd_rcgr =3D 0x77078, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_1_aux_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x77054, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_1_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] =3D { + F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src =3D { + .cmd_rcgr =3D 0x3f010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pdm2_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pdm2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] =3D { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src =3D { + .cmd_rcgr =3D 0x23154, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src =3D { + .cmd_rcgr =3D 0x23288, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] =3D { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src =3D { + .cmd_rcgr =3D 0x233bc, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src =3D { + .cmd_rcgr =3D 0x234f0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s4_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src =3D { + .cmd_rcgr =3D 0x23624, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src =3D { + .cmd_rcgr =3D 0x23758, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s6_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src =3D { + .cmd_rcgr =3D 0x2388c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s6_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src =3D { + .cmd_rcgr =3D 0x24154, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src =3D { + .cmd_rcgr =3D 0x24288, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src =3D { + .cmd_rcgr =3D 0x243bc, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src =3D { + .cmd_rcgr =3D 0x244f0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s4_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src =3D { + .cmd_rcgr =3D 0x24624, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src =3D { + .cmd_rcgr =3D 0x24758, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s6_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src =3D { + .cmd_rcgr =3D 0x2488c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s6_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s0_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src =3D { + .cmd_rcgr =3D 0x2a154, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s1_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src =3D { + .cmd_rcgr =3D 0x2a288, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s2_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src =3D { + .cmd_rcgr =3D 0x2a3bc, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s3_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src =3D { + .cmd_rcgr =3D 0x2a4f0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s4_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src =3D { + .cmd_rcgr =3D 0x2a624, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s5_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src =3D { + .cmd_rcgr =3D 0x2a758, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s6_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src =3D { + .cmd_rcgr =3D 0x2a88c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s6_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap3_s0_clk_src[] =3D { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap3_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap3_s0_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap3_s0_clk_src =3D { + .cmd_rcgr =3D 0xc4154, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_qupv3_wrap3_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap3_s0_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] =3D { + F(144000, P_BI_TCXO, 16, 3, 25), + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3), + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), + F(192000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), + F(384000000, P_GCC_GPLL9_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src =3D { + .cmd_rcgr =3D 0x20014, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_13, + .freq_tbl =3D ftbl_gcc_sdcc1_apps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_sdcc1_apps_clk_src", + .parent_data =3D gcc_parent_data_13, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_13), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] =3D { + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x2002c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_14, + .freq_tbl =3D ftbl_gcc_sdcc1_ice_core_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_sdcc1_ice_core_clk_src", + .parent_data =3D gcc_parent_data_14, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_14), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_tscss_cntr_clk_src[] =3D { + F(15625000, P_GCC_GPLL7_OUT_MAIN, 16, 1, 4), + { } +}; + +static struct clk_rcg2 gcc_tscss_cntr_clk_src =3D { + .cmd_rcgr =3D 0x21008, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_15, + .freq_tbl =3D ftbl_gcc_tscss_cntr_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_tscss_cntr_clk_src", + .parent_data =3D gcc_parent_data_15, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_15), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] =3D { + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), + F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_card_axi_clk_src =3D { + .cmd_rcgr =3D 0x8102c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_card_axi_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_axi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] =3D { + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), + F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x81074, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_card_ice_core_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_ice_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x810a8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src =3D { + .cmd_rcgr =3D 0x8108c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_card_ice_core_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_unipro_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src =3D { + .cmd_rcgr =3D 0x8302c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_card_axi_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_axi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x83074, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_card_ice_core_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_ice_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x830a8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src =3D { + .cmd_rcgr =3D 0x8308c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_card_ice_core_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_unipro_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] =3D { + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb20_master_clk_src =3D { + .cmd_rcgr =3D 0x1c028, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb20_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb20_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x1c040, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb20_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] =3D { + F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_master_clk_src =3D { + .cmd_rcgr =3D 0x1b028, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb30_prim_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb30_prim_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x1b040, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb30_prim_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_sec_master_clk_src =3D { + .cmd_rcgr =3D 0x2f028, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb30_prim_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb30_sec_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x2f040, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb30_sec_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x1b06c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x2f06c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb3_sec_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gcc_pcie_0_pipe_div_clk_src =3D { + .reg =3D 0xa9070, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_pipe_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pcie_0_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_pcie_1_pipe_div_clk_src =3D { + .reg =3D 0x77070, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_pipe_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pcie_1_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_qupv3_wrap3_s0_div_clk_src =3D { + .reg =3D 0xc4284, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap3_s0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0x1c058, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb20_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0x1b058, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0x2f058, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_sec_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_aggre_noc_qupv3_axi_clk =3D { + .halt_reg =3D 0x8e200, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8e200, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4b000, + .enable_mask =3D BIT(28), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_aggre_noc_qupv3_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_ufs_card_axi_clk =3D { + .halt_reg =3D 0x810d4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x810d4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x810d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_aggre_ufs_card_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_card_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x830d4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x830d4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x830d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_aggre_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk =3D { + .halt_reg =3D 0x830d4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x830d4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x830d4, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_aggre_ufs_phy_axi_hw_ctl_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb2_prim_axi_clk =3D { + .halt_reg =3D 0x1c05c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x1c05c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1c05c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_aggre_usb2_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb3_prim_axi_clk =3D { + .halt_reg =3D 0x1b084, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x1b084, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1b084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_aggre_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb3_sec_axi_clk =3D { + .halt_reg =3D 0x2f088, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2f088, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2f088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_aggre_usb3_sec_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_sec_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ahb2phy0_clk =3D { + .halt_reg =3D 0x76004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x76004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x76004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ahb2phy0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ahb2phy2_clk =3D { + .halt_reg =3D 0x76008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x76008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x76008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ahb2phy2_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ahb2phy3_clk =3D { + .halt_reg =3D 0x7600c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x7600c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7600c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ahb2phy3_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk =3D { + .halt_reg =3D 0x44004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x44004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4b000, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_boot_rom_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_hf_axi_clk =3D { + .halt_reg =3D 0x32010, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x32010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x32010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_camera_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_sf_axi_clk =3D { + .halt_reg =3D 0x32018, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x32018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x32018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_camera_sf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_throttle_xo_clk =3D { + .halt_reg =3D 0x32024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x32024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_camera_throttle_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk =3D { + .halt_reg =3D 0x1c060, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x1c060, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1c060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_cfg_noc_usb2_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk =3D { + .halt_reg =3D 0x1b088, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x1b088, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1b088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_cfg_noc_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk =3D { + .halt_reg =3D 0x2f084, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2f084, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2f084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_cfg_noc_usb3_sec_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_sec_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ddrss_gpu_axi_clk =3D { + .halt_reg =3D 0x7d164, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x7d164, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d164, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ddrss_gpu_axi_clk", + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gcc_disp1_hf_axi_clk =3D { + .halt_reg =3D 0xc7010, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xc7010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xc7010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_disp1_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_hf_axi_clk =3D { + .halt_reg =3D 0x33010, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x33010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x33010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_disp_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_edp_ref_clkref_en =3D { + .halt_reg =3D 0x97448, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x97448, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_edp_ref_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_axi_clk =3D { + .halt_reg =3D 0xb6018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb6018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb6018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac0_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_phy_aux_clk =3D { + .halt_reg =3D 0xb6024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb6024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac0_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_emac0_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_ptp_clk =3D { + .halt_reg =3D 0xb6040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb6040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac0_ptp_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_emac0_ptp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_rgmii_clk =3D { + .halt_reg =3D 0xb6044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb6044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac0_rgmii_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_emac0_rgmii_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_slv_ahb_clk =3D { + .halt_reg =3D 0xb6020, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb6020, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb6020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac0_slv_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_axi_clk =3D { + .halt_reg =3D 0xb4018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb4018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb4018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac1_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_phy_aux_clk =3D { + .halt_reg =3D 0xb4024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb4024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac1_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_emac1_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_ptp_clk =3D { + .halt_reg =3D 0xb4040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb4040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac1_ptp_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_emac1_ptp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_rgmii_clk =3D { + .halt_reg =3D 0xb4044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb4044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac1_rgmii_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_emac1_rgmii_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_slv_ahb_clk =3D { + .halt_reg =3D 0xb4020, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb4020, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb4020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_emac1_slv_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk =3D { + .halt_reg =3D 0x70000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x70000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk =3D { + .halt_reg =3D 0x71000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk =3D { + .halt_reg =3D 0x62000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gp3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp4_clk =3D { + .halt_reg =3D 0x1e000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1e000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gp4_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp5_clk =3D { + .halt_reg =3D 0x1f000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1f000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gp5_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x4b000, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gpu_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x4b000, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gpu_gpll0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gpll0_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_memnoc_gfx_clk =3D { + .halt_reg =3D 0x7d010, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x7d010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gpu_memnoc_gfx_clk", + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk =3D { + .halt_reg =3D 0x7d01c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x7d01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gpu_snoc_dvm_gfx_clk", + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_tcu_throttle_ahb_clk =3D { + .halt_reg =3D 0x7d008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x7d008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gpu_tcu_throttle_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_tcu_throttle_clk =3D { + .halt_reg =3D 0x7d014, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x7d014, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_gpu_tcu_throttle_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_aux_clk =3D { + .halt_reg =3D 0xa9038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pcie_0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_cfg_ahb_clk =3D { + .halt_reg =3D 0xa902c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xa902c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_0_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_mstr_axi_clk =3D { + .halt_reg =3D 0xa9024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(11), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_0_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_phy_aux_clk =3D { + .halt_reg =3D 0xa9030, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_0_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pcie_0_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_phy_rchng_clk =3D { + .halt_reg =3D 0xa9050, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_0_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_pipe_clk =3D { + .halt_reg =3D 0xa9040, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_0_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pcie_0_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_pipediv2_clk =3D { + .halt_reg =3D 0xa9048, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x4b018, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_0_pipediv2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pcie_0_pipe_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_slv_axi_clk =3D { + .halt_reg =3D 0xa901c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_0_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk =3D { + .halt_reg =3D 0xa9018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b018, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_0_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_aux_clk =3D { + .halt_reg =3D 0x77038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b000, + .enable_mask =3D BIT(31), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_1_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pcie_1_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_cfg_ahb_clk =3D { + .halt_reg =3D 0x7702c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x7702c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_1_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_mstr_axi_clk =3D { + .halt_reg =3D 0x77024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_1_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_phy_aux_clk =3D { + .halt_reg =3D 0x77030, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_1_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pcie_1_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_phy_rchng_clk =3D { + .halt_reg =3D 0x77050, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b000, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_1_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_pipe_clk =3D { + .halt_reg =3D 0x77040, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_1_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pcie_1_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_pipediv2_clk =3D { + .halt_reg =3D 0x77048, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x4b018, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_1_pipediv2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pcie_1_pipe_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_slv_axi_clk =3D { + .halt_reg =3D 0x7701c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_1_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x77018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_1_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_clkref_en =3D { + .halt_reg =3D 0x9746c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x9746c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_throttle_cfg_clk =3D { + .halt_reg =3D 0xb2034, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b020, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pcie_throttle_cfg_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk =3D { + .halt_reg =3D 0x3f00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3f00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pdm2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk =3D { + .halt_reg =3D 0x3f004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x3f004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3f004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pdm_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk =3D { + .halt_reg =3D 0x3f008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3f008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_pdm_xo4_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk =3D { + .halt_reg =3D 0x32008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x32008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x32008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qmip_camera_nrt_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_rt_ahb_clk =3D { + .halt_reg =3D 0x3200c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x3200c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3200c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qmip_camera_rt_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp1_ahb_clk =3D { + .halt_reg =3D 0xc7008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xc7008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xc7008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qmip_disp1_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp1_rot_ahb_clk =3D { + .halt_reg =3D 0xc700c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xc700c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qmip_disp1_rot_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp_ahb_clk =3D { + .halt_reg =3D 0x33008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x33008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x33008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qmip_disp_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp_rot_ahb_clk =3D { + .halt_reg =3D 0x3300c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x3300c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qmip_disp_rot_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_cvp_ahb_clk =3D { + .halt_reg =3D 0x34008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x34008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x34008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qmip_video_cvp_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk =3D { + .halt_reg =3D 0x3400c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x3400c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3400c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qmip_video_vcodec_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_vcpu_ahb_clk =3D { + .halt_reg =3D 0x34010, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x34010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x34010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qmip_video_vcpu_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk =3D { + .halt_reg =3D 0x23018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(9), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk =3D { + .halt_reg =3D 0x2300c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk =3D { + .halt_reg =3D 0x2314c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk =3D { + .halt_reg =3D 0x23280, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(11), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk =3D { + .halt_reg =3D 0x233b4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk =3D { + .halt_reg =3D 0x234e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk =3D { + .halt_reg =3D 0x2361c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s4_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk =3D { + .halt_reg =3D 0x23750, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s5_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s6_clk =3D { + .halt_reg =3D 0x23884, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s6_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk =3D { + .halt_reg =3D 0x24018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_clk =3D { + .halt_reg =3D 0x2400c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s0_clk =3D { + .halt_reg =3D 0x2414c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s1_clk =3D { + .halt_reg =3D 0x24280, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s2_clk =3D { + .halt_reg =3D 0x243b4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s3_clk =3D { + .halt_reg =3D 0x244e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s4_clk =3D { + .halt_reg =3D 0x2461c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s4_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s5_clk =3D { + .halt_reg =3D 0x24750, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(27), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s5_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s6_clk =3D { + .halt_reg =3D 0x24884, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b018, + .enable_mask =3D BIT(27), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s6_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_core_2x_clk =3D { + .halt_reg =3D 0x2a018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap2_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_core_clk =3D { + .halt_reg =3D 0x2a00c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap2_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s0_clk =3D { + .halt_reg =3D 0x2a14c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap2_s0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s1_clk =3D { + .halt_reg =3D 0x2a280, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap2_s1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s2_clk =3D { + .halt_reg =3D 0x2a3b4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap2_s2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s3_clk =3D { + .halt_reg =3D 0x2a4e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap2_s3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s4_clk =3D { + .halt_reg =3D 0x2a61c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap2_s4_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s5_clk =3D { + .halt_reg =3D 0x2a750, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(9), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap2_s5_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s6_clk =3D { + .halt_reg =3D 0x2a884, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b018, + .enable_mask =3D BIT(29), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap2_s6_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_core_2x_clk =3D { + .halt_reg =3D 0xc4018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b000, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap3_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_core_clk =3D { + .halt_reg =3D 0xc400c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b000, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap3_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_qspi_clk =3D { + .halt_reg =3D 0xc4280, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b000, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap3_qspi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_s0_clk =3D { + .halt_reg =3D 0xc414c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4b000, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap3_s0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap3_s0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk =3D { + .halt_reg =3D 0x23004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x23004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_0_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk =3D { + .halt_reg =3D 0x23008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x23008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_0_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk =3D { + .halt_reg =3D 0x24004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x24004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_1_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk =3D { + .halt_reg =3D 0x24008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x24008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4b008, + .enable_mask =3D BIT(21), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_1_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk =3D { + .halt_reg =3D 0x2a004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2a004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_2_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk =3D { + .halt_reg =3D 0x2a008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2a008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4b010, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_2_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk =3D { + .halt_reg =3D 0xc4004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xc4004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4b000, + .enable_mask =3D BIT(27), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_3_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk =3D { + .halt_reg =3D 0xc4008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xc4008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4b000, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_3_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk =3D { + .halt_reg =3D 0x2000c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2000c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_sdcc1_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk =3D { + .halt_reg =3D 0x20004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_sdcc1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk =3D { + .halt_reg =3D 0x20044, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x20044, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x20044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_sdcc1_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sgmi_clkref_en =3D { + .halt_reg =3D 0x9c034, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x9c034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_sgmi_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tscss_ahb_clk =3D { + .halt_reg =3D 0x21024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_tscss_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tscss_etu_clk =3D { + .halt_reg =3D 0x21020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_tscss_etu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tscss_global_cntr_clk =3D { + .halt_reg =3D 0x21004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x21004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_tscss_global_cntr_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_tscss_cntr_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_ahb_clk =3D { + .halt_reg =3D 0x81020, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x81020, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x81020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_axi_clk =3D { + .halt_reg =3D 0x81018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x81018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x81018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_card_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_ice_core_clk =3D { + .halt_reg =3D 0x8106c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8106c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8106c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_card_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_phy_aux_clk =3D { + .halt_reg =3D 0x810a4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x810a4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x810a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_card_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_rx_symbol_0_clk =3D { + .halt_reg =3D 0x81028, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x81028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_rx_symbol_0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_rx_symbol_1_clk =3D { + .halt_reg =3D 0x810c0, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x810c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_rx_symbol_1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_tx_symbol_0_clk =3D { + .halt_reg =3D 0x81024, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x81024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_tx_symbol_0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_unipro_core_clk =3D { + .halt_reg =3D 0x81064, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x81064, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x81064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_card_unipro_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_card_unipro_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ahb_clk =3D { + .halt_reg =3D 0x83020, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x83020, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x83020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x83018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x83018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x83018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk =3D { + .halt_reg =3D 0x83018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x83018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x83018, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_axi_hw_ctl_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ice_core_clk =3D { + .halt_reg =3D 0x8306c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8306c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8306c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk =3D { + .halt_reg =3D 0x8306c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8306c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8306c, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_ice_core_hw_ctl_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_phy_aux_clk =3D { + .halt_reg =3D 0x830a4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x830a4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x830a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk =3D { + .halt_reg =3D 0x830a4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x830a4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x830a4, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_phy_aux_hw_ctl_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk =3D { + .halt_reg =3D 0x83028, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x83028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_rx_symbol_0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk =3D { + .halt_reg =3D 0x830c0, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x830c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_rx_symbol_1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk =3D { + .halt_reg =3D 0x83024, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x83024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_tx_symbol_0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_unipro_core_clk =3D { + .halt_reg =3D 0x83064, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x83064, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x83064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_unipro_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk =3D { + .halt_reg =3D 0x83064, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x83064, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x83064, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_ufs_phy_unipro_core_hw_ctl_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_master_clk =3D { + .halt_reg =3D 0x1c018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1c018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb20_master_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_mock_utmi_clk =3D { + .halt_reg =3D 0x1c024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1c024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb20_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_sleep_clk =3D { + .halt_reg =3D 0x1c020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1c020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb20_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_master_clk =3D { + .halt_reg =3D 0x1b018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1b018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb30_prim_master_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_mock_utmi_clk =3D { + .halt_reg =3D 0x1b024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1b024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb30_prim_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_sleep_clk =3D { + .halt_reg =3D 0x1b020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1b020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb30_prim_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sec_master_clk =3D { + .halt_reg =3D 0x2f018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2f018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb30_sec_master_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_sec_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sec_mock_utmi_clk =3D { + .halt_reg =3D 0x2f024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2f024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb30_sec_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sec_sleep_clk =3D { + .halt_reg =3D 0x2f020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2f020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb30_sec_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_aux_clk =3D { + .halt_reg =3D 0x1b05c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1b05c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk =3D { + .halt_reg =3D 0x1b060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1b060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_com_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_pipe_clk =3D { + .halt_reg =3D 0x1b064, + .halt_check =3D BRANCH_HALT_DELAY, + .hwcg_reg =3D 0x1b064, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1b064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_sec_phy_aux_clk =3D { + .halt_reg =3D 0x2f05c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2f05c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb3_sec_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_sec_phy_com_aux_clk =3D { + .halt_reg =3D 0x2f060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2f060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb3_sec_phy_com_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_sec_phy_pipe_clk =3D { + .halt_reg =3D 0x2f064, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x2f064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb3_sec_phy_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_clkref_en =3D { + .halt_reg =3D 0x97468, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x97468, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_usb_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi0_clk =3D { + .halt_reg =3D 0x34014, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x34014, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x34014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_video_axi0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi1_clk =3D { + .halt_reg =3D 0x3401c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x3401c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3401c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gcc_video_axi1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc pcie_0_gdsc =3D { + .gdscr =3D 0xa9004, + .pd =3D { + .name =3D "pcie_0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc pcie_1_gdsc =3D { + .gdscr =3D 0x77004, + .pd =3D { + .name =3D "pcie_1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc ufs_card_gdsc =3D { + .gdscr =3D 0x81004, + .pd =3D { + .name =3D "ufs_card_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc ufs_phy_gdsc =3D { + .gdscr =3D 0x83004, + .pd =3D { + .name =3D "ufs_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc usb20_prim_gdsc =3D { + .gdscr =3D 0x1c004, + .pd =3D { + .name =3D "usb20_prim_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_prim_gdsc =3D { + .gdscr =3D 0x1b004, + .pd =3D { + .name =3D "usb30_prim_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_sec_gdsc =3D { + .gdscr =3D 0x2f004, + .pd =3D { + .name =3D "usb30_sec_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc emac0_gdsc =3D { + .gdscr =3D 0xb6004, + .pd =3D { + .name =3D "emac0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc emac1_gdsc =3D { + .gdscr =3D 0xb4004, + .pd =3D { + .name =3D "emac1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct clk_regmap *gcc_sa8775p_clocks[] =3D { + [GCC_AGGRE_NOC_QUPV3_AXI_CLK] =3D &gcc_aggre_noc_qupv3_axi_clk.clkr, + [GCC_AGGRE_UFS_CARD_AXI_CLK] =3D &gcc_aggre_ufs_card_axi_clk.clkr, + [GCC_AGGRE_UFS_PHY_AXI_CLK] =3D &gcc_aggre_ufs_phy_axi_clk.clkr, + [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =3D &gcc_aggre_ufs_phy_axi_hw_ctl_clk.= clkr, + [GCC_AGGRE_USB2_PRIM_AXI_CLK] =3D &gcc_aggre_usb2_prim_axi_clk.clkr, + [GCC_AGGRE_USB3_PRIM_AXI_CLK] =3D &gcc_aggre_usb3_prim_axi_clk.clkr, + [GCC_AGGRE_USB3_SEC_AXI_CLK] =3D &gcc_aggre_usb3_sec_axi_clk.clkr, + [GCC_AHB2PHY0_CLK] =3D &gcc_ahb2phy0_clk.clkr, + [GCC_AHB2PHY2_CLK] =3D &gcc_ahb2phy2_clk.clkr, + [GCC_AHB2PHY3_CLK] =3D &gcc_ahb2phy3_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAMERA_HF_AXI_CLK] =3D &gcc_camera_hf_axi_clk.clkr, + [GCC_CAMERA_SF_AXI_CLK] =3D &gcc_camera_sf_axi_clk.clkr, + [GCC_CAMERA_THROTTLE_XO_CLK] =3D &gcc_camera_throttle_xo_clk.clkr, + [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] =3D &gcc_cfg_noc_usb2_prim_axi_clk.clkr, + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_cfg_noc_usb3_prim_axi_clk.clkr, + [GCC_CFG_NOC_USB3_SEC_AXI_CLK] =3D &gcc_cfg_noc_usb3_sec_axi_clk.clkr, + [GCC_DDRSS_GPU_AXI_CLK] =3D &gcc_ddrss_gpu_axi_clk.clkr, + [GCC_DISP1_HF_AXI_CLK] =3D &gcc_disp1_hf_axi_clk.clkr, + [GCC_DISP_HF_AXI_CLK] =3D &gcc_disp_hf_axi_clk.clkr, + [GCC_EDP_REF_CLKREF_EN] =3D &gcc_edp_ref_clkref_en.clkr, + [GCC_EMAC0_AXI_CLK] =3D &gcc_emac0_axi_clk.clkr, + [GCC_EMAC0_PHY_AUX_CLK] =3D &gcc_emac0_phy_aux_clk.clkr, + [GCC_EMAC0_PHY_AUX_CLK_SRC] =3D &gcc_emac0_phy_aux_clk_src.clkr, + [GCC_EMAC0_PTP_CLK] =3D &gcc_emac0_ptp_clk.clkr, + [GCC_EMAC0_PTP_CLK_SRC] =3D &gcc_emac0_ptp_clk_src.clkr, + [GCC_EMAC0_RGMII_CLK] =3D &gcc_emac0_rgmii_clk.clkr, + [GCC_EMAC0_RGMII_CLK_SRC] =3D &gcc_emac0_rgmii_clk_src.clkr, + [GCC_EMAC0_SLV_AHB_CLK] =3D &gcc_emac0_slv_ahb_clk.clkr, + [GCC_EMAC1_AXI_CLK] =3D &gcc_emac1_axi_clk.clkr, + [GCC_EMAC1_PHY_AUX_CLK] =3D &gcc_emac1_phy_aux_clk.clkr, + [GCC_EMAC1_PHY_AUX_CLK_SRC] =3D &gcc_emac1_phy_aux_clk_src.clkr, + [GCC_EMAC1_PTP_CLK] =3D &gcc_emac1_ptp_clk.clkr, + [GCC_EMAC1_PTP_CLK_SRC] =3D &gcc_emac1_ptp_clk_src.clkr, + [GCC_EMAC1_RGMII_CLK] =3D &gcc_emac1_rgmii_clk.clkr, + [GCC_EMAC1_RGMII_CLK_SRC] =3D &gcc_emac1_rgmii_clk_src.clkr, + [GCC_EMAC1_SLV_AHB_CLK] =3D &gcc_emac1_slv_ahb_clk.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, + [GCC_GP4_CLK] =3D &gcc_gp4_clk.clkr, + [GCC_GP4_CLK_SRC] =3D &gcc_gp4_clk_src.clkr, + [GCC_GP5_CLK] =3D &gcc_gp5_clk.clkr, + [GCC_GP5_CLK_SRC] =3D &gcc_gp5_clk_src.clkr, + [GCC_GPLL0] =3D &gcc_gpll0.clkr, + [GCC_GPLL0_OUT_EVEN] =3D &gcc_gpll0_out_even.clkr, + [GCC_GPLL1] =3D &gcc_gpll1.clkr, + [GCC_GPLL4] =3D &gcc_gpll4.clkr, + [GCC_GPLL5] =3D &gcc_gpll5.clkr, + [GCC_GPLL7] =3D &gcc_gpll7.clkr, + [GCC_GPLL9] =3D &gcc_gpll9.clkr, + [GCC_GPU_GPLL0_CLK_SRC] =3D &gcc_gpu_gpll0_clk_src.clkr, + [GCC_GPU_GPLL0_DIV_CLK_SRC] =3D &gcc_gpu_gpll0_div_clk_src.clkr, + [GCC_GPU_MEMNOC_GFX_CLK] =3D &gcc_gpu_memnoc_gfx_clk.clkr, + [GCC_GPU_SNOC_DVM_GFX_CLK] =3D &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [GCC_GPU_TCU_THROTTLE_AHB_CLK] =3D &gcc_gpu_tcu_throttle_ahb_clk.clkr, + [GCC_GPU_TCU_THROTTLE_CLK] =3D &gcc_gpu_tcu_throttle_clk.clkr, + [GCC_PCIE_0_AUX_CLK] =3D &gcc_pcie_0_aux_clk.clkr, + [GCC_PCIE_0_AUX_CLK_SRC] =3D &gcc_pcie_0_aux_clk_src.clkr, + [GCC_PCIE_0_CFG_AHB_CLK] =3D &gcc_pcie_0_cfg_ahb_clk.clkr, + [GCC_PCIE_0_MSTR_AXI_CLK] =3D &gcc_pcie_0_mstr_axi_clk.clkr, + [GCC_PCIE_0_PHY_AUX_CLK] =3D &gcc_pcie_0_phy_aux_clk.clkr, + [GCC_PCIE_0_PHY_AUX_CLK_SRC] =3D &gcc_pcie_0_phy_aux_clk_src.clkr, + [GCC_PCIE_0_PHY_RCHNG_CLK] =3D &gcc_pcie_0_phy_rchng_clk.clkr, + [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_0_phy_rchng_clk_src.clkr, + [GCC_PCIE_0_PIPE_CLK] =3D &gcc_pcie_0_pipe_clk.clkr, + [GCC_PCIE_0_PIPE_CLK_SRC] =3D &gcc_pcie_0_pipe_clk_src.clkr, + [GCC_PCIE_0_PIPE_DIV_CLK_SRC] =3D &gcc_pcie_0_pipe_div_clk_src.clkr, + [GCC_PCIE_0_PIPEDIV2_CLK] =3D &gcc_pcie_0_pipediv2_clk.clkr, + [GCC_PCIE_0_SLV_AXI_CLK] =3D &gcc_pcie_0_slv_axi_clk.clkr, + [GCC_PCIE_0_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_0_slv_q2a_axi_clk.clkr, + [GCC_PCIE_1_AUX_CLK] =3D &gcc_pcie_1_aux_clk.clkr, + [GCC_PCIE_1_AUX_CLK_SRC] =3D &gcc_pcie_1_aux_clk_src.clkr, + [GCC_PCIE_1_CFG_AHB_CLK] =3D &gcc_pcie_1_cfg_ahb_clk.clkr, + [GCC_PCIE_1_MSTR_AXI_CLK] =3D &gcc_pcie_1_mstr_axi_clk.clkr, + [GCC_PCIE_1_PHY_AUX_CLK] =3D &gcc_pcie_1_phy_aux_clk.clkr, + [GCC_PCIE_1_PHY_AUX_CLK_SRC] =3D &gcc_pcie_1_phy_aux_clk_src.clkr, + [GCC_PCIE_1_PHY_RCHNG_CLK] =3D &gcc_pcie_1_phy_rchng_clk.clkr, + [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_1_phy_rchng_clk_src.clkr, + [GCC_PCIE_1_PIPE_CLK] =3D &gcc_pcie_1_pipe_clk.clkr, + [GCC_PCIE_1_PIPE_CLK_SRC] =3D &gcc_pcie_1_pipe_clk_src.clkr, + [GCC_PCIE_1_PIPE_DIV_CLK_SRC] =3D &gcc_pcie_1_pipe_div_clk_src.clkr, + [GCC_PCIE_1_PIPEDIV2_CLK] =3D &gcc_pcie_1_pipediv2_clk.clkr, + [GCC_PCIE_1_SLV_AXI_CLK] =3D &gcc_pcie_1_slv_axi_clk.clkr, + [GCC_PCIE_1_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_1_slv_q2a_axi_clk.clkr, + [GCC_PCIE_CLKREF_EN] =3D &gcc_pcie_clkref_en.clkr, + [GCC_PCIE_THROTTLE_CFG_CLK] =3D &gcc_pcie_throttle_cfg_clk.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] =3D &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] =3D &gcc_pdm_xo4_clk.clkr, + [GCC_QMIP_CAMERA_NRT_AHB_CLK] =3D &gcc_qmip_camera_nrt_ahb_clk.clkr, + [GCC_QMIP_CAMERA_RT_AHB_CLK] =3D &gcc_qmip_camera_rt_ahb_clk.clkr, + [GCC_QMIP_DISP1_AHB_CLK] =3D &gcc_qmip_disp1_ahb_clk.clkr, + [GCC_QMIP_DISP1_ROT_AHB_CLK] =3D &gcc_qmip_disp1_rot_ahb_clk.clkr, + [GCC_QMIP_DISP_AHB_CLK] =3D &gcc_qmip_disp_ahb_clk.clkr, + [GCC_QMIP_DISP_ROT_AHB_CLK] =3D &gcc_qmip_disp_rot_ahb_clk.clkr, + [GCC_QMIP_VIDEO_CVP_AHB_CLK] =3D &gcc_qmip_video_cvp_ahb_clk.clkr, + [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] =3D &gcc_qmip_video_vcodec_ahb_clk.clkr, + [GCC_QMIP_VIDEO_VCPU_AHB_CLK] =3D &gcc_qmip_video_vcpu_ahb_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] =3D &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] =3D &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] =3D &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] =3D &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] =3D &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] =3D &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] =3D &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] =3D &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] =3D &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] =3D &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] =3D &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] =3D &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP0_S5_CLK] =3D &gcc_qupv3_wrap0_s5_clk.clkr, + [GCC_QUPV3_WRAP0_S5_CLK_SRC] =3D &gcc_qupv3_wrap0_s5_clk_src.clkr, + [GCC_QUPV3_WRAP0_S6_CLK] =3D &gcc_qupv3_wrap0_s6_clk.clkr, + [GCC_QUPV3_WRAP0_S6_CLK_SRC] =3D &gcc_qupv3_wrap0_s6_clk_src.clkr, + [GCC_QUPV3_WRAP1_CORE_2X_CLK] =3D &gcc_qupv3_wrap1_core_2x_clk.clkr, + [GCC_QUPV3_WRAP1_CORE_CLK] =3D &gcc_qupv3_wrap1_core_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK] =3D &gcc_qupv3_wrap1_s0_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK_SRC] =3D &gcc_qupv3_wrap1_s0_clk_src.clkr, + [GCC_QUPV3_WRAP1_S1_CLK] =3D &gcc_qupv3_wrap1_s1_clk.clkr, + [GCC_QUPV3_WRAP1_S1_CLK_SRC] =3D &gcc_qupv3_wrap1_s1_clk_src.clkr, + [GCC_QUPV3_WRAP1_S2_CLK] =3D &gcc_qupv3_wrap1_s2_clk.clkr, + [GCC_QUPV3_WRAP1_S2_CLK_SRC] =3D &gcc_qupv3_wrap1_s2_clk_src.clkr, + [GCC_QUPV3_WRAP1_S3_CLK] =3D &gcc_qupv3_wrap1_s3_clk.clkr, + [GCC_QUPV3_WRAP1_S3_CLK_SRC] =3D &gcc_qupv3_wrap1_s3_clk_src.clkr, + [GCC_QUPV3_WRAP1_S4_CLK] =3D &gcc_qupv3_wrap1_s4_clk.clkr, + [GCC_QUPV3_WRAP1_S4_CLK_SRC] =3D &gcc_qupv3_wrap1_s4_clk_src.clkr, + [GCC_QUPV3_WRAP1_S5_CLK] =3D &gcc_qupv3_wrap1_s5_clk.clkr, + [GCC_QUPV3_WRAP1_S5_CLK_SRC] =3D &gcc_qupv3_wrap1_s5_clk_src.clkr, + [GCC_QUPV3_WRAP1_S6_CLK] =3D &gcc_qupv3_wrap1_s6_clk.clkr, + [GCC_QUPV3_WRAP1_S6_CLK_SRC] =3D &gcc_qupv3_wrap1_s6_clk_src.clkr, + [GCC_QUPV3_WRAP2_CORE_2X_CLK] =3D &gcc_qupv3_wrap2_core_2x_clk.clkr, + [GCC_QUPV3_WRAP2_CORE_CLK] =3D &gcc_qupv3_wrap2_core_clk.clkr, + [GCC_QUPV3_WRAP2_S0_CLK] =3D &gcc_qupv3_wrap2_s0_clk.clkr, + [GCC_QUPV3_WRAP2_S0_CLK_SRC] =3D &gcc_qupv3_wrap2_s0_clk_src.clkr, + [GCC_QUPV3_WRAP2_S1_CLK] =3D &gcc_qupv3_wrap2_s1_clk.clkr, + [GCC_QUPV3_WRAP2_S1_CLK_SRC] =3D &gcc_qupv3_wrap2_s1_clk_src.clkr, + [GCC_QUPV3_WRAP2_S2_CLK] =3D &gcc_qupv3_wrap2_s2_clk.clkr, + [GCC_QUPV3_WRAP2_S2_CLK_SRC] =3D &gcc_qupv3_wrap2_s2_clk_src.clkr, + [GCC_QUPV3_WRAP2_S3_CLK] =3D &gcc_qupv3_wrap2_s3_clk.clkr, + [GCC_QUPV3_WRAP2_S3_CLK_SRC] =3D &gcc_qupv3_wrap2_s3_clk_src.clkr, + [GCC_QUPV3_WRAP2_S4_CLK] =3D &gcc_qupv3_wrap2_s4_clk.clkr, + [GCC_QUPV3_WRAP2_S4_CLK_SRC] =3D &gcc_qupv3_wrap2_s4_clk_src.clkr, + [GCC_QUPV3_WRAP2_S5_CLK] =3D &gcc_qupv3_wrap2_s5_clk.clkr, + [GCC_QUPV3_WRAP2_S5_CLK_SRC] =3D &gcc_qupv3_wrap2_s5_clk_src.clkr, + [GCC_QUPV3_WRAP2_S6_CLK] =3D &gcc_qupv3_wrap2_s6_clk.clkr, + [GCC_QUPV3_WRAP2_S6_CLK_SRC] =3D &gcc_qupv3_wrap2_s6_clk_src.clkr, + [GCC_QUPV3_WRAP3_CORE_2X_CLK] =3D &gcc_qupv3_wrap3_core_2x_clk.clkr, + [GCC_QUPV3_WRAP3_CORE_CLK] =3D &gcc_qupv3_wrap3_core_clk.clkr, + [GCC_QUPV3_WRAP3_QSPI_CLK] =3D &gcc_qupv3_wrap3_qspi_clk.clkr, + [GCC_QUPV3_WRAP3_S0_CLK] =3D &gcc_qupv3_wrap3_s0_clk.clkr, + [GCC_QUPV3_WRAP3_S0_CLK_SRC] =3D &gcc_qupv3_wrap3_s0_clk_src.clkr, + [GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC] =3D &gcc_qupv3_wrap3_s0_div_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] =3D &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] =3D &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_M_AHB_CLK] =3D &gcc_qupv3_wrap_1_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_S_AHB_CLK] =3D &gcc_qupv3_wrap_1_s_ahb_clk.clkr, + [GCC_QUPV3_WRAP_2_M_AHB_CLK] =3D &gcc_qupv3_wrap_2_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_2_S_AHB_CLK] =3D &gcc_qupv3_wrap_2_s_ahb_clk.clkr, + [GCC_QUPV3_WRAP_3_M_AHB_CLK] =3D &gcc_qupv3_wrap_3_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_3_S_AHB_CLK] =3D &gcc_qupv3_wrap_3_s_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] =3D &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] =3D &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] =3D &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] =3D &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] =3D &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SGMI_CLKREF_EN] =3D &gcc_sgmi_clkref_en.clkr, + [GCC_TSCSS_AHB_CLK] =3D &gcc_tscss_ahb_clk.clkr, + [GCC_TSCSS_CNTR_CLK_SRC] =3D &gcc_tscss_cntr_clk_src.clkr, + [GCC_TSCSS_ETU_CLK] =3D &gcc_tscss_etu_clk.clkr, + [GCC_TSCSS_GLOBAL_CNTR_CLK] =3D &gcc_tscss_global_cntr_clk.clkr, + [GCC_UFS_CARD_AHB_CLK] =3D &gcc_ufs_card_ahb_clk.clkr, + [GCC_UFS_CARD_AXI_CLK] =3D &gcc_ufs_card_axi_clk.clkr, + [GCC_UFS_CARD_AXI_CLK_SRC] =3D &gcc_ufs_card_axi_clk_src.clkr, + [GCC_UFS_CARD_ICE_CORE_CLK] =3D &gcc_ufs_card_ice_core_clk.clkr, + [GCC_UFS_CARD_ICE_CORE_CLK_SRC] =3D &gcc_ufs_card_ice_core_clk_src.clkr, + [GCC_UFS_CARD_PHY_AUX_CLK] =3D &gcc_ufs_card_phy_aux_clk.clkr, + [GCC_UFS_CARD_PHY_AUX_CLK_SRC] =3D &gcc_ufs_card_phy_aux_clk_src.clkr, + [GCC_UFS_CARD_RX_SYMBOL_0_CLK] =3D &gcc_ufs_card_rx_symbol_0_clk.clkr, + [GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] =3D &gcc_ufs_card_rx_symbol_0_clk_src.= clkr, + [GCC_UFS_CARD_RX_SYMBOL_1_CLK] =3D &gcc_ufs_card_rx_symbol_1_clk.clkr, + [GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] =3D &gcc_ufs_card_rx_symbol_1_clk_src.= clkr, + [GCC_UFS_CARD_TX_SYMBOL_0_CLK] =3D &gcc_ufs_card_tx_symbol_0_clk.clkr, + [GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] =3D &gcc_ufs_card_tx_symbol_0_clk_src.= clkr, + [GCC_UFS_CARD_UNIPRO_CORE_CLK] =3D &gcc_ufs_card_unipro_core_clk.clkr, + [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =3D &gcc_ufs_card_unipro_core_clk_src.= clkr, + [GCC_UFS_PHY_AHB_CLK] =3D &gcc_ufs_phy_ahb_clk.clkr, + [GCC_UFS_PHY_AXI_CLK] =3D &gcc_ufs_phy_axi_clk.clkr, + [GCC_UFS_PHY_AXI_CLK_SRC] =3D &gcc_ufs_phy_axi_clk_src.clkr, + [GCC_UFS_PHY_AXI_HW_CTL_CLK] =3D &gcc_ufs_phy_axi_hw_ctl_clk.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK] =3D &gcc_ufs_phy_ice_core_clk.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK_SRC] =3D &gcc_ufs_phy_ice_core_clk_src.clkr, + [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =3D &gcc_ufs_phy_ice_core_hw_ctl_clk.cl= kr, + [GCC_UFS_PHY_PHY_AUX_CLK] =3D &gcc_ufs_phy_phy_aux_clk.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK_SRC] =3D &gcc_ufs_phy_phy_aux_clk_src.clkr, + [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] =3D &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] =3D &gcc_ufs_phy_rx_symbol_0_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] =3D &gcc_ufs_phy_rx_symbol_0_clk_src.cl= kr, + [GCC_UFS_PHY_RX_SYMBOL_1_CLK] =3D &gcc_ufs_phy_rx_symbol_1_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] =3D &gcc_ufs_phy_rx_symbol_1_clk_src.cl= kr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] =3D &gcc_ufs_phy_tx_symbol_0_clk.clkr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] =3D &gcc_ufs_phy_tx_symbol_0_clk_src.cl= kr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK] =3D &gcc_ufs_phy_unipro_core_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =3D &gcc_ufs_phy_unipro_core_clk_src.cl= kr, + [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =3D &gcc_ufs_phy_unipro_core_hw_ctl_= clk.clkr, + [GCC_USB20_MASTER_CLK] =3D &gcc_usb20_master_clk.clkr, + [GCC_USB20_MASTER_CLK_SRC] =3D &gcc_usb20_master_clk_src.clkr, + [GCC_USB20_MOCK_UTMI_CLK] =3D &gcc_usb20_mock_utmi_clk.clkr, + [GCC_USB20_MOCK_UTMI_CLK_SRC] =3D &gcc_usb20_mock_utmi_clk_src.clkr, + [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb20_mock_utmi_postdiv_cl= k_src.clkr, + [GCC_USB20_SLEEP_CLK] =3D &gcc_usb20_sleep_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK] =3D &gcc_usb30_prim_master_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK_SRC] =3D &gcc_usb30_prim_master_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK] =3D &gcc_usb30_prim_mock_utmi_clk.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =3D &gcc_usb30_prim_mock_utmi_clk_src.= clkr, + [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb30_prim_mock_utmi_= postdiv_clk_src.clkr, + [GCC_USB30_PRIM_SLEEP_CLK] =3D &gcc_usb30_prim_sleep_clk.clkr, + [GCC_USB30_SEC_MASTER_CLK] =3D &gcc_usb30_sec_master_clk.clkr, + [GCC_USB30_SEC_MASTER_CLK_SRC] =3D &gcc_usb30_sec_master_clk_src.clkr, + [GCC_USB30_SEC_MOCK_UTMI_CLK] =3D &gcc_usb30_sec_mock_utmi_clk.clkr, + [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =3D &gcc_usb30_sec_mock_utmi_clk_src.cl= kr, + [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb30_sec_mock_utmi_po= stdiv_clk_src.clkr, + [GCC_USB30_SEC_SLEEP_CLK] =3D &gcc_usb30_sec_sleep_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK] =3D &gcc_usb3_prim_phy_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] =3D &gcc_usb3_prim_phy_aux_clk_src.clkr, + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] =3D &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] =3D &gcc_usb3_prim_phy_pipe_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] =3D &gcc_usb3_prim_phy_pipe_clk_src.clkr, + [GCC_USB3_SEC_PHY_AUX_CLK] =3D &gcc_usb3_sec_phy_aux_clk.clkr, + [GCC_USB3_SEC_PHY_AUX_CLK_SRC] =3D &gcc_usb3_sec_phy_aux_clk_src.clkr, + [GCC_USB3_SEC_PHY_COM_AUX_CLK] =3D &gcc_usb3_sec_phy_com_aux_clk.clkr, + [GCC_USB3_SEC_PHY_PIPE_CLK] =3D &gcc_usb3_sec_phy_pipe_clk.clkr, + [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] =3D &gcc_usb3_sec_phy_pipe_clk_src.clkr, + [GCC_USB_CLKREF_EN] =3D &gcc_usb_clkref_en.clkr, + [GCC_VIDEO_AXI0_CLK] =3D &gcc_video_axi0_clk.clkr, + [GCC_VIDEO_AXI1_CLK] =3D &gcc_video_axi1_clk.clkr, +}; + +static const struct qcom_reset_map gcc_sa8775p_resets[] =3D { + [GCC_CAMERA_BCR] =3D { 0x32000 }, + [GCC_DISPLAY1_BCR] =3D { 0xc7000 }, + [GCC_DISPLAY_BCR] =3D { 0x33000 }, + [GCC_EMAC0_BCR] =3D { 0xb6000 }, + [GCC_EMAC1_BCR] =3D { 0xb4000 }, + [GCC_GPU_BCR] =3D { 0x7d000 }, + [GCC_MMSS_BCR] =3D { 0x17000 }, + [GCC_PCIE_0_BCR] =3D { 0xa9000 }, + [GCC_PCIE_0_LINK_DOWN_BCR] =3D { 0xbf000 }, + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] =3D { 0xbf008 }, + [GCC_PCIE_0_PHY_BCR] =3D { 0xad144 }, + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] =3D { 0xbf00c }, + [GCC_PCIE_1_BCR] =3D { 0x77000 }, + [GCC_PCIE_1_LINK_DOWN_BCR] =3D { 0xae084 }, + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] =3D { 0xae090 }, + [GCC_PCIE_1_PHY_BCR] =3D { 0xae08c }, + [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] =3D { 0xae094 }, + [GCC_PDM_BCR] =3D { 0x3f000 }, + [GCC_QUPV3_WRAPPER_0_BCR] =3D { 0x23000 }, + [GCC_QUPV3_WRAPPER_1_BCR] =3D { 0x24000 }, + [GCC_QUPV3_WRAPPER_2_BCR] =3D { 0x2a000 }, + [GCC_QUPV3_WRAPPER_3_BCR] =3D { 0xc4000 }, + [GCC_SDCC1_BCR] =3D { 0x20000 }, + [GCC_TSCSS_BCR] =3D { 0x21000 }, + [GCC_UFS_CARD_BCR] =3D { 0x81000 }, + [GCC_UFS_PHY_BCR] =3D { 0x83000 }, + [GCC_USB20_PRIM_BCR] =3D { 0x1c000 }, + [GCC_USB2_PHY_PRIM_BCR] =3D { 0x5c028 }, + [GCC_USB2_PHY_SEC_BCR] =3D { 0x5c02c }, + [GCC_USB30_PRIM_BCR] =3D { 0x1b000 }, + [GCC_USB30_SEC_BCR] =3D { 0x2f000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] =3D { 0x5c008 }, + [GCC_USB3_DP_PHY_SEC_BCR] =3D { 0x5c014 }, + [GCC_USB3_PHY_PRIM_BCR] =3D { 0x5c000 }, + [GCC_USB3_PHY_SEC_BCR] =3D { 0x5c00c }, + [GCC_USB3_PHY_TERT_BCR] =3D { 0x5c030 }, + [GCC_USB3_UNIPHY_MP0_BCR] =3D { 0x5c018 }, + [GCC_USB3_UNIPHY_MP1_BCR] =3D { 0x5c01c }, + [GCC_USB3PHY_PHY_PRIM_BCR] =3D { 0x5c004 }, + [GCC_USB3PHY_PHY_SEC_BCR] =3D { 0x5c010 }, + [GCC_USB3UNIPHY_PHY_MP0_BCR] =3D { 0x5c020 }, + [GCC_USB3UNIPHY_PHY_MP1_BCR] =3D { 0x5c024 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] =3D { 0x76000 }, + [GCC_VIDEO_AXI0_CLK_ARES] =3D { 0x34014, 2 }, + [GCC_VIDEO_AXI1_CLK_ARES] =3D { 0x3401c, 2 }, + [GCC_VIDEO_BCR] =3D { 0x34000 }, +}; + +static struct gdsc *gcc_sa8775p_gdscs[] =3D { + [PCIE_0_GDSC] =3D &pcie_0_gdsc, + [PCIE_1_GDSC] =3D &pcie_1_gdsc, + [UFS_CARD_GDSC] =3D &ufs_card_gdsc, + [UFS_PHY_GDSC] =3D &ufs_phy_gdsc, + [USB20_PRIM_GDSC] =3D &usb20_prim_gdsc, + [USB30_PRIM_GDSC] =3D &usb30_prim_gdsc, + [USB30_SEC_GDSC] =3D &usb30_sec_gdsc, + [EMAC0_GDSC] =3D &emac0_gdsc, + [EMAC1_GDSC] =3D &emac1_gdsc, +}; + +static const struct clk_rcg_dfs_data gcc_dfs_clocks[] =3D { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap3_s0_clk_src), +}; + +static const struct regmap_config gcc_sa8775p_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xc7018, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc gcc_sa8775p_desc =3D { + .config =3D &gcc_sa8775p_regmap_config, + .clks =3D gcc_sa8775p_clocks, + .num_clks =3D ARRAY_SIZE(gcc_sa8775p_clocks), + .resets =3D gcc_sa8775p_resets, + .num_resets =3D ARRAY_SIZE(gcc_sa8775p_resets), + .gdscs =3D gcc_sa8775p_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_sa8775p_gdscs), +}; + +static const struct of_device_id gcc_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,sa8775p-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_sa8775p_match_table); + +static int gcc_sa8775p_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap =3D qcom_cc_map(pdev, &gcc_sa8775p_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, + ARRAY_SIZE(gcc_dfs_clocks)); + if (ret) + return ret; + + /* + * Keep the clocks always-ON + * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK, + * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, + * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK. + */ + regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0)); + + return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); +} + +static struct platform_driver gcc_sa8775p_driver =3D { + .probe =3D gcc_sa8775p_probe, + .driver =3D { + .name =3D "sa8775p-gcc", + .of_match_table =3D gcc_sa8775p_match_table, + }, +}; + +static int __init gcc_sa8775p_init(void) +{ + return platform_driver_register(&gcc_sa8775p_driver); +} +subsys_initcall(gcc_sa8775p_init); + +static void __exit gcc_sa8775p_exit(void) +{ + platform_driver_unregister(&gcc_sa8775p_driver); +} +module_exit(gcc_sa8775p_exit); + +MODULE_DESCRIPTION("Qualcomm SA8775P GCC driver"); +MODULE_LICENSE("GPL"); --=20 2.37.2