From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4228C46467 for ; Mon, 16 Jan 2023 12:49:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230457AbjAPMtt (ORCPT ); Mon, 16 Jan 2023 07:49:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230438AbjAPMti (ORCPT ); Mon, 16 Jan 2023 07:49:38 -0500 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBE541E5E2 for ; Mon, 16 Jan 2023 04:49:36 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id f12-20020a7bc8cc000000b003daf6b2f9b9so2555341wml.3 for ; Mon, 16 Jan 2023 04:49:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=71Qc7NdqE+vOIwrKti0fEKXkbrxyF/DZyAYqjBspK70=; b=UMw5f8qGCf/rlTwaNDjugAXf8EG3ZO5VXjRThRel94xSOkPOm6kV5+JOgCB65DT/HR rK+rLcTxjQX4wH5KgnA8qsNAp1RmRZogCZl3BMklp6S7dVUcj6bf+ggbdkDfWGaQguXa cHx9lWvIojog440Vk2MazwybKiPClqgIFFZiPXHGYl+hGemZVsQuRfTF6fGk4ylCUrow lS/2T5F0N589sun56yI5wcq+qWKmRjo0nTp1e4H3ap7hOgDcpgEXhID4XAf3HRwIKbcr JEHbRHHERKCnkTKqXV7MqeK6cRTzdFiAcMIg16Uf7YCzdEguX3EYUnr4/ZRa2AYWma7t RzKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=71Qc7NdqE+vOIwrKti0fEKXkbrxyF/DZyAYqjBspK70=; b=YK4sah/vgacPCyqMnISkIqFLPNW3Kgx2P4uZ8fBYQyqHkkIliKMVTV1UbYinkI2vzL OLjYn1hQhC8NfCNoxjYqjIdTzh4PAMnyb6nqpQBFpTl5sQt6bN10ZAbsgDxngZwVaBS2 CzjpY5TrHIuiFlJQk/Ir0+U/IVfsTIssbYlRXTc/68Q/uzAZ1uVCWSTJk2f2GGv7w9LM 2FLUbloncWtS23k9jsPRpVHHX1cyDJUXp0X8j1jrIi1HKniu4uPt0zd6mdLNhusSXmJw 8C4N5Ea+20e1SATlrctlpYtt26YF2Ep8oT/OZu9gbHLOxkYr8kalXJi5TFohVULy29lY 0I+Q== X-Gm-Message-State: AFqh2kqeA6UbmU5J5DCIe3+8T7pqBRYM7jx540O+RDOnYNAW9sci3KPs 5AonPD35xWj7rGH+M0HsBO3x5Q== X-Google-Smtp-Source: AMrXdXvU+ZkDBJDD4w/QUItGJvYhE8j3rM7R4rivD5QcUjb7oTzhg6bTdY/uy3PnjXOAv/M9nRb72Q== X-Received: by 2002:a05:600c:1c1b:b0:3da:fada:e38a with SMTP id j27-20020a05600c1c1b00b003dafadae38amr3547636wms.24.1673873375295; Mon, 16 Jan 2023 04:49:35 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:6c91:710d:9433:e868]) by smtp.gmail.com with ESMTPSA id fl12-20020a05600c0b8c00b003dab40f9eafsm6896832wmb.35.2023.01.16.04.49.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 04:49:34 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v7 01/15] coresight: trace-id: Add API to dynamically assign Trace ID values Date: Mon, 16 Jan 2023 12:49:14 +0000 Message-Id: <20230116124928.5440-2-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230116124928.5440-1-mike.leach@linaro.org> References: <20230116124928.5440-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The existing mechanism to assign Trace ID values to sources is limited and does not scale for larger multicore / multi trace source systems. The API introduces functions that reserve IDs based on availabilty represented by a coresight_trace_id_map structure. This records the used and free IDs in a bitmap. CPU bound sources such as ETMs use the coresight_trace_id_get_cpu_id coresight_trace_id_put_cpu_id pair of functions. The API will record the ID associated with the CPU. This ensures that the same ID will be re-used while perf events are active on the CPU. The put_cpu_id function will pend release of the ID until all perf cs_etm sessions are complete. For backward compatibility the functions will attempt to use the same CPU IDs as the legacy system would have used if these are still available. Non-cpu sources, such as the STM can use coresight_trace_id_get_system_id / coresight_trace_id_put_system_id. Signed-off-by: Mike Leach Reported-by: kernel test robot --- drivers/hwtracing/coresight/Makefile | 2 +- .../hwtracing/coresight/coresight-trace-id.c | 265 ++++++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 156 +++++++++++ include/linux/coresight-pmu.h | 10 + 4 files changed, 432 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index b6c4a48140ec..329a0c704b87 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_CORESIGHT) +=3D coresight.o coresight-y :=3D coresight-core.o coresight-etm-perf.o coresight-platform= .o \ coresight-sysfs.o coresight-syscfg.o coresight-config.o \ coresight-cfg-preload.o coresight-cfg-afdo.o \ - coresight-syscfg-configfs.o + coresight-syscfg-configfs.o coresight-trace-id.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) +=3D coresight-tmc.o coresight-tmc-y :=3D coresight-tmc-core.o coresight-tmc-etf.o \ coresight-tmc-etr.o diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwt= racing/coresight/coresight-trace-id.c new file mode 100644 index 000000000000..9b85c376cb12 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, Linaro Limited, All rights reserved. + * Author: Mike Leach + */ +#include +#include +#include +#include +#include + +#include "coresight-trace-id.h" + +/* Default trace ID map. Used on systems that don't require per sink mappi= ngs */ +static struct coresight_trace_id_map id_map_default; + +/* maintain a record of the mapping of IDs and pending releases per cpu */ +static DEFINE_PER_CPU(atomic_t, cpu_id) =3D ATOMIC_INIT(0); +static cpumask_t cpu_id_release_pending; + +/* perf session active counter */ +static atomic_t perf_cs_etm_session_active =3D ATOMIC_INIT(0); + +/* lock to protect id_map and cpu data */ +static DEFINE_SPINLOCK(id_map_lock); + +/* unlocked read of current trace ID value for given CPU */ +static int _coresight_trace_id_read_cpu_id(int cpu) +{ + return atomic_read(&per_cpu(cpu_id, cpu)); +} + +/* look for next available odd ID, return 0 if none found */ +static int coresight_trace_id_find_odd_id(struct coresight_trace_id_map *i= d_map) +{ + int found_id =3D 0, bit =3D 1, next_id; + + while ((bit < CORESIGHT_TRACE_ID_RES_TOP) && !found_id) { + /* + * bitmap length of CORESIGHT_TRACE_ID_RES_TOP, + * search from offset `bit`. + */ + next_id =3D find_next_zero_bit(id_map->used_ids, + CORESIGHT_TRACE_ID_RES_TOP, bit); + if ((next_id < CORESIGHT_TRACE_ID_RES_TOP) && (next_id & 0x1)) + found_id =3D next_id; + else + bit =3D next_id + 1; + } + return found_id; +} + +/* + * Allocate new ID and set in use + * + * if @preferred_id is a valid id then try to use that value if available. + * if @preferred_id is not valid and @prefer_odd_id is true, try for odd i= d. + * + * Otherwise allocate next available ID. + */ +static int coresight_trace_id_alloc_new_id(struct coresight_trace_id_map *= id_map, + int preferred_id, bool prefer_odd_id) +{ + int id =3D 0; + + /* for backwards compatibility, cpu IDs may use preferred value */ + if (IS_VALID_CS_TRACE_ID(preferred_id) && + !test_bit(preferred_id, id_map->used_ids)) { + id =3D preferred_id; + goto trace_id_allocated; + } else if (prefer_odd_id) { + /* may use odd ids to avoid preferred legacy cpu IDs */ + id =3D coresight_trace_id_find_odd_id(id_map); + if (id) + goto trace_id_allocated; + } + + /* + * skip reserved bit 0, look at bitmap length of + * CORESIGHT_TRACE_ID_RES_TOP from offset of bit 1. + */ + id =3D find_next_zero_bit(id_map->used_ids, CORESIGHT_TRACE_ID_RES_TOP, 1= ); + if (id >=3D CORESIGHT_TRACE_ID_RES_TOP) + return -EINVAL; + + /* mark as used */ +trace_id_allocated: + set_bit(id, id_map->used_ids); + return id; +} + +static void coresight_trace_id_free(int id, struct coresight_trace_id_map = *id_map) +{ + if (WARN(!IS_VALID_CS_TRACE_ID(id), "Invalid Trace ID %d\n", id)) + return; + if (WARN(!test_bit(id, id_map->used_ids), "Freeing unused ID %d\n", id)) + return; + clear_bit(id, id_map->used_ids); +} + +static void coresight_trace_id_set_pend_rel(int id, struct coresight_trace= _id_map *id_map) +{ + if (WARN(!IS_VALID_CS_TRACE_ID(id), "Invalid Trace ID %d\n", id)) + return; + set_bit(id, id_map->pend_rel_ids); +} + +/* + * release all pending IDs for all current maps & clear CPU associations + * + * This currently operates on the default id map, but may be extended to + * operate on all registered id maps if per sink id maps are used. + */ +static void coresight_trace_id_release_all_pending(void) +{ + struct coresight_trace_id_map *id_map =3D &id_map_default; + unsigned long flags; + int cpu, bit; + + spin_lock_irqsave(&id_map_lock, flags); + for_each_set_bit(bit, id_map->pend_rel_ids, CORESIGHT_TRACE_ID_RES_TOP) { + clear_bit(bit, id_map->used_ids); + clear_bit(bit, id_map->pend_rel_ids); + } + for_each_cpu(cpu, &cpu_id_release_pending) { + atomic_set(&per_cpu(cpu_id, cpu), 0); + cpumask_clear_cpu(cpu, &cpu_id_release_pending); + } + spin_unlock_irqrestore(&id_map_lock, flags); +} + +static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_tra= ce_id_map *id_map) +{ + unsigned long flags; + int id; + + spin_lock_irqsave(&id_map_lock, flags); + + /* check for existing allocation for this CPU */ + id =3D _coresight_trace_id_read_cpu_id(cpu); + if (id) + goto get_cpu_id_clr_pend; + + /* + * Find a new ID. + * + * Use legacy values where possible in the dynamic trace ID allocator to + * allow older tools to continue working if they are not upgraded at the + * same time as the kernel drivers. + * + * If the generated legacy ID is invalid, or not available then the next + * available dynamic ID will be used. + */ + id =3D coresight_trace_id_alloc_new_id(id_map, + CORESIGHT_LEGACY_CPU_TRACE_ID(cpu), + false); + if (!IS_VALID_CS_TRACE_ID(id)) + goto get_cpu_id_out_unlock; + + /* allocate the new id to the cpu */ + atomic_set(&per_cpu(cpu_id, cpu), id); + +get_cpu_id_clr_pend: + /* we are (re)using this ID - so ensure it is not marked for release */ + cpumask_clear_cpu(cpu, &cpu_id_release_pending); + clear_bit(id, id_map->pend_rel_ids); + +get_cpu_id_out_unlock: + spin_unlock_irqrestore(&id_map_lock, flags); + + return id; +} + +static void coresight_trace_id_map_put_cpu_id(int cpu, struct coresight_tr= ace_id_map *id_map) +{ + unsigned long flags; + int id; + + /* check for existing allocation for this CPU */ + id =3D _coresight_trace_id_read_cpu_id(cpu); + if (!id) + return; + + spin_lock_irqsave(&id_map_lock, flags); + + if (atomic_read(&perf_cs_etm_session_active)) { + /* set release at pending if perf still active */ + coresight_trace_id_set_pend_rel(id, id_map); + cpumask_set_cpu(cpu, &cpu_id_release_pending); + } else { + /* otherwise clear id */ + coresight_trace_id_free(id, id_map); + atomic_set(&per_cpu(cpu_id, cpu), 0); + } + + spin_unlock_irqrestore(&id_map_lock, flags); +} + +static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_= map *id_map) +{ + unsigned long flags; + int id; + + spin_lock_irqsave(&id_map_lock, flags); + /* prefer odd IDs for system components to avoid legacy CPU IDS */ + id =3D coresight_trace_id_alloc_new_id(id_map, 0, true); + spin_unlock_irqrestore(&id_map_lock, flags); + + return id; +} + +static void coresight_trace_id_map_put_system_id(struct coresight_trace_id= _map *id_map, int id) +{ + unsigned long flags; + + spin_lock_irqsave(&id_map_lock, flags); + coresight_trace_id_free(id, id_map); + spin_unlock_irqrestore(&id_map_lock, flags); +} + +/* API functions */ + +int coresight_trace_id_get_cpu_id(int cpu) +{ + return coresight_trace_id_map_get_cpu_id(cpu, &id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_get_cpu_id); + +void coresight_trace_id_put_cpu_id(int cpu) +{ + coresight_trace_id_map_put_cpu_id(cpu, &id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_put_cpu_id); + +int coresight_trace_id_read_cpu_id(int cpu) +{ + return _coresight_trace_id_read_cpu_id(cpu); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_read_cpu_id); + +int coresight_trace_id_get_system_id(void) +{ + return coresight_trace_id_map_get_system_id(&id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_get_system_id); + +void coresight_trace_id_put_system_id(int id) +{ + coresight_trace_id_map_put_system_id(&id_map_default, id); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_put_system_id); + +void coresight_trace_id_perf_start(void) +{ + atomic_inc(&perf_cs_etm_session_active); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_perf_start); + +void coresight_trace_id_perf_stop(void) +{ + if (!atomic_dec_return(&perf_cs_etm_session_active)) + coresight_trace_id_release_all_pending(); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_perf_stop); + diff --git a/drivers/hwtracing/coresight/coresight-trace-id.h b/drivers/hwt= racing/coresight/coresight-trace-id.h new file mode 100644 index 000000000000..3797777d367e --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-trace-id.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright(C) 2022 Linaro Limited. All rights reserved. + * Author: Mike Leach + */ + +#ifndef _CORESIGHT_TRACE_ID_H +#define _CORESIGHT_TRACE_ID_H + +/* + * Coresight trace ID allocation API + * + * With multi cpu systems, and more additional trace sources a scalable + * trace ID reservation system is required. + * + * The system will allocate Ids on a demand basis, and allow them to be + * released when done. + * + * In order to ensure that a consistent cpu / ID matching is maintained + * throughout a perf cs_etm event session - a session in progress flag will + * be maintained, and released IDs not cleared until the perf session is + * complete. This allows the same CPU to be re-allocated its prior ID. + * + * + * Trace ID maps will be created and initialised to prevent architecturally + * reserved IDs from being allocated. + * + * API permits multiple maps to be maintained - for large systems where + * different sets of cpus trace into different independent sinks. + */ + +#include +#include + + +/* architecturally we have 128 IDs some of which are reserved */ +#define CORESIGHT_TRACE_IDS_MAX 128 + +/* ID 0 is reserved */ +#define CORESIGHT_TRACE_ID_RES_0 0 + +/* ID 0x70 onwards are reserved */ +#define CORESIGHT_TRACE_ID_RES_TOP 0x70 + +/* check an ID is in the valid range */ +#define IS_VALID_CS_TRACE_ID(id) \ + ((id > CORESIGHT_TRACE_ID_RES_0) && (id < CORESIGHT_TRACE_ID_RES_TOP)) + +/** + * Trace ID map. + * + * @used_ids: Bitmap to register available (bit =3D 0) and in use (bit =3D= 1) IDs. + * Initialised so that the reserved IDs are permanently marked as + * in use. + * @pend_rel_ids: CPU IDs that have been released by the trace source but = not + * yet marked as available, to allow re-allocation to the same + * CPU during a perf session. + */ +struct coresight_trace_id_map { + DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); + DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX); +}; + +/* Allocate and release IDs for a single default trace ID map */ + +/** + * Read and optionally allocate a CoreSight trace ID and associate with a = CPU. + * + * Function will read the current trace ID for the associated CPU, + * allocating an new ID if one is not currently allocated. + * + * Numeric ID values allocated use legacy allocation algorithm if possible, + * otherwise any available ID is used. + * + * @cpu: The CPU index to allocate for. + * + * return: CoreSight trace ID or -EINVAL if allocation impossible. + */ +int coresight_trace_id_get_cpu_id(int cpu); + +/** + * Release an allocated trace ID associated with the CPU. + * + * This will release the CoreSight trace ID associated with the CPU, + * unless a perf session is in operation. + * + * If a perf session is in operation then the ID will be marked as pending + * release. + * + * @cpu: The CPU index to release the associated trace ID. + */ +void coresight_trace_id_put_cpu_id(int cpu); + +/** + * Read the current allocated CoreSight Trace ID value for the CPU. + * + * Fast read of the current value that does not allocate if no ID allocated + * for the CPU. + * + * Used in perf context where it is known that the value for the CPU will= not + * be changing, when perf starts and event on a core and outputs the Trace= ID + * for the CPU as a packet in the data file. IDs cannot change during a pe= rf + * session. + * + * This function does not take the lock protecting the ID lists, avoiding + * locking dependency issues with perf locks. + * + * @cpu: The CPU index to read. + * + * return: current value, will be 0 if unallocated. + */ +int coresight_trace_id_read_cpu_id(int cpu); + +/** + * Allocate a CoreSight trace ID for a system component. + * + * Unconditionally allocates a Trace ID, without associating the ID with a= CPU. + * + * Used to allocate IDs for system trace sources such as STM. + * + * return: Trace ID or -EINVAL if allocation is impossible. + */ +int coresight_trace_id_get_system_id(void); + +/** + * Release an allocated system trace ID. + * + * Unconditionally release a trace ID allocated to a system component. + * + * @id: value of trace ID allocated. + */ +void coresight_trace_id_put_system_id(int id); + +/* notifiers for perf session start and stop */ + +/** + * Notify the Trace ID allocator that a perf session is starting. + * + * Increase the perf session reference count - called by perf when setting= up + * a trace event. + * + * This reference count is used by the ID allocator to ensure that trace I= Ds + * associated with a CPU cannot change or be released during a perf sessio= n. + */ +void coresight_trace_id_perf_start(void); + +/** + * Notify the ID allocator that a perf session is stopping. + * + * Decrease the perf session reference count. + * if this causes the count to go to zero, then all Trace IDs marked as pe= nding + * release, will be released. + */ +void coresight_trace_id_perf_stop(void); + +#endif /* _CORESIGHT_TRACE_ID_H */ diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 6c2fd6cc5a98..ffff4e6277e5 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -10,6 +10,16 @@ #define CORESIGHT_ETM_PMU_NAME "cs_etm" #define CORESIGHT_ETM_PMU_SEED 0x10 =20 +/* + * The legacy Trace ID system based on fixed calculation from the cpu + * number. This has been replaced by drivers using a dynamic allocation + * system - but need to retain the legacy algorithm for backward comparibi= lity + * in certain situations:- + * a) new perf running on older systems that generate the legacy mapping + * b) older tools that may not update at the same time as the kernel. + */ +#define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2)) + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35A35C46467 for ; Mon, 16 Jan 2023 12:49:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230423AbjAPMtz (ORCPT ); Mon, 16 Jan 2023 07:49:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230374AbjAPMtn (ORCPT ); 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Mon, 16 Jan 2023 04:49:35 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v7 02/15] coresight: Remove obsolete Trace ID unniqueness checks Date: Mon, 16 Jan 2023 12:49:15 +0000 Message-Id: <20230116124928.5440-3-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230116124928.5440-1-mike.leach@linaro.org> References: <20230116124928.5440-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The checks for sources to have unique IDs has been removed - this is now guaranteed by the ID allocation mechanisms, and inappropriate where multiple ID maps are in use in larger systems Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Reported-by: kernel test robot --- drivers/hwtracing/coresight/coresight-core.c | 45 -------------------- 1 file changed, 45 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index f3068175ca9d..ce3aa845ecc2 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -112,45 +112,6 @@ struct coresight_device *coresight_get_percpu_sink(int= cpu) } EXPORT_SYMBOL_GPL(coresight_get_percpu_sink); =20 -static int coresight_id_match(struct device *dev, void *data) -{ - int trace_id, i_trace_id; - struct coresight_device *csdev, *i_csdev; - - csdev =3D data; - i_csdev =3D to_coresight_device(dev); - - /* - * No need to care about oneself and components that are not - * sources or not enabled - */ - if (i_csdev =3D=3D csdev || !i_csdev->enable || - i_csdev->type !=3D CORESIGHT_DEV_TYPE_SOURCE) - return 0; - - /* Get the source ID for both components */ - trace_id =3D source_ops(csdev)->trace_id(csdev); - i_trace_id =3D source_ops(i_csdev)->trace_id(i_csdev); - - /* All you need is one */ - if (trace_id =3D=3D i_trace_id) - return 1; - - return 0; -} - -static int coresight_source_is_unique(struct coresight_device *csdev) -{ - int trace_id =3D source_ops(csdev)->trace_id(csdev); - - /* this shouldn't happen */ - if (trace_id < 0) - return 0; - - return !bus_for_each_dev(&coresight_bustype, NULL, - csdev, coresight_id_match); -} - static int coresight_find_link_inport(struct coresight_device *csdev, struct coresight_device *parent) { @@ -459,12 +420,6 @@ static int coresight_enable_source(struct coresight_de= vice *csdev, u32 mode) { int ret; =20 - if (!coresight_source_is_unique(csdev)) { - dev_warn(&csdev->dev, "traceID %d not unique\n", - source_ops(csdev)->trace_id(csdev)); - return -EINVAL; - } - if (!csdev->enable) { if (source_ops(csdev)->enable) { ret =3D coresight_control_assoc_ectdev(csdev, true); --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0FA7C54EBE for ; Mon, 16 Jan 2023 12:50:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230518AbjAPMuC (ORCPT ); Mon, 16 Jan 2023 07:50:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230443AbjAPMto (ORCPT ); Mon, 16 Jan 2023 07:49:44 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CF4B1E5EC for ; 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charset="utf-8" Adds in calls to allocate and release Trace ID for the CPUs in use by the perf session. Adds in notifier calls to the trace ID allocator that perf events are starting and stopping. This ensures that Trace IDs associated with CPUs remain the same throughout the perf session, and are only released when all perf sessions are complete. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Reported-by: kernel test robot --- drivers/hwtracing/coresight/coresight-etm-perf.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwt= racing/coresight/coresight-etm-perf.c index 43bbd5dc3d3b..bdb9ab86173a 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -22,6 +22,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" =20 static struct pmu etm_pmu; static bool etm_perf_up; @@ -228,8 +229,12 @@ static void free_event_data(struct work_struct *work) if (!(IS_ERR_OR_NULL(*ppath))) coresight_release_path(*ppath); *ppath =3D NULL; + coresight_trace_id_put_cpu_id(cpu); } =20 + /* mark perf event as done for trace id allocator */ + coresight_trace_id_perf_stop(); + free_percpu(event_data->path); kfree(event_data); } @@ -300,6 +305,7 @@ static void *etm_setup_aux(struct perf_event *event, vo= id **pages, { u32 id, cfg_hash; int cpu =3D event->cpu; + int trace_id; cpumask_t *mask; struct coresight_device *sink =3D NULL; struct coresight_device *user_sink =3D NULL, *last_sink =3D NULL; @@ -316,6 +322,9 @@ static void *etm_setup_aux(struct perf_event *event, vo= id **pages, sink =3D user_sink =3D coresight_get_sink_by_id(id); } =20 + /* tell the trace ID allocator that a perf event is starting up */ + coresight_trace_id_perf_start(); + /* check if user wants a coresight configuration selected */ cfg_hash =3D (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32); if (cfg_hash) { @@ -388,6 +397,13 @@ static void *etm_setup_aux(struct perf_event *event, v= oid **pages, continue; } =20 + /* ensure we can allocate a trace ID for this CPU */ + trace_id =3D coresight_trace_id_get_cpu_id(cpu); + if (!IS_VALID_CS_TRACE_ID(trace_id)) { + cpumask_clear_cpu(cpu, mask); + continue; + } + *etm_event_cpu_path_ptr(event_data, cpu) =3D path; } =20 --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FA2AC46467 for ; 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Mon, 16 Jan 2023 04:49:38 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v7 04/15] coresight: stm: Update STM driver to use Trace ID API Date: Mon, 16 Jan 2023 12:49:17 +0000 Message-Id: <20230116124928.5440-5-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230116124928.5440-1-mike.leach@linaro.org> References: <20230116124928.5440-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Updates the STM driver to use the trace ID allocation API. This uses the _system_id calls to allocate an ID on device poll, and release on device remove. The sysfs access to the STMTRACEIDR register has been changed from RW to RO. Having this value as writable is not appropriate for the new Trace ID scheme - and had potential to cause errors in the previous scheme if values clashed with other sources. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Reported-by: kernel test robot --- drivers/hwtracing/coresight/coresight-stm.c | 41 +++++++-------------- 1 file changed, 14 insertions(+), 27 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracin= g/coresight/coresight-stm.c index 463f449cfb79..6af1b996af6f 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -31,6 +31,7 @@ #include =20 #include "coresight-priv.h" +#include "coresight-trace-id.h" =20 #define STMDMASTARTR 0xc04 #define STMDMASTOPR 0xc08 @@ -615,24 +616,7 @@ static ssize_t traceid_show(struct device *dev, val =3D drvdata->traceid; return sprintf(buf, "%#lx\n", val); } - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; - struct stm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); - - ret =3D kstrtoul(buf, 16, &val); - if (ret) - return ret; - - /* traceid field is 7bit wide on STM32 */ - drvdata->traceid =3D val & 0x7f; - return size; -} -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); =20 static struct attribute *coresight_stm_attrs[] =3D { &dev_attr_hwevent_enable.attr, @@ -803,14 +787,6 @@ static void stm_init_default_data(struct stm_drvdata *= drvdata) */ drvdata->stmsper =3D ~0x0; =20 - /* - * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and - * anything equal to or higher than 0x70 is reserved. Since 0x00 is - * also reserved the STM trace ID needs to be higher than 0x00 and - * lowner than 0x10. - */ - drvdata->traceid =3D 0x1; - /* Set invariant transaction timing on all channels */ bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp); } @@ -838,7 +814,7 @@ static void stm_init_generic_data(struct stm_drvdata *d= rvdata, =20 static int stm_probe(struct amba_device *adev, const struct amba_id *id) { - int ret; + int ret, trace_id; void __iomem *base; struct device *dev =3D &adev->dev; struct coresight_platform_data *pdata =3D NULL; @@ -922,12 +898,22 @@ static int stm_probe(struct amba_device *adev, const = struct amba_id *id) goto stm_unregister; } =20 + trace_id =3D coresight_trace_id_get_system_id(); + if (trace_id < 0) { + ret =3D trace_id; + goto cs_unregister; + } + drvdata->traceid =3D (u8)trace_id; + pm_runtime_put(&adev->dev); =20 dev_info(&drvdata->csdev->dev, "%s initialized\n", (char *)coresight_get_uci_data(id)); return 0; =20 +cs_unregister: + coresight_unregister(drvdata->csdev); + stm_unregister: stm_unregister_device(&drvdata->stm); return ret; @@ -937,6 +923,7 @@ static void stm_remove(struct amba_device *adev) { struct stm_drvdata *drvdata =3D dev_get_drvdata(&adev->dev); =20 + coresight_trace_id_put_system_id(drvdata->traceid); coresight_unregister(drvdata->csdev); =20 stm_unregister_device(&drvdata->stm); --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35846C46467 for ; Mon, 16 Jan 2023 12:50:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230470AbjAPMuN (ORCPT ); Mon, 16 Jan 2023 07:50:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230458AbjAPMtp (ORCPT ); Mon, 16 Jan 2023 07:49:45 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A1CD1E5F6 for ; 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charset="utf-8" The trace ID API is now used to allocate trace IDs for ETM4.x / ETE devices. For perf sessions, these will be allocated on enable, and released on disable. For sysfs sessions, these will be allocated on enable, but only released on reset. This allows the sysfs session to interrogate the Trace ID used after the session is over - maintaining functional consistency with the previous allocation scheme. The trace ID will also be allocated on read of the mgmt/trctraceid file. This ensures that if perf or sysfs read this before enabling trace, the value will be the one used for the trace session. Trace ID initialisation is removed from the _probe() function. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Reported-by: kernel test robot --- .../coresight/coresight-etm4x-core.c | 73 +++++++++++++++++-- .../coresight/coresight-etm4x-sysfs.c | 27 ++++++- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + 3 files changed, 93 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 1cc052979e01..370826179c0b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -42,6 +42,7 @@ #include "coresight-etm4x-cfg.h" #include "coresight-self-hosted-trace.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" =20 static int boot_enable; module_param(boot_enable, int, 0444); @@ -237,6 +238,30 @@ static int etm4_trace_id(struct coresight_device *csde= v) return drvdata->trcid; } =20 +int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) +{ + int trace_id; + + /* + * This will allocate a trace ID to the cpu, + * or return the one currently allocated. + * The trace id function has its own lock + */ + trace_id =3D coresight_trace_id_get_cpu_id(drvdata->cpu); + if (IS_VALID_CS_TRACE_ID(trace_id)) + drvdata->trcid =3D (u8)trace_id; + else + dev_err(&drvdata->csdev->dev, + "Failed to allocate trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + return trace_id; +} + +void etm4_release_trace_id(struct etmv4_drvdata *drvdata) +{ + coresight_trace_id_put_cpu_id(drvdata->cpu); +} + struct etm4_enable_arg { struct etmv4_drvdata *drvdata; int rc; @@ -720,7 +745,7 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, static int etm4_enable_perf(struct coresight_device *csdev, struct perf_event *event) { - int ret =3D 0; + int ret =3D 0, trace_id; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); =20 if (WARN_ON_ONCE(drvdata->cpu !=3D smp_processor_id())) { @@ -732,6 +757,24 @@ static int etm4_enable_perf(struct coresight_device *c= sdev, ret =3D etm4_parse_event_config(csdev, event); if (ret) goto out; + + /* + * perf allocates cpu ids as part of _setup_aux() - device needs to use + * the allocated ID. This reads the current version without allocation. + * + * This does not use the trace id lock to prevent lock_dep issues + * with perf locks - we know the ID cannot change until perf shuts down + * the session + */ + trace_id =3D coresight_trace_id_read_cpu_id(drvdata->cpu); + if (!IS_VALID_CS_TRACE_ID(trace_id)) { + dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + ret =3D -EINVAL; + goto out; + } + drvdata->trcid =3D (u8)trace_id; + /* And enable it */ ret =3D etm4_enable_hw(drvdata); =20 @@ -756,6 +799,11 @@ static int etm4_enable_sysfs(struct coresight_device *= csdev) =20 spin_lock(&drvdata->spinlock); =20 + /* sysfs needs to read and allocate a trace ID */ + ret =3D etm4_read_alloc_trace_id(drvdata); + if (ret < 0) + goto unlock_sysfs_enable; + /* * Executing etm4_enable_hw on the cpu whose ETM is being enabled * ensures that register writes occur when cpu is powered. @@ -767,6 +815,11 @@ static int etm4_enable_sysfs(struct coresight_device *= csdev) ret =3D arg.rc; if (!ret) drvdata->sticky_enable =3D true; + + if (ret) + etm4_release_trace_id(drvdata); + +unlock_sysfs_enable: spin_unlock(&drvdata->spinlock); =20 if (!ret) @@ -898,6 +951,11 @@ static int etm4_disable_perf(struct coresight_device *= csdev, /* TRCVICTLR::SSSTATUS, bit[9] */ filters->ssstatus =3D (control & BIT(9)); =20 + /* + * perf will release trace ids when _free_aux() is + * called at the end of the session. + */ + return 0; } =20 @@ -923,6 +981,13 @@ static void etm4_disable_sysfs(struct coresight_device= *csdev) spin_unlock(&drvdata->spinlock); cpus_read_unlock(); =20 + /* + * we only release trace IDs when resetting sysfs. + * This permits sysfs users to read the trace ID after the trace + * session has completed. This maintains operational behaviour with + * prior trace id allocation method + */ + dev_dbg(&csdev->dev, "ETM tracing disabled\n"); } =20 @@ -1565,11 +1630,6 @@ static int etm4_dying_cpu(unsigned int cpu) return 0; } =20 -static void etm4_init_trace_id(struct etmv4_drvdata *drvdata) -{ - drvdata->trcid =3D coresight_get_trace_id(drvdata->cpu); -} - static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) { int i, ret =3D 0; @@ -1946,7 +2006,6 @@ static int etm4_add_coresight_dev(struct etm4_init_ar= g *init_arg) if (!desc.name) return -ENOMEM; =20 - etm4_init_trace_id(drvdata); etm4_set_default(&drvdata->config); =20 pdata =3D coresight_get_platform_data(dev); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index 9cac848cffaf..5e62aa40ecd0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -266,10 +266,11 @@ static ssize_t reset_store(struct device *dev, config->vmid_mask0 =3D 0x0; config->vmid_mask1 =3D 0x0; =20 - drvdata->trcid =3D drvdata->cpu + 1; - spin_unlock(&drvdata->spinlock); =20 + /* for sysfs - only release trace id when resetting */ + etm4_release_trace_id(drvdata); + cscfg_csdev_reset_feats(to_coresight_device(dev)); =20 return size; @@ -2392,6 +2393,26 @@ static struct attribute *coresight_etmv4_attrs[] =3D= { NULL, }; =20 +/* + * Trace ID allocated dynamically on enable - but also allocate on read + * in case sysfs or perf read before enable to ensure consistent metadata + * information for trace decode + */ +static ssize_t trctraceid_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int trace_id; + struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + trace_id =3D etm4_read_alloc_trace_id(drvdata); + if (trace_id < 0) + return trace_id; + + return sysfs_emit(buf, "0x%x\n", trace_id); +} +static DEVICE_ATTR_RO(trctraceid); + struct etmv4_reg { struct coresight_device *csdev; u32 offset; @@ -2528,7 +2549,7 @@ static struct attribute *coresight_etmv4_mgmt_attrs[]= =3D { coresight_etm4x_reg(trcpidr3, TRCPIDR3), coresight_etm4x_reg(trcoslsr, TRCOSLSR), coresight_etm4x_reg(trcconfig, TRCCONFIGR), - coresight_etm4x_reg(trctraceid, TRCTRACEIDR), + &dev_attr_trctraceid.attr, coresight_etm4x_reg(trcdevarch, TRCDEVARCH), NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 4b21bb79f168..434f4e95ee17 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1095,4 +1095,7 @@ static inline bool etm4x_is_ete(struct etmv4_drvdata = *drvdata) { return drvdata->arch >=3D ETM_ARCH_ETE; } + +int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata); +void etm4_release_trace_id(struct etmv4_drvdata *drvdata); #endif --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50711C46467 for ; Mon, 16 Jan 2023 12:50:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230482AbjAPMuV (ORCPT ); Mon, 16 Jan 2023 07:50:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230469AbjAPMtp (ORCPT ); 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Mon, 16 Jan 2023 04:49:40 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v7 06/15] coresight: etm3x: Update ETM3 driver to use Trace ID API Date: Mon, 16 Jan 2023 12:49:19 +0000 Message-Id: <20230116124928.5440-7-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230116124928.5440-1-mike.leach@linaro.org> References: <20230116124928.5440-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use the TraceID API to allocate ETM trace IDs dynamically. As with the etm4x we allocate on enable / disable for perf, allocate on enable / reset for sysfs. Additionally we allocate on sysfs file read as both perf and sysfs can read the ID before enabling the hardware. Remove sysfs option to write trace ID - which is inconsistent with both the dynamic allocation method and the fixed allocation method previously used. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Reported-by: kernel test robot --- drivers/hwtracing/coresight/coresight-etm.h | 2 + .../coresight/coresight-etm3x-core.c | 72 +++++++++++++++++-- .../coresight/coresight-etm3x-sysfs.c | 27 ++----- 3 files changed, 75 insertions(+), 26 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracin= g/coresight/coresight-etm.h index f3ab96eaf44e..3667428d38b6 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -287,4 +287,6 @@ int etm_get_trace_id(struct etm_drvdata *drvdata); void etm_set_default(struct etm_config *config); void etm_config_trace_mode(struct etm_config *config); struct etm_config *get_etm_config(struct etm_drvdata *drvdata); +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata); +void etm_release_trace_id(struct etm_drvdata *drvdata); #endif diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/h= wtracing/coresight/coresight-etm3x-core.c index d0ab9933472b..090b6fbf6305 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -32,6 +32,7 @@ =20 #include "coresight-etm.h" #include "coresight-etm-perf.h" +#include "coresight-trace-id.h" =20 /* * Not really modular but using module_param is the easiest way to @@ -490,16 +491,59 @@ static int etm_trace_id(struct coresight_device *csde= v) return etm_get_trace_id(drvdata); } =20 +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata) +{ + int trace_id; + + /* + * This will allocate a trace ID to the cpu, + * or return the one currently allocated. + * + * trace id function has its own lock + */ + trace_id =3D coresight_trace_id_get_cpu_id(drvdata->cpu); + if (IS_VALID_CS_TRACE_ID(trace_id)) + drvdata->traceid =3D (u8)trace_id; + else + dev_err(&drvdata->csdev->dev, + "Failed to allocate trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + return trace_id; +} + +void etm_release_trace_id(struct etm_drvdata *drvdata) +{ + coresight_trace_id_put_cpu_id(drvdata->cpu); +} + static int etm_enable_perf(struct coresight_device *csdev, struct perf_event *event) { struct etm_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + int trace_id; =20 if (WARN_ON_ONCE(drvdata->cpu !=3D smp_processor_id())) return -EINVAL; =20 /* Configure the tracer based on the session's specifics */ etm_parse_event_config(drvdata, event); + + /* + * perf allocates cpu ids as part of _setup_aux() - device needs to use + * the allocated ID. This reads the current version without allocation. + * + * This does not use the trace id lock to prevent lock_dep issues + * with perf locks - we know the ID cannot change until perf shuts down + * the session + */ + trace_id =3D coresight_trace_id_read_cpu_id(drvdata->cpu); + if (!IS_VALID_CS_TRACE_ID(trace_id)) { + dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + return -EINVAL; + } + drvdata->traceid =3D (u8)trace_id; + /* And enable it */ return etm_enable_hw(drvdata); } @@ -512,6 +556,11 @@ static int etm_enable_sysfs(struct coresight_device *c= sdev) =20 spin_lock(&drvdata->spinlock); =20 + /* sysfs needs to allocate and set a trace ID */ + ret =3D etm_read_alloc_trace_id(drvdata); + if (ret < 0) + goto unlock_enable_sysfs; + /* * Configure the ETM only if the CPU is online. If it isn't online * hw configuration will take place on the local CPU during bring up. @@ -528,6 +577,10 @@ static int etm_enable_sysfs(struct coresight_device *c= sdev) ret =3D -ENODEV; } =20 + if (ret) + etm_release_trace_id(drvdata); + +unlock_enable_sysfs: spin_unlock(&drvdata->spinlock); =20 if (!ret) @@ -611,6 +664,12 @@ static void etm_disable_perf(struct coresight_device *= csdev) coresight_disclaim_device_unlocked(csdev); =20 CS_LOCK(drvdata->base); + + /* + * perf will release trace ids when _free_aux() + * is called at the end of the session + */ + } =20 static void etm_disable_sysfs(struct coresight_device *csdev) @@ -635,6 +694,13 @@ static void etm_disable_sysfs(struct coresight_device = *csdev) spin_unlock(&drvdata->spinlock); cpus_read_unlock(); =20 + /* + * we only release trace IDs when resetting sysfs. + * This permits sysfs users to read the trace ID after the trace + * session has completed. This maintains operational behaviour with + * prior trace id allocation method + */ + dev_dbg(&csdev->dev, "ETM tracing disabled\n"); } =20 @@ -781,11 +847,6 @@ static void etm_init_arch_data(void *info) CS_LOCK(drvdata->base); } =20 -static void etm_init_trace_id(struct etm_drvdata *drvdata) -{ - drvdata->traceid =3D coresight_get_trace_id(drvdata->cpu); -} - static int __init etm_hp_setup(void) { int ret; @@ -871,7 +932,6 @@ static int etm_probe(struct amba_device *adev, const st= ruct amba_id *id) if (etm_arch_supported(drvdata->arch) =3D=3D false) return -EINVAL; =20 - etm_init_trace_id(drvdata); etm_set_default(&drvdata->config); =20 pdata =3D coresight_get_platform_data(dev); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm3x-sysfs.c index fd81eca3ec18..2f271b7fb048 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -85,6 +85,7 @@ static ssize_t reset_store(struct device *dev, } =20 etm_set_default(config); + etm_release_trace_id(drvdata); spin_unlock(&drvdata->spinlock); } =20 @@ -1189,30 +1190,16 @@ static DEVICE_ATTR_RO(cpu); static ssize_t traceid_show(struct device *dev, struct device_attribute *attr, char *buf) { - unsigned long val; - struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); - - val =3D etm_get_trace_id(drvdata); - - return sprintf(buf, "%#lx\n", val); -} - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; + int trace_id; struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); =20 - ret =3D kstrtoul(buf, 16, &val); - if (ret) - return ret; + trace_id =3D etm_read_alloc_trace_id(drvdata); + if (trace_id < 0) + return trace_id; =20 - drvdata->traceid =3D val & ETM_TRACEID_MASK; - return size; + return sysfs_emit(buf, "%#x\n", trace_id); } -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); =20 static struct attribute *coresight_etm_attrs[] =3D { &dev_attr_nr_addr_cmp.attr, --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E50DC54EBE for ; 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Mon, 16 Jan 2023 04:49:41 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v7 07/15] coresight: etmX.X: stm: Remove trace_id() callback Date: Mon, 16 Jan 2023 12:49:20 +0000 Message-Id: <20230116124928.5440-8-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230116124928.5440-1-mike.leach@linaro.org> References: <20230116124928.5440-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" CoreSight sources provide a callback (.trace_id) in the standard source ops which returns the ID to the core code. This was used to check that sources all had a unique Trace ID. Uniqueness is now gauranteed by the Trace ID allocation system, and the check code has been removed from the core. This patch removes the unneeded and unused .trace_id source ops from the ops structure and implementations in etm3x, etm4x and stm. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Reported-by: kernel test robot --- drivers/hwtracing/coresight/coresight-etm.h | 1 - .../coresight/coresight-etm3x-core.c | 37 ------------------- .../coresight/coresight-etm4x-core.c | 8 ---- drivers/hwtracing/coresight/coresight-stm.c | 8 ---- include/linux/coresight.h | 3 -- 5 files changed, 57 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracin= g/coresight/coresight-etm.h index 3667428d38b6..9a0d08b092ae 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -283,7 +283,6 @@ static inline unsigned int etm_readl(struct etm_drvdata= *drvdata, u32 off) } =20 extern const struct attribute_group *coresight_etm_groups[]; -int etm_get_trace_id(struct etm_drvdata *drvdata); void etm_set_default(struct etm_config *config); void etm_config_trace_mode(struct etm_config *config); struct etm_config *get_etm_config(struct etm_drvdata *drvdata); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/h= wtracing/coresight/coresight-etm3x-core.c index 090b6fbf6305..afc57195ee52 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -455,42 +455,6 @@ static int etm_cpu_id(struct coresight_device *csdev) return drvdata->cpu; } =20 -int etm_get_trace_id(struct etm_drvdata *drvdata) -{ - unsigned long flags; - int trace_id =3D -1; - struct device *etm_dev; - - if (!drvdata) - goto out; - - etm_dev =3D drvdata->csdev->dev.parent; - if (!local_read(&drvdata->mode)) - return drvdata->traceid; - - pm_runtime_get_sync(etm_dev); - - spin_lock_irqsave(&drvdata->spinlock, flags); - - CS_UNLOCK(drvdata->base); - trace_id =3D (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK); - CS_LOCK(drvdata->base); - - spin_unlock_irqrestore(&drvdata->spinlock, flags); - pm_runtime_put(etm_dev); - -out: - return trace_id; - -} - -static int etm_trace_id(struct coresight_device *csdev) -{ - struct etm_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); - - return etm_get_trace_id(drvdata); -} - int etm_read_alloc_trace_id(struct etm_drvdata *drvdata) { int trace_id; @@ -737,7 +701,6 @@ static void etm_disable(struct coresight_device *csdev, =20 static const struct coresight_ops_source etm_source_ops =3D { .cpu_id =3D etm_cpu_id, - .trace_id =3D etm_trace_id, .enable =3D etm_enable, .disable =3D etm_disable, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 370826179c0b..1827a5b32743 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -231,13 +231,6 @@ static int etm4_cpu_id(struct coresight_device *csdev) return drvdata->cpu; } =20 -static int etm4_trace_id(struct coresight_device *csdev) -{ - struct etmv4_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); - - return drvdata->trcid; -} - int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) { int trace_id; @@ -1021,7 +1014,6 @@ static void etm4_disable(struct coresight_device *csd= ev, =20 static const struct coresight_ops_source etm4_source_ops =3D { .cpu_id =3D etm4_cpu_id, - .trace_id =3D etm4_trace_id, .enable =3D etm4_enable, .disable =3D etm4_disable, }; diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracin= g/coresight/coresight-stm.c index 6af1b996af6f..66a614c5492c 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -281,15 +281,7 @@ static void stm_disable(struct coresight_device *csdev, } } =20 -static int stm_trace_id(struct coresight_device *csdev) -{ - struct stm_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); - - return drvdata->traceid; -} - static const struct coresight_ops_source stm_source_ops =3D { - .trace_id =3D stm_trace_id, .enable =3D stm_enable, .disable =3D stm_disable, }; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 1554021231f9..e241eb88dfb9 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -314,14 +314,11 @@ struct coresight_ops_link { * Operations available for sources. * @cpu_id: returns the value of the CPU number this component * is associated to. - * @trace_id: returns the value of the component's trace ID as known - * to the HW. * @enable: enables tracing for a source. * @disable: disables tracing for a source. */ struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); - int (*trace_id)(struct coresight_device *csdev); int (*enable)(struct coresight_device *csdev, struct perf_event *event, u32 mode); void (*disable)(struct coresight_device *csdev, --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D69FC54EBE for ; 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Mon, 16 Jan 2023 04:49:42 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v7 08/15] coresight: trace id: Remove legacy get trace ID function. Date: Mon, 16 Jan 2023 12:49:21 +0000 Message-Id: <20230116124928.5440-9-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230116124928.5440-1-mike.leach@linaro.org> References: <20230116124928.5440-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Removes legacy coresight_get_trace_id() function now its use has been removed from the ETM code. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Reported-by: kernel test robot --- include/linux/coresight-pmu.h | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index ffff4e6277e5..624f4843453e 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -8,7 +8,6 @@ #define _LINUX_CORESIGHT_PMU_H =20 #define CORESIGHT_ETM_PMU_NAME "cs_etm" -#define CORESIGHT_ETM_PMU_SEED 0x10 =20 /* * The legacy Trace ID system based on fixed calculation from the cpu @@ -44,15 +43,4 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 =20 -static inline int coresight_get_trace_id(int cpu) -{ - /* - * A trace ID of value 0 is invalid, so let's start at some - * random value that fits in 7 bits and go from there. Since - * the common convention is to have data trace IDs be I(N) + 1, - * set instruction trace IDs as a function of the CPU number. - */ - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); -} - #endif --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F6C8C63797 for ; Mon, 16 Jan 2023 12:50:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231228AbjAPMuh (ORCPT ); Mon, 16 Jan 2023 07:50:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230494AbjAPMtr (ORCPT ); Mon, 16 Jan 2023 07:49:47 -0500 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 119BE1E5E1 for ; Mon, 16 Jan 2023 04:49:44 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id o15so19899731wmr.4 for ; Mon, 16 Jan 2023 04:49:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=XPvSQ2akOg9lVFYLsk36HR8GI0OejzxG35eUcUs1NTE=; b=Go7EpvZDL5KdZqJRSWvi42j/10yJvz5yCDa9bfWfx+cuKLlgINAjC06DMTOFEw0DG7 7ee+Uhm2/Gsn/wWBhIVdnk02W1d/i3hQom7RFg0tIj5kWE3v2CLwZNDGhGNsqnMqKbh7 3/mvGkL7FG5ZyVoeebkBPGBorTP5KT63AdtuXTllWpJ4lgrJSi28SMQSmgbT/dWCWLOK 0UctEviq7fW2q95SUD4rYRHdyxdr8WyvdfpcM2pPRHz6zcpI2SIR9aDC5q7oLT9cViDF n+EMYzgC3TrGun2KXtho4Xt1DBwHxqDpl2+AI6SNzMAll4F7/zHHYdjE7mkxtk2U8lQf oygw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=XPvSQ2akOg9lVFYLsk36HR8GI0OejzxG35eUcUs1NTE=; b=nJXZnJa4l4JUizGPPxwFpv6CzwRo5BCSFCxg6cbBWeO9PNcJJi0HaVD9sOlh0Dar+r l6xSmABbVTvaCAWFVTP9eFB7ZQTSgF0sYTIIjonZJ3yjrj5FogOBucFYEOzE4EVm4Mj+ yE1tGA83QFtAeZz5jsQmp5vARxSsYf8eKUCATJ04gxlkWSepZ8tWOD2WboEhSNlqZkzW vgt3EzhyCsLIpignBqygsextcwHOI/s8N5ZSt/xIkgdpnij4vmKpALxeIFVRTfTXzJU+ 24+93knPyZ05aaAQccBR5OShNuaNFtVX36+Lwy7KAs2SrSbv+2tm7epKldMdLUyYW5Ij aSPg== X-Gm-Message-State: AFqh2ko12Vj3gEq3N7ib8pGbZ8QIpNGk9si+tZlqUyc5zAIGakDklTis 6JTznBU1yDHz03ZU4wXAjokUTg== X-Google-Smtp-Source: AMrXdXuMijzCQsuEGb76/3RaU/WnZPbQFRAea6UQVFgxT5XQIU2RuuBD1XvdK5GHtEYcwetepCmbDQ== X-Received: by 2002:a7b:c302:0:b0:3d3:5c9e:6b27 with SMTP id k2-20020a7bc302000000b003d35c9e6b27mr8152556wmj.12.1673873384375; Mon, 16 Jan 2023 04:49:44 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:6c91:710d:9433:e868]) by smtp.gmail.com with ESMTPSA id fl12-20020a05600c0b8c00b003dab40f9eafsm6896832wmb.35.2023.01.16.04.49.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 04:49:43 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v7 09/15] perf: cs-etm: Move mapping of Trace ID and cpu into helper function Date: Mon, 16 Jan 2023 12:49:22 +0000 Message-Id: <20230116124928.5440-10-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230116124928.5440-1-mike.leach@linaro.org> References: <20230116124928.5440-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The information to associate Trace ID and CPU will be changing. Drivers will start outputting this as a hardware ID packet in the data file which if present will be used in preference to the AUXINFO values. To prepare for this we provide a helper functions to do the individual ID mapping, and one to extract the IDs from the completed metadata blocks. Signed-off-by: Mike Leach Reviewed-by: James Clark Acked-by: Suzuki K Poulose Reported-by: kernel test robot --- tools/include/linux/coresight-pmu.h | 5 ++ tools/perf/util/cs-etm.c | 91 +++++++++++++++++++---------- tools/perf/util/cs-etm.h | 14 ++++- 3 files changed, 77 insertions(+), 33 deletions(-) diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/core= sight-pmu.h index 6c2fd6cc5a98..db9c7c0abb6a 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -7,9 +7,14 @@ #ifndef _LINUX_CORESIGHT_PMU_H #define _LINUX_CORESIGHT_PMU_H =20 +#include + #define CORESIGHT_ETM_PMU_NAME "cs_etm" #define CORESIGHT_ETM_PMU_SEED 0x10 =20 +/* CoreSight trace ID is currently the bottom 7 bits of the value */ +#define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0) + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 33303d03c2fa..f77260b9253e 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -193,6 +193,30 @@ int cs_etm__get_pid_fmt(u8 trace_chan_id, u64 *pid_fmt) return 0; } =20 +static int cs_etm__map_trace_id(u8 trace_chan_id, u64 *cpu_metadata) +{ + struct int_node *inode; + + /* Get an RB node for this CPU */ + inode =3D intlist__findnew(traceid_list, trace_chan_id); + + /* Something went wrong, no need to continue */ + if (!inode) + return -ENOMEM; + + /* + * The node for that CPU should not be taken. + * Back out if that's the case. + */ + if (inode->priv) + return -EINVAL; + + /* All good, associate the traceID with the metadata pointer */ + inode->priv =3D cpu_metadata; + + return 0; +} + void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, u8 trace_chan_id) { @@ -2746,6 +2770,36 @@ static int cs_etm__queue_aux_records(struct perf_ses= sion *session) return 0; } =20 +/* map trace ids to correct metadata block, from information in metadata */ +static int cs_etm__map_trace_ids_metadata(int num_cpu, u64 **metadata) +{ + u64 cs_etm_magic; + u8 trace_chan_id; + int i, err; + + for (i =3D 0; i < num_cpu; i++) { + cs_etm_magic =3D metadata[i][CS_ETM_MAGIC]; + switch (cs_etm_magic) { + case __perf_cs_etmv3_magic: + trace_chan_id =3D (u8)((metadata[i][CS_ETM_ETMTRACEIDR]) & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + case __perf_cs_etmv4_magic: + case __perf_cs_ete_magic: + trace_chan_id =3D (u8)((metadata[i][CS_ETMV4_TRCTRACEIDR]) & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + default: + /* unknown magic number */ + return -EINVAL; + } + err =3D cs_etm__map_trace_id(trace_chan_id, metadata[i]); + if (err) + return err; + } + return 0; +} + int cs_etm__process_auxtrace_info_full(union perf_event *event, struct perf_session *session) { @@ -2755,7 +2809,7 @@ int cs_etm__process_auxtrace_info_full(union perf_eve= nt *event, int event_header_size =3D sizeof(struct perf_event_header); int total_size =3D auxtrace_info->header.size; int priv_size =3D 0; - int num_cpu, trcidr_idx; + int num_cpu; int err =3D 0; int i, j; u64 *ptr =3D NULL; @@ -2794,23 +2848,13 @@ int cs_etm__process_auxtrace_info_full(union perf_e= vent *event, cs_etm__create_meta_blk(ptr, &i, CS_ETM_PRIV_MAX, CS_ETM_NR_TRC_PARAMS_V0); - - /* The traceID is our handle */ - trcidr_idx =3D CS_ETM_ETMTRACEIDR; - } else if (ptr[i] =3D=3D __perf_cs_etmv4_magic) { metadata[j] =3D cs_etm__create_meta_blk(ptr, &i, CS_ETMV4_PRIV_MAX, CS_ETMV4_NR_TRC_PARAMS_V0); - - /* The traceID is our handle */ - trcidr_idx =3D CS_ETMV4_TRCTRACEIDR; } else if (ptr[i] =3D=3D __perf_cs_ete_magic) { metadata[j] =3D cs_etm__create_meta_blk(ptr, &i, CS_ETE_PRIV_MAX, -1); - - /* ETE shares first part of metadata with ETMv4 */ - trcidr_idx =3D CS_ETMV4_TRCTRACEIDR; } else { ui__error("CS ETM Trace: Unrecognised magic number %#"PRIx64". File cou= ld be from a newer version of perf.\n", ptr[i]); @@ -2822,26 +2866,6 @@ int cs_etm__process_auxtrace_info_full(union perf_ev= ent *event, err =3D -ENOMEM; goto err_free_metadata; } - - /* Get an RB node for this CPU */ - inode =3D intlist__findnew(traceid_list, metadata[j][trcidr_idx]); - - /* Something went wrong, no need to continue */ - if (!inode) { - err =3D -ENOMEM; - goto err_free_metadata; - } - - /* - * The node for that CPU should not be taken. - * Back out if that's the case. - */ - if (inode->priv) { - err =3D -EINVAL; - goto err_free_metadata; - } - /* All good, associate the traceID with the metadata pointer */ - inode->priv =3D metadata[j]; } =20 /* @@ -2919,6 +2943,11 @@ int cs_etm__process_auxtrace_info_full(union perf_ev= ent *event, if (err) goto err_delete_thread; =20 + /* before aux records are queued, need to map metadata to trace IDs */ + err =3D cs_etm__map_trace_ids_metadata(num_cpu, metadata); + if (err) + goto err_delete_thread; + err =3D cs_etm__queue_aux_records(session); if (err) goto err_delete_thread; diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 5da50d5dae6b..e0a5eb1f3ce7 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -29,13 +29,17 @@ enum { /* * Update the version for new format. * - * New version 1 format adds a param count to the per cpu metadata. + * Version 1: format adds a param count to the per cpu metadata. * This allows easy adding of new metadata parameters. * Requires that new params always added after current ones. * Also allows client reader to handle file versions that are different by * checking the number of params in the file vs the number expected. + * + * Version 2: Drivers will use PERF_RECORD_AUX_OUTPUT_HW_ID to output + * CoreSight Trace ID. ...TRACEIDR metadata will be set to unused ID. */ -#define CS_HEADER_CURRENT_VERSION 1 +#define CS_HEADER_CURRENT_VERSION 2 +#define CS_AUX_HW_ID_VERSION_MIN 2 =20 /* Beginning of header common to both ETMv3 and V4 */ enum { @@ -86,6 +90,12 @@ enum { CS_ETE_PRIV_MAX }; =20 +/* + * Check for valid CoreSight trace ID. If an invalid value is present in t= he metadata, + * then IDs are present in the hardware ID packet in the data file. + */ +#define CS_IS_VALID_TRACE_ID(id) ((id > 0) && (id < 0x70)) + /* * ETMv3 exception encoding number: * See Embedded Trace Macrocell specification (ARM IHI 0014Q) --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D688EC46467 for ; Mon, 16 Jan 2023 12:50:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231130AbjAPMuq (ORCPT ); Mon, 16 Jan 2023 07:50:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230509AbjAPMtt (ORCPT ); Mon, 16 Jan 2023 07:49:49 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDFAD1E9E3 for ; Mon, 16 Jan 2023 04:49:46 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id ay40so19923277wmb.2 for ; Mon, 16 Jan 2023 04:49:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=JOkIyMrj9jAVnq1u2b/d95NeRDzS4KUPTPtP8tjZN5c=; b=JCWYeAnBNl1aj8s6McMHJuFzuniVzPmUKtFAlXM2zNUPKDmpEh5dUm1v76pvDap18Z lfhQQY9WNPKuYxLN36xpJJfAgBd88e38dzDtON/QPIb25J7eJkneH2p71/3rn9VrOg5R BnwuSzAjYAWqx5VRenlKDX5Z2Cgr8+ExiVmJH36O5bTColvwIw4cOKAg0KIWq1qfFpSD kPlvq1tW10Y6X7PWr3NzhfEtJcR1tKO3pB+I1EAz9AKw3pxtwOPMh0EdILua2VTXKOoD Ko3dzBLQy/1WHHfOaugIzsm8YNg/FygM7ic0Q39lM8fMieXXEqRaXtdZFa6cTEg73djX WK0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=JOkIyMrj9jAVnq1u2b/d95NeRDzS4KUPTPtP8tjZN5c=; b=PqqJzErEZnqkNv0zgnBsAQiERMUgGluB79un+2OdK8LHitnxL0R7Sk6I32ZVJXGZu7 f5AvFAz4fsjZeBLGqDVHApZJ+UurFbc1iOM/SchxwrGKnGSMf0eBvknpQ1bJcoRML6xS fzwGp9uYaRO1VWnDtdKCOp8IP16R+k+fs5IoUhRZV9yO1YWDDmGHmPbWmU6bS1pBJQ4y 2D8zsnN9OgDUMxj16pBZVya9cogrG3+EV5xPzAlYh7xez+xsxo0eOmSGR/qowXgFZF8O PExKvhFtdLxEQrCOcFxC3YEwzMJ1I4ztUAtoCq6k/iKoOmZOv+zR56Ylw2S//xPltFtJ yXqA== X-Gm-Message-State: AFqh2krEduHFsZL5x+8XNIm96c0TeV1WvZS00FM9NEhgN7MBhkbCNHnG z3gYYQciHQ7HrZu+PHx3CAFPOw== X-Google-Smtp-Source: AMrXdXubYrQOuZrpFj2z6HUARVjepeRLL6DQV0tuqOuqBsyGloACaORyytKdGuSx4grwNjdsq/s0kw== X-Received: by 2002:a05:600c:3d12:b0:3d0:bd9:edd4 with SMTP id bh18-20020a05600c3d1200b003d00bd9edd4mr66606829wmb.0.1673873385513; Mon, 16 Jan 2023 04:49:45 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:6c91:710d:9433:e868]) by smtp.gmail.com with ESMTPSA id fl12-20020a05600c0b8c00b003dab40f9eafsm6896832wmb.35.2023.01.16.04.49.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 04:49:44 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v7 10/15] perf: cs-etm: Update record event to use new Trace ID protocol Date: Mon, 16 Jan 2023 12:49:23 +0000 Message-Id: <20230116124928.5440-11-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230116124928.5440-1-mike.leach@linaro.org> References: <20230116124928.5440-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Trace IDs are now dynamically allocated. Previously used the static association algorithm that is no longer used. The 'cpu * 2 + seed' was outdated and broken for systems with high core counts (>46). as it did not scale and was broken for larger core counts. Trace ID will now be sent in PERF_RECORD_AUX_OUTPUT_HW_ID record. Legacy ID algorithm renamed and retained for limited backward compatibility use. Signed-off-by: Mike Leach Reviewed-by: James Clark Acked-by: Suzuki K Poulose Reported-by: kernel test robot --- tools/include/linux/coresight-pmu.h | 30 +++++++++++++++++------------ tools/perf/arch/arm/util/cs-etm.c | 21 ++++++++++++-------- 2 files changed, 31 insertions(+), 20 deletions(-) diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/core= sight-pmu.h index db9c7c0abb6a..307f357defe9 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -10,11 +10,28 @@ #include =20 #define CORESIGHT_ETM_PMU_NAME "cs_etm" -#define CORESIGHT_ETM_PMU_SEED 0x10 + +/* + * The legacy Trace ID system based on fixed calculation from the cpu + * number. This has been replaced by drivers using a dynamic allocation + * system - but need to retain the legacy algorithm for backward comparibi= lity + * in certain situations:- + * a) new perf running on older systems that generate the legacy mapping + * b) older tools e.g. simpleperf in Android, that may not update at the s= ame + * time as the kernel. + */ +#define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2)) =20 /* CoreSight trace ID is currently the bottom 7 bits of the value */ #define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0) =20 +/* + * perf record will set the legacy meta data values as unused initially. + * This allows perf report to manage the decoders created when dynamic + * allocation in operation. + */ +#define CORESIGHT_TRACE_ID_UNUSED_FLAG BIT(31) + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. @@ -39,15 +56,4 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 =20 -static inline int coresight_get_trace_id(int cpu) -{ - /* - * A trace ID of value 0 is invalid, so let's start at some - * random value that fits in 7 bits and go from there. Since - * the common convention is to have data trace IDs be I(N) + 1, - * set instruction trace IDs as a function of the CPU number. - */ - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); -} - #endif diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/c= s-etm.c index a346d5f3dafa..c7e4b543259f 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -421,13 +421,16 @@ static int cs_etm_recording_options(struct auxtrace_r= ecord *itr, evlist__to_front(evlist, cs_etm_evsel); =20 /* - * In the case of per-cpu mmaps, we need the CPU on the - * AUX event. We also need the contextID in order to be notified + * get the CPU on the sample - need it to associate trace ID in the + * AUX_OUTPUT_HW_ID event, and the AUX event for per-cpu mmaps. + */ + evsel__set_sample_bit(cs_etm_evsel, CPU); + + /* + * Also the case of per-cpu mmaps, need the contextID in order to be noti= fied * when a context switch happened. */ if (!perf_cpu_map__empty(cpus)) { - evsel__set_sample_bit(cs_etm_evsel, CPU); - err =3D cs_etm_set_option(itr, cs_etm_evsel, BIT(ETM_OPT_CTXTID) | BIT(ETM_OPT_TS)); if (err) @@ -633,8 +636,10 @@ static void cs_etm_save_etmv4_header(__u64 data[], str= uct auxtrace_record *itr, =20 /* Get trace configuration register */ data[CS_ETMV4_TRCCONFIGR] =3D cs_etmv4_get_config(itr); - /* Get traceID from the framework */ - data[CS_ETMV4_TRCTRACEIDR] =3D coresight_get_trace_id(cpu); + /* traceID set to legacy version, in case new perf running on older syste= m */ + data[CS_ETMV4_TRCTRACEIDR] =3D + CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) | CORESIGHT_TRACE_ID_UNUSED_FLAG; + /* Get read-only information from sysFS */ data[CS_ETMV4_TRCIDR0] =3D cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0]); @@ -681,9 +686,9 @@ static void cs_etm_get_metadata(int cpu, u32 *offset, magic =3D __perf_cs_etmv3_magic; /* Get configuration register */ info->priv[*offset + CS_ETM_ETMCR] =3D cs_etm_get_config(itr); - /* Get traceID from the framework */ + /* traceID set to legacy value in case new perf running on old system */ info->priv[*offset + CS_ETM_ETMTRACEIDR] =3D - coresight_get_trace_id(cpu); + CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) | CORESIGHT_TRACE_ID_UNUSED_FLAG; /* Get read-only information from sysFS */ info->priv[*offset + CS_ETM_ETMCCER] =3D cs_etm_get_ro(cs_etm_pmu, cpu, --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23532C54EBE for ; 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Mon, 16 Jan 2023 04:49:46 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v7 11/15] kernel: events: Export perf_report_aux_output_id() Date: Mon, 16 Jan 2023 12:49:24 +0000 Message-Id: <20230116124928.5440-12-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230116124928.5440-1-mike.leach@linaro.org> References: <20230116124928.5440-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" CoreSight trace being updated to use the perf_report_aux_output_id() in a similar way to intel-pt. This function in needs export visibility to allow it to be called from kernel loadable modules, which CoreSight may configured to be built as. Signed-off-by: Mike Leach Acked-by: Suzuki K Poulose Acked-by: Peter Zijlstra (Intel) Reported-by: kernel test robot --- kernel/events/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/events/core.c b/kernel/events/core.c index d56328e5080e..f7036ed53b3f 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -9399,6 +9399,7 @@ void perf_report_aux_output_id(struct perf_event *eve= nt, u64 hw_id) =20 perf_output_end(&handle); } +EXPORT_SYMBOL_GPL(perf_report_aux_output_id); =20 static int __perf_event_account_interrupt(struct perf_event *event, int throttle) --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66CD5C46467 for ; Mon, 16 Jan 2023 12:50:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230477AbjAPMuv (ORCPT ); Mon, 16 Jan 2023 07:50:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231151AbjAPMuP (ORCPT ); Mon, 16 Jan 2023 07:50:15 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4683C1E5EC for ; Mon, 16 Jan 2023 04:49:48 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id l41-20020a05600c1d2900b003daf986faaeso2165627wms.3 for ; Mon, 16 Jan 2023 04:49:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=P/3aXwMZwgrau366dBSnrYQn2HN+KNkSdmsKFPNERis=; b=WcLrOdpPRJWzPPLSdP/T3sYpBt4BLf2ygkGl5mntJVPLTIjEOzNqYaFzj9YvrybL7P 7ojjayQsnI2nR+Pel+NaAfZJuXHBOQ6+MwxdLGRvb9tuMxIbdeHfkP50W18XtJiypbZT JUaoQeh1xDoKYu73L4SX6cgcA49vpfp1DSXwSxzJkHPcKoDJCOQ0GWPyF2jS+eBxw2xD zdATP71hE5u6At2F5aX8jho+Zn9dxF/JQ0lPU0A2tLPse6elBauS4GLz+8yQp/16jKXP MI32JHdccugcTQiz+EmUZb3Ffvtsl72lBWRmyNtNgdCLXc+DGXOwcGNBiJvEVrpUX5uc VFZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=P/3aXwMZwgrau366dBSnrYQn2HN+KNkSdmsKFPNERis=; b=ZdFsoKXJHuPm0sDAjSuPBE83FR93ALUpepBXLP1/ELyj+oDf3XSTPVUn8SohTOCHFH Mz9FL9JlrAspXSgGdbNLOGd7lHqu/+lPUv6UV/lgKqKcP/iqMJGx+qcPEw/Md9iIhP+v L8Gz9fAlgH0uDEJ3OSF4V9JNccNLhKD/5Y6h+aGIN4ANWPyK/hp5+OMrB2RcdXRf0g14 NGI3OXMUPeiBQyNSsmDiLRUAvJXyl2NSyPnTqlwyC4B0L/UGlAKtjOsoVVPMCxUWIBOV Ysh3RsWwkkeoGRY5pxTkaN7mTYqtk/Ch7UWhm02U0QPkJbhAHAV1FuB844Hqj6K5BFrL sRlg== X-Gm-Message-State: AFqh2krGrtLIkX2uHR/74rJleCE2WzYZnPijbXibSTehfZ9UItEc7ce8 T5b/MNt4TPBl2NhF6JhK2tE1QQ== X-Google-Smtp-Source: AMrXdXtV/v66cXuERuUEmgGgvcKx9M3mNMAQeYAgkQgx3oI8R/H0gUJ3YlgJewgEaBHA7UxxJ/UKKw== X-Received: by 2002:a1c:f616:0:b0:3da:f88:958f with SMTP id w22-20020a1cf616000000b003da0f88958fmr8122803wmc.10.1673873387786; Mon, 16 Jan 2023 04:49:47 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:6c91:710d:9433:e868]) by smtp.gmail.com with ESMTPSA id fl12-20020a05600c0b8c00b003dab40f9eafsm6896832wmb.35.2023.01.16.04.49.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 04:49:47 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v7 12/15] perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet Date: Mon, 16 Jan 2023 12:49:25 +0000 Message-Id: <20230116124928.5440-13-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230116124928.5440-1-mike.leach@linaro.org> References: <20230116124928.5440-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When using dynamically assigned CoreSight trace IDs the drivers can output the ID / CPU association as a PERF_RECORD_AUX_OUTPUT_HW_ID packet. Update cs-etm decoder to handle this packet by setting the CPU/Trace ID mapping. Signed-off-by: Mike Leach Reviewed-by: James Clark Acked-by: Suzuki K Poulose Reported-by: kernel test robot --- tools/include/linux/coresight-pmu.h | 15 ++ .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 + tools/perf/util/cs-etm.c | 246 ++++++++++++++++-- 3 files changed, 250 insertions(+), 18 deletions(-) diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/core= sight-pmu.h index 307f357defe9..57ba1abf1224 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -32,6 +32,9 @@ */ #define CORESIGHT_TRACE_ID_UNUSED_FLAG BIT(31) =20 +/* Value to set for unused trace ID values */ +#define CORESIGHT_TRACE_ID_UNUSED_VAL 0x7F + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. @@ -56,4 +59,16 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 =20 +/* + * Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload. + * Used to associate a CPU with the CoreSight Trace ID. + * [07:00] - Trace ID - uses 8 bits to make value easy to read in file. + * [59:08] - Unused (SBZ) + * [63:60] - Version + */ +#define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0) +#define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60) + +#define CS_AUX_HW_ID_CURR_VERSION 0 + #endif diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/u= til/cs-etm-decoder/cs-etm-decoder.c index 31fa3b45134a..fa3aa9c0fb2e 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -625,6 +625,7 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_decode= r_params *d_params, switch (t_params->protocol) { case CS_ETM_PROTO_ETMV3: case CS_ETM_PROTO_PTM: + csid =3D (t_params->etmv3.reg_idr & CORESIGHT_TRACE_ID_VAL_MASK); cs_etm_decoder__gen_etmv3_config(t_params, &config_etmv3); decoder->decoder_name =3D (t_params->protocol =3D=3D CS_ETM_PROTO_ETMV3)= ? OCSD_BUILTIN_DCD_ETMV3 : @@ -632,11 +633,13 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_deco= der_params *d_params, trace_config =3D &config_etmv3; break; case CS_ETM_PROTO_ETMV4i: + csid =3D (t_params->etmv4.reg_traceidr & CORESIGHT_TRACE_ID_VAL_MASK); cs_etm_decoder__gen_etmv4_config(t_params, &trace_config_etmv4); decoder->decoder_name =3D OCSD_BUILTIN_DCD_ETMV4I; trace_config =3D &trace_config_etmv4; break; case CS_ETM_PROTO_ETE: + csid =3D (t_params->ete.reg_traceidr & CORESIGHT_TRACE_ID_VAL_MASK); cs_etm_decoder__gen_ete_config(t_params, &trace_config_ete); decoder->decoder_name =3D OCSD_BUILTIN_DCD_ETE; trace_config =3D &trace_config_ete; @@ -645,6 +648,10 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_decod= er_params *d_params, return -1; } =20 + /* if the CPU has no trace ID associated, no decoder needed */ + if (csid =3D=3D CORESIGHT_TRACE_ID_UNUSED_VAL) + return 0; + if (d_params->operation =3D=3D CS_ETM_OPERATION_DECODE) { if (ocsd_dt_create_decoder(decoder->dcd_tree, decoder->decoder_name, diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index f77260b9253e..51f58e7ababd 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -217,6 +217,143 @@ static int cs_etm__map_trace_id(u8 trace_chan_id, u64= *cpu_metadata) return 0; } =20 +static int cs_etm__metadata_get_trace_id(u8 *trace_chan_id, u64 *cpu_metad= ata) +{ + u64 cs_etm_magic =3D cpu_metadata[CS_ETM_MAGIC]; + + switch (cs_etm_magic) { + case __perf_cs_etmv3_magic: + *trace_chan_id =3D (u8)(cpu_metadata[CS_ETM_ETMTRACEIDR] & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + case __perf_cs_etmv4_magic: + case __perf_cs_ete_magic: + *trace_chan_id =3D (u8)(cpu_metadata[CS_ETMV4_TRCTRACEIDR] & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + default: + return -EINVAL; + } + return 0; +} + +/* + * update metadata trace ID from the value found in the AUX_HW_INFO packet. + * This will also clear the CORESIGHT_TRACE_ID_UNUSED_FLAG flag if present. + */ +static int cs_etm__metadata_set_trace_id(u8 trace_chan_id, u64 *cpu_metada= ta) +{ + u64 cs_etm_magic =3D cpu_metadata[CS_ETM_MAGIC]; + + switch (cs_etm_magic) { + case __perf_cs_etmv3_magic: + cpu_metadata[CS_ETM_ETMTRACEIDR] =3D trace_chan_id; + break; + case __perf_cs_etmv4_magic: + case __perf_cs_ete_magic: + cpu_metadata[CS_ETMV4_TRCTRACEIDR] =3D trace_chan_id; + break; + + default: + return -EINVAL; + } + return 0; +} + +/* + * FIELD_GET (linux/bitfield.h) not available outside kernel code, + * and the header contains too many dependencies to just copy over, + * so roll our own based on the original + */ +#define __bf_shf(x) (__builtin_ffsll(x) - 1) +#define FIELD_GET(_mask, _reg) \ + ({ \ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + +/* + * Handle the PERF_RECORD_AUX_OUTPUT_HW_ID event. + * + * The payload associates the Trace ID and the CPU. + * The routine is tolerant of seeing multiple packets with the same associ= ation, + * but a CPU / Trace ID association changing during a session is an error. + */ +static int cs_etm__process_aux_output_hw_id(struct perf_session *session, + union perf_event *event) +{ + struct cs_etm_auxtrace *etm; + struct perf_sample sample; + struct int_node *inode; + struct evsel *evsel; + u64 *cpu_data; + u64 hw_id; + int cpu, version, err; + u8 trace_chan_id, curr_chan_id; + + /* extract and parse the HW ID */ + hw_id =3D event->aux_output_hw_id.hw_id; + version =3D FIELD_GET(CS_AUX_HW_ID_VERSION_MASK, hw_id); + trace_chan_id =3D FIELD_GET(CS_AUX_HW_ID_TRACE_ID_MASK, hw_id); + + /* check that we can handle this version */ + if (version > CS_AUX_HW_ID_CURR_VERSION) + return -EINVAL; + + /* get access to the etm metadata */ + etm =3D container_of(session->auxtrace, struct cs_etm_auxtrace, auxtrace); + if (!etm || !etm->metadata) + return -EINVAL; + + /* parse the sample to get the CPU */ + evsel =3D evlist__event2evsel(session->evlist, event); + if (!evsel) + return -EINVAL; + err =3D evsel__parse_sample(evsel, event, &sample); + if (err) + return err; + cpu =3D sample.cpu; + if (cpu =3D=3D -1) { + /* no CPU in the sample - possibly recorded with an old version of perf = */ + pr_err("CS_ETM: no CPU AUX_OUTPUT_HW_ID sample. Use compatible perf to r= ecord."); + return -EINVAL; + } + + /* See if the ID is mapped to a CPU, and it matches the current CPU */ + inode =3D intlist__find(traceid_list, trace_chan_id); + if (inode) { + cpu_data =3D inode->priv; + if ((int)cpu_data[CS_ETM_CPU] !=3D cpu) { + pr_err("CS_ETM: map mismatch between HW_ID packet CPU and Trace ID\n"); + return -EINVAL; + } + + /* check that the mapped ID matches */ + err =3D cs_etm__metadata_get_trace_id(&curr_chan_id, cpu_data); + if (err) + return err; + if (curr_chan_id !=3D trace_chan_id) { + pr_err("CS_ETM: mismatch between CPU trace ID and HW_ID packet ID\n"); + return -EINVAL; + } + + /* mapped and matched - return OK */ + return 0; + } + + /* not one we've seen before - lets map it */ + cpu_data =3D etm->metadata[cpu]; + err =3D cs_etm__map_trace_id(trace_chan_id, cpu_data); + if (err) + return err; + + /* + * if we are picking up the association from the packet, need to plug + * the correct trace ID into the metadata for setting up decoders later. + */ + err =3D cs_etm__metadata_set_trace_id(trace_chan_id, cpu_data); + return err; +} + void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, u8 trace_chan_id) { @@ -2639,11 +2776,16 @@ static int cs_etm__queue_aux_fragment(struct perf_s= ession *session, off_t file_o } =20 /* - * In per-thread mode, CPU is set to -1, but TID will be set instead. See - * auxtrace_mmap_params__set_idx(). Return 'not found' if neither CPU nor= TID match. + * In per-thread mode, auxtrace CPU is set to -1, but TID will be set ins= tead. See + * auxtrace_mmap_params__set_idx(). However, the sample AUX event will co= ntain a + * CPU as we set this always for the AUX_OUTPUT_HW_ID event. + * So now compare only TIDs if auxtrace CPU is -1, and CPUs if auxtrace C= PU is not -1. + * Return 'not found' if mismatch. */ - if ((auxtrace_event->cpu =3D=3D (__u32) -1 && auxtrace_event->tid !=3D sa= mple->tid) || - auxtrace_event->cpu !=3D sample->cpu) + if (auxtrace_event->cpu =3D=3D (__u32) -1) { + if (auxtrace_event->tid !=3D sample->tid) + return 1; + } else if (auxtrace_event->cpu !=3D sample->cpu) return 1; =20 if (aux_event->flags & PERF_AUX_FLAG_OVERWRITE) { @@ -2692,6 +2834,17 @@ static int cs_etm__queue_aux_fragment(struct perf_se= ssion *session, off_t file_o return 1; } =20 +static int cs_etm__process_aux_hw_id_cb(struct perf_session *session, unio= n perf_event *event, + u64 offset __maybe_unused, void *data __maybe_unused) +{ + /* look to handle PERF_RECORD_AUX_OUTPUT_HW_ID early to ensure decoders c= an be set up */ + if (event->header.type =3D=3D PERF_RECORD_AUX_OUTPUT_HW_ID) { + (*(int *)data)++; /* increment found count */ + return cs_etm__process_aux_output_hw_id(session, event); + } + return 0; +} + static int cs_etm__queue_aux_records_cb(struct perf_session *session, unio= n perf_event *event, u64 offset __maybe_unused, void *data __maybe_unused) { @@ -2781,13 +2934,13 @@ static int cs_etm__map_trace_ids_metadata(int num_c= pu, u64 **metadata) cs_etm_magic =3D metadata[i][CS_ETM_MAGIC]; switch (cs_etm_magic) { case __perf_cs_etmv3_magic: - trace_chan_id =3D (u8)((metadata[i][CS_ETM_ETMTRACEIDR]) & - CORESIGHT_TRACE_ID_VAL_MASK); + metadata[i][CS_ETM_ETMTRACEIDR] &=3D CORESIGHT_TRACE_ID_VAL_MASK; + trace_chan_id =3D (u8)(metadata[i][CS_ETM_ETMTRACEIDR]); break; case __perf_cs_etmv4_magic: case __perf_cs_ete_magic: - trace_chan_id =3D (u8)((metadata[i][CS_ETMV4_TRCTRACEIDR]) & - CORESIGHT_TRACE_ID_VAL_MASK); + metadata[i][CS_ETMV4_TRCTRACEIDR] &=3D CORESIGHT_TRACE_ID_VAL_MASK; + trace_chan_id =3D (u8)(metadata[i][CS_ETMV4_TRCTRACEIDR]); break; default: /* unknown magic number */ @@ -2800,6 +2953,35 @@ static int cs_etm__map_trace_ids_metadata(int num_cp= u, u64 **metadata) return 0; } =20 +/* + * If we found AUX_HW_ID packets, then set any metadata marked as unused t= o the + * unused value to reduce the number of unneeded decoders created. + */ +static int cs_etm__clear_unused_trace_ids_metadata(int num_cpu, u64 **meta= data) +{ + u64 cs_etm_magic; + int i; + + for (i =3D 0; i < num_cpu; i++) { + cs_etm_magic =3D metadata[i][CS_ETM_MAGIC]; + switch (cs_etm_magic) { + case __perf_cs_etmv3_magic: + if (metadata[i][CS_ETM_ETMTRACEIDR] & CORESIGHT_TRACE_ID_UNUSED_FLAG) + metadata[i][CS_ETM_ETMTRACEIDR] =3D CORESIGHT_TRACE_ID_UNUSED_VAL; + break; + case __perf_cs_etmv4_magic: + case __perf_cs_ete_magic: + if (metadata[i][CS_ETMV4_TRCTRACEIDR] & CORESIGHT_TRACE_ID_UNUSED_FLAG) + metadata[i][CS_ETMV4_TRCTRACEIDR] =3D CORESIGHT_TRACE_ID_UNUSED_VAL; + break; + default: + /* unknown magic number */ + return -EINVAL; + } + } + return 0; +} + int cs_etm__process_auxtrace_info_full(union perf_event *event, struct perf_session *session) { @@ -2811,6 +2993,7 @@ int cs_etm__process_auxtrace_info_full(union perf_eve= nt *event, int priv_size =3D 0; int num_cpu; int err =3D 0; + int aux_hw_id_found; int i, j; u64 *ptr =3D NULL; u64 **metadata =3D NULL; @@ -2943,8 +3126,43 @@ int cs_etm__process_auxtrace_info_full(union perf_ev= ent *event, if (err) goto err_delete_thread; =20 - /* before aux records are queued, need to map metadata to trace IDs */ - err =3D cs_etm__map_trace_ids_metadata(num_cpu, metadata); + /* + * Map Trace ID values to CPU metadata. + * + * Trace metadata will always contain Trace ID values from the legacy alg= orithm. If the + * files has been recorded by a "new" perf updated to handle AUX_HW_ID th= en the metadata + * ID value will also have the CORESIGHT_TRACE_ID_UNUSED_FLAG set. + * + * The updated kernel drivers that use AUX_HW_ID to sent Trace IDs will a= ttempt to use + * the same IDs as the old algorithm as far as is possible, unless there = are clashes + * in which case a different value will be used. This means an older perf= may still + * be able to record and read files generate on a newer system. + * + * For a perf able to interpret AUX_HW_ID packets we first check for the = presence of + * those packets. If they are there then the values will be mapped and pl= ugged into + * the metadata. We then set any remaining metadata values with the used = flag to a + * value CORESIGHT_TRACE_ID_UNUSED_VAL - which indicates no decoder is re= quired. + * + * If no AUX_HW_ID packets are present - which means a file recorded on a= n old kernel + * then we map Trace ID values to CPU directly from the metadata - cleari= ng any unused + * flags if present. + */ + + /* first scan for AUX_OUTPUT_HW_ID records to map trace ID values to CPU = metadata */ + aux_hw_id_found =3D 0; + err =3D perf_session__peek_events(session, session->header.data_offset, + session->header.data_size, + cs_etm__process_aux_hw_id_cb, &aux_hw_id_found); + if (err) + goto err_delete_thread; + + /* if HW ID found then clear any unused metadata ID values */ + if (aux_hw_id_found) + err =3D cs_etm__clear_unused_trace_ids_metadata(num_cpu, metadata); + /* otherwise, this is a file with metadata values only, map from metadata= */ + else + err =3D cs_etm__map_trace_ids_metadata(num_cpu, metadata); + if (err) goto err_delete_thread; =20 @@ -2953,14 +3171,6 @@ int cs_etm__process_auxtrace_info_full(union perf_ev= ent *event, goto err_delete_thread; =20 etm->data_queued =3D etm->queues.populated; - /* - * Print warning in pipe mode, see cs_etm__process_auxtrace_event() and - * cs_etm__queue_aux_fragment() for details relating to limitations. - */ - if (!etm->data_queued) - pr_warning("CS ETM warning: Coresight decode and TRBE support requires r= andom file access.\n" - "Continuing with best effort decoding in piped mode.\n\n"); - return 0; =20 err_delete_thread: --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3959C63797 for ; Mon, 16 Jan 2023 12:51:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230488AbjAPMvM (ORCPT ); Mon, 16 Jan 2023 07:51:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230484AbjAPMuW (ORCPT ); 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Mon, 16 Jan 2023 04:49:48 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v7 13/15] coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID Date: Mon, 16 Jan 2023 12:49:26 +0000 Message-Id: <20230116124928.5440-14-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230116124928.5440-1-mike.leach@linaro.org> References: <20230116124928.5440-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use the perf_report_aux_output_id() call to output the CoreSight trace ID and associated CPU as a PERF_RECORD_AUX_OUTPUT_HW_ID record in the perf.data file. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Reported-by: kernel test robot --- drivers/hwtracing/coresight/coresight-etm-perf.c | 7 +++++++ include/linux/coresight-pmu.h | 14 ++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwt= racing/coresight/coresight-etm-perf.c index bdb9ab86173a..12fff661456e 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -4,6 +4,7 @@ * Author: Mathieu Poirier */ =20 +#include #include #include #include @@ -448,6 +449,7 @@ static void etm_event_start(struct perf_event *event, i= nt flags) struct perf_output_handle *handle =3D &ctxt->handle; struct coresight_device *sink, *csdev =3D per_cpu(csdev_src, cpu); struct list_head *path; + u64 hw_id; =20 if (!csdev) goto fail; @@ -493,6 +495,11 @@ static void etm_event_start(struct perf_event *event, = int flags) if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) goto fail_disable_path; =20 + /* output cpu / trace ID in perf record */ + hw_id =3D FIELD_PREP(CS_AUX_HW_ID_VERSION_MASK, CS_AUX_HW_ID_CURR_VERSION= ); + hw_id |=3D FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, coresight_trace_id_read= _cpu_id(cpu)); + perf_report_aux_output_id(event, hw_id); + out: /* Tell the perf core the event is alive */ event->hw.state =3D 0; diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 624f4843453e..51ac441a37c3 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -7,6 +7,8 @@ #ifndef _LINUX_CORESIGHT_PMU_H #define _LINUX_CORESIGHT_PMU_H =20 +#include + #define CORESIGHT_ETM_PMU_NAME "cs_etm" =20 /* @@ -43,4 +45,16 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 =20 +/* + * Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload. + * Used to associate a CPU with the CoreSight Trace ID. + * [07:00] - Trace ID - uses 8 bits to make value easy to read in file. + * [59:08] - Unused (SBZ) + * [63:60] - Version + */ +#define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0) +#define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60) + +#define CS_AUX_HW_ID_CURR_VERSION 0 + #endif --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3E02C63797 for ; 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Mon, 16 Jan 2023 04:49:49 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v7 14/15] coresight: trace-id: Add debug & test macros to Trace ID allocation Date: Mon, 16 Jan 2023 12:49:27 +0000 Message-Id: <20230116124928.5440-15-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230116124928.5440-1-mike.leach@linaro.org> References: <20230116124928.5440-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds in a number of pr_debug macros to allow the debugging and test of the trace ID allocation system. Signed-off-by: Mike Leach Reported-by: kernel test robot --- .../hwtracing/coresight/coresight-trace-id.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwt= racing/coresight/coresight-trace-id.c index 9b85c376cb12..367bbfb4c213 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.c +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -24,6 +24,27 @@ static atomic_t perf_cs_etm_session_active =3D ATOMIC_IN= IT(0); /* lock to protect id_map and cpu data */ static DEFINE_SPINLOCK(id_map_lock); =20 +/* #define TRACE_ID_DEBUG 1 */ +#if defined(TRACE_ID_DEBUG) || defined(CONFIG_COMPILE_TEST) + +static void coresight_trace_id_dump_table(struct coresight_trace_id_map *i= d_map, + const char *func_name) +{ + pr_debug("%s id_map::\n", func_name); + pr_debug("Used =3D %*pb\n", CORESIGHT_TRACE_IDS_MAX, id_map->used_ids); + pr_debug("Pend =3D %*pb\n", CORESIGHT_TRACE_IDS_MAX, id_map->pend_rel_ids= ); +} +#define DUMP_ID_MAP(map) coresight_trace_id_dump_table(map, __func__) +#define DUMP_ID_CPU(cpu, id) pr_debug("%s called; cpu=3D%d, id=3D%d\n", _= _func__, cpu, id) +#define DUMP_ID(id) pr_debug("%s called; id=3D%d\n", __func__, id) +#define PERF_SESSION(n) pr_debug("%s perf count %d\n", __func__, n) +#else +#define DUMP_ID_MAP(map) +#define DUMP_ID(id) +#define DUMP_ID_CPU(cpu, id) +#define PERF_SESSION(n) +#endif + /* unlocked read of current trace ID value for given CPU */ static int _coresight_trace_id_read_cpu_id(int cpu) { @@ -127,6 +148,7 @@ static void coresight_trace_id_release_all_pending(void) cpumask_clear_cpu(cpu, &cpu_id_release_pending); } spin_unlock_irqrestore(&id_map_lock, flags); + DUMP_ID_MAP(id_map); } =20 static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_tra= ce_id_map *id_map) @@ -168,6 +190,8 @@ static int coresight_trace_id_map_get_cpu_id(int cpu, s= truct coresight_trace_id_ get_cpu_id_out_unlock: spin_unlock_irqrestore(&id_map_lock, flags); =20 + DUMP_ID_CPU(cpu, id); + DUMP_ID_MAP(id_map); return id; } =20 @@ -194,6 +218,8 @@ static void coresight_trace_id_map_put_cpu_id(int cpu, = struct coresight_trace_id } =20 spin_unlock_irqrestore(&id_map_lock, flags); + DUMP_ID_CPU(cpu, id); + DUMP_ID_MAP(id_map); } =20 static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_= map *id_map) @@ -206,6 +232,8 @@ static int coresight_trace_id_map_get_system_id(struct = coresight_trace_id_map *i id =3D coresight_trace_id_alloc_new_id(id_map, 0, true); spin_unlock_irqrestore(&id_map_lock, flags); =20 + DUMP_ID(id); + DUMP_ID_MAP(id_map); return id; } =20 @@ -216,6 +244,9 @@ static void coresight_trace_id_map_put_system_id(struct= coresight_trace_id_map * spin_lock_irqsave(&id_map_lock, flags); coresight_trace_id_free(id, id_map); spin_unlock_irqrestore(&id_map_lock, flags); + + DUMP_ID(id); + DUMP_ID_MAP(id_map); } =20 /* API functions */ @@ -253,6 +284,7 @@ EXPORT_SYMBOL_GPL(coresight_trace_id_put_system_id); void coresight_trace_id_perf_start(void) { atomic_inc(&perf_cs_etm_session_active); + PERF_SESSION(atomic_read(&perf_cs_etm_session_active)); } EXPORT_SYMBOL_GPL(coresight_trace_id_perf_start); =20 @@ -260,6 +292,7 @@ void coresight_trace_id_perf_stop(void) { if (!atomic_dec_return(&perf_cs_etm_session_active)) coresight_trace_id_release_all_pending(); + PERF_SESSION(atomic_read(&perf_cs_etm_session_active)); } EXPORT_SYMBOL_GPL(coresight_trace_id_perf_stop); =20 --=20 2.17.1 From nobody Mon Sep 15 02:05:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE624C54EBE for ; Mon, 16 Jan 2023 12:51:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231193AbjAPMvT (ORCPT ); Mon, 16 Jan 2023 07:51:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231178AbjAPMuc (ORCPT ); Mon, 16 Jan 2023 07:50:32 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77C8C1F4A2 for ; Mon, 16 Jan 2023 04:49:51 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id k22-20020a05600c1c9600b003d1ee3a6289so22062840wms.2 for ; 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Mon, 16 Jan 2023 04:49:51 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:6c91:710d:9433:e868]) by smtp.gmail.com with ESMTPSA id fl12-20020a05600c0b8c00b003dab40f9eafsm6896832wmb.35.2023.01.16.04.49.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 04:49:50 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v7 15/15] coresight: etm3x: docs: Alter sysfs documentation for trace id updates Date: Mon, 16 Jan 2023 12:49:28 +0000 Message-Id: <20230116124928.5440-16-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230116124928.5440-1-mike.leach@linaro.org> References: <20230116124928.5440-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Sysfs access to etm3x trace ID value is now read-only due to recent trace updates and for consistency with etm4x. Signed-off-by: Mike Leach Reported-by: kernel test robot --- Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x b/= Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x index 651602a61eac..234c33fbdb55 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x @@ -236,7 +236,7 @@ What: /sys/bus/coresight/devices/.[etm|ptm= ]/traceid Date: November 2014 KernelVersion: 3.19 Contact: Mathieu Poirier -Description: (RW) Holds the trace ID that will appear in the trace stream +Description: (RO) Holds the trace ID that will appear in the trace stream coming from this trace entity. =20 What: /sys/bus/coresight/devices/.[etm|ptm]/trigger_event --=20 2.17.1