From nobody Sat Sep 21 07:28:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9535C678DA for ; Mon, 16 Jan 2023 23:52:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232725AbjAPXwu (ORCPT ); Mon, 16 Jan 2023 18:52:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232650AbjAPXwr (ORCPT ); Mon, 16 Jan 2023 18:52:47 -0500 Received: from mail.3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C859022A07; Mon, 16 Jan 2023 15:52:46 -0800 (PST) Received: from mwalle01.sab.local (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 6F428D5C; Tue, 17 Jan 2023 00:52:44 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1673913164; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fbfQoq+/nP40y3Od/7KPlEsF8XCF4vb8Tsl/JXpv37c=; b=RIRLUnFhk4lbuRdXBZHwvVY5XR0+dcNDfp4iMVgeUJ/UMEQKXYirRkgdpUGsMF3lEheMEu J7n7W4g5GkNe3Ys5h5VF9sorDHMDoon2yECEhIi6H+GgsOB58yXiBggLDlClmOgvMvYtuc JalLhD+AYTo6z6j+OUTifMY64KrLoQeoSOzrQQwQbDgxmGlfhhf1lrqUZztKAOuRTAXK1f kUqJqu9UC9YABe4lSZmAuB8eAa1kwA3Pl9ZUzsCuP9KGgYTaUswHOLtGA8/u+n4YrBxDx5 xUqH6i3Zxn684NGuVXqt0uHK1+Xu2e86DjuAgPpa2ZFyVlOBAMl6EmWDewyUEg== From: Michael Walle Date: Tue, 17 Jan 2023 00:52:16 +0100 Subject: [PATCH net-next 01/12] net: dsa: mt7530: Separate C22 and C45 MDIO bus transactions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230116-net-next-c45-seperation-part-3-v1-1-0c53afa56aad@walle.cc> References: <20230116-net-next-c45-seperation-part-3-v1-0-0c53afa56aad@walle.cc> In-Reply-To: <20230116-net-next-c45-seperation-part-3-v1-0-0c53afa56aad@walle.cc> To: Sean Wang , Landen Chao , DENG Qingfang , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , Russell King , Byungho An , Nicolas Ferre , Claudiu Beznea , Jesse Brandeburg , Tony Nguyen , Yisen Zhuang , Salil Mehta , Tom Lendacky , Shyam Sundar S K , Sergey Shtylyov Cc: netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org, linux-renesas-soc@vger.kernel.org, Andrew Lunn , Michael Walle X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Lunn mt7530 does support C45, but its uses a mix of registering its MDIO bus and providing its private MDIO bus to the DSA core, too. This makes the change a bit more complex. Signed-off-by: Andrew Lunn Signed-off-by: Michael Walle --- v3 (the 'new' v1): [mw] Remove dsa core comment [mw] Rephrase commit message v2: [al] Remove conditional c45, since all switches support c45 [al] Remove dsa core changes, they are not needed [al] Add comment that DSA provided MDIO bus is C22 only. --- drivers/net/dsa/mt7530.c | 87 ++++++++++++++++++++++++--------------------= ---- drivers/net/dsa/mt7530.h | 15 ++++++--- 2 files changed, 55 insertions(+), 47 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 908fa89444c9..616b21c90d05 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -608,17 +608,29 @@ mt7530_mib_reset(struct dsa_switch *ds) mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); } =20 -static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum) +static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int reg= num) { return mdiobus_read_nested(priv->bus, port, regnum); } =20 -static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum, - u16 val) +static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int re= gnum, + u16 val) { return mdiobus_write_nested(priv->bus, port, regnum, val); } =20 +static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, + int devad, int regnum) +{ + return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); +} + +static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int de= vad, + int regnum, u16 val) +{ + return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); +} + static int mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, int regnum) @@ -670,7 +682,7 @@ mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int p= ort, int devad, =20 static int mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, - int regnum, u32 data) + int regnum, u16 data) { struct mii_bus *bus =3D priv->bus; struct mt7530_dummy_poll p; @@ -793,55 +805,36 @@ mt7531_ind_c22_phy_write(struct mt7530_priv *priv, in= t port, int regnum, } =20 static int -mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum) +mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) { - int devad; - int ret; - - if (regnum & MII_ADDR_C45) { - devad =3D (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; - ret =3D mt7531_ind_c45_phy_read(priv, port, devad, - regnum & MII_REGADDR_C45_MASK); - } else { - ret =3D mt7531_ind_c22_phy_read(priv, port, regnum); - } + struct mt7530_priv *priv =3D bus->priv; =20 - return ret; + return priv->info->phy_read_c22(priv, port, regnum); } =20 static int -mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum, - u16 data) +mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) { - int devad; - int ret; - - if (regnum & MII_ADDR_C45) { - devad =3D (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; - ret =3D mt7531_ind_c45_phy_write(priv, port, devad, - regnum & MII_REGADDR_C45_MASK, - data); - } else { - ret =3D mt7531_ind_c22_phy_write(priv, port, regnum, data); - } + struct mt7530_priv *priv =3D bus->priv; =20 - return ret; + return priv->info->phy_read_c45(priv, port, devad, regnum); } =20 static int -mt753x_phy_read(struct mii_bus *bus, int port, int regnum) +mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) { struct mt7530_priv *priv =3D bus->priv; =20 - return priv->info->phy_read(priv, port, regnum); + return priv->info->phy_write_c22(priv, port, regnum, val); } =20 static int -mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val) +mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, + u16 val) { struct mt7530_priv *priv =3D bus->priv; =20 - return priv->info->phy_write(priv, port, regnum, val); + return priv->info->phy_write_c45(priv, port, devad, regnum, val); } =20 static void @@ -2086,8 +2079,10 @@ mt7530_setup_mdio(struct mt7530_priv *priv) bus->priv =3D priv; bus->name =3D KBUILD_MODNAME "-mii"; snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); - bus->read =3D mt753x_phy_read; - bus->write =3D mt753x_phy_write; + bus->read =3D mt753x_phy_read_c22; + bus->write =3D mt753x_phy_write_c22; + bus->read_c45 =3D mt753x_phy_read_c45; + bus->write_c45 =3D mt753x_phy_write_c45; bus->parent =3D dev; bus->phy_mask =3D ~ds->phys_mii_mask; =20 @@ -3182,8 +3177,10 @@ static const struct mt753x_info mt753x_table[] =3D { .id =3D ID_MT7621, .pcs_ops =3D &mt7530_pcs_ops, .sw_setup =3D mt7530_setup, - .phy_read =3D mt7530_phy_read, - .phy_write =3D mt7530_phy_write, + .phy_read_c22 =3D mt7530_phy_read_c22, + .phy_write_c22 =3D mt7530_phy_write_c22, + .phy_read_c45 =3D mt7530_phy_read_c45, + .phy_write_c45 =3D mt7530_phy_write_c45, .pad_setup =3D mt7530_pad_clk_setup, .mac_port_get_caps =3D mt7530_mac_port_get_caps, .mac_port_config =3D mt7530_mac_config, @@ -3192,8 +3189,10 @@ static const struct mt753x_info mt753x_table[] =3D { .id =3D ID_MT7530, .pcs_ops =3D &mt7530_pcs_ops, .sw_setup =3D mt7530_setup, - .phy_read =3D mt7530_phy_read, - .phy_write =3D mt7530_phy_write, + .phy_read_c22 =3D mt7530_phy_read_c22, + .phy_write_c22 =3D mt7530_phy_write_c22, + .phy_read_c45 =3D mt7530_phy_read_c45, + .phy_write_c45 =3D mt7530_phy_write_c45, .pad_setup =3D mt7530_pad_clk_setup, .mac_port_get_caps =3D mt7530_mac_port_get_caps, .mac_port_config =3D mt7530_mac_config, @@ -3202,8 +3201,10 @@ static const struct mt753x_info mt753x_table[] =3D { .id =3D ID_MT7531, .pcs_ops =3D &mt7531_pcs_ops, .sw_setup =3D mt7531_setup, - .phy_read =3D mt7531_ind_phy_read, - .phy_write =3D mt7531_ind_phy_write, + .phy_read_c22 =3D mt7531_ind_c22_phy_read, + .phy_write_c22 =3D mt7531_ind_c22_phy_write, + .phy_read_c45 =3D mt7531_ind_c45_phy_read, + .phy_write_c45 =3D mt7531_ind_c45_phy_write, .pad_setup =3D mt7531_pad_setup, .cpu_port_config =3D mt7531_cpu_port_config, .mac_port_get_caps =3D mt7531_mac_port_get_caps, @@ -3263,7 +3264,7 @@ mt7530_probe(struct mdio_device *mdiodev) * properly. */ if (!priv->info->sw_setup || !priv->info->pad_setup || - !priv->info->phy_read || !priv->info->phy_write || + !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps || !priv->info->mac_port_config) return -EINVAL; diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index e8d966435350..6b2fc6290ea8 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -750,8 +750,10 @@ struct mt753x_pcs { /* struct mt753x_info - This is the main data structure for holding the sp= ecific * part for each supported device * @sw_setup: Holding the handler to a device initialization - * @phy_read: Holding the way reading PHY port - * @phy_write: Holding the way writing PHY port + * @phy_read_c22: Holding the way reading PHY port using C22 + * @phy_write_c22: Holding the way writing PHY port using C22 + * @phy_read_c45: Holding the way reading PHY port using C45 + * @phy_write_c45: Holding the way writing PHY port using C45 * @pad_setup: Holding the way setting up the bus pad for a certain * MAC port * @phy_mode_supported: Check if the PHY type is being supported on a cert= ain @@ -767,8 +769,13 @@ struct mt753x_info { const struct phylink_pcs_ops *pcs_ops; =20 int (*sw_setup)(struct dsa_switch *ds); - int (*phy_read)(struct mt7530_priv *priv, int port, int regnum); - int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val); + int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum); + int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum, + u16 val); + int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad, + int regnum); + int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad, + int regnum, u16 val); int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); int (*cpu_port_config)(struct dsa_switch *ds, int port); void (*mac_port_get_caps)(struct dsa_switch *ds, int port, --=20 2.30.2