From nobody Mon Sep 15 06:20:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6B20C3DA78 for ; Sun, 15 Jan 2023 16:01:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231494AbjAOQBF (ORCPT ); Sun, 15 Jan 2023 11:01:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231539AbjAOQAt (ORCPT ); Sun, 15 Jan 2023 11:00:49 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DEDD10426; Sun, 15 Jan 2023 08:00:30 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 2252FB80B57; Sun, 15 Jan 2023 16:00:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D3D2FC4339B; Sun, 15 Jan 2023 16:00:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673798427; bh=EUOTCCvK3BHS1pXfvH2BWP1K07d19xWmUCZHwihqXEQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IyaKhZ/O6P3f7A84a7Mw65DbbtwySU8FHZUpDYH5rMVUn5TACJ0lE35OOY2tMrSCt lJp6+2oW4CX+R33fdtERPdljP4YWsgHv19MdNMi5SiHbKNVMQ3wyE+5X2/pHjVE0l+ hoV6VU4BGHlE+mYgCtrkDmAL+LkeXLtTIjQbYDyi4356m1BDtAvaU208rp/pC9QD9n 1Jr1e01kNzsfv+t92drf0Sc6Pw0MrtdEkw2AYvGVpQQ95eVR23t3GLmM8n/diSvSAK 4XtxUhihzUefRaNaGGnDWnr2vX6GvQkVmgGIEn/83x6uni6DB47U0FJK6U2nSLQFr4 vCqqiPbQzaVCg== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner , Conor Dooley , Andrew Jones Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v4 05/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Date: Sun, 15 Jan 2023 23:49:45 +0800 Message-Id: <20230115154953.831-6-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230115154953.831-1-jszhang@kernel.org> References: <20230115154953.831-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" riscv_cpufeature_patch_func() currently only scans a limited set of cpufeatures, explicitly defined with macros. Extend it to probe for all ISA extensions. Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/include/asm/errata_list.h | 9 ++-- arch/riscv/kernel/cpufeature.c | 63 ++++------------------------ 2 files changed, 11 insertions(+), 61 deletions(-) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 4180312d2a70..274c6f889602 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -7,6 +7,7 @@ =20 #include #include +#include #include =20 #ifdef CONFIG_ERRATA_SIFIVE @@ -22,10 +23,6 @@ #define ERRATA_THEAD_NUMBER 3 #endif =20 -#define CPUFEATURE_SVPBMT 0 -#define CPUFEATURE_ZICBOM 1 -#define CPUFEATURE_NUMBER 2 - #ifdef __ASSEMBLY__ =20 #define ALT_INSN_FAULT(x) \ @@ -55,7 +52,7 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VEN= DOR_ID, \ #define ALT_SVPBMT(_val, prot) \ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ "li %0, %1\t\nslli %0,%0,%3", 0, \ - CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ + RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ : "=3Dr"(_val) \ @@ -129,7 +126,7 @@ asm volatile(ALTERNATIVE_2( \ "add a0, a0, %0\n\t" \ "2:\n\t" \ "bltu a0, %2, 3b\n\t" \ - "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ + "nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ "mv a0, %1\n\t" \ "j 2f\n\t" \ "3:\n\t" \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 37e8c5e69754..6db8b31d9149 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -275,58 +275,11 @@ void __init riscv_fill_hwcap(void) } =20 #ifdef CONFIG_RISCV_ALTERNATIVE -static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage) -{ - if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT)) - return false; - - if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) - return false; - - return riscv_isa_extension_available(NULL, SVPBMT); -} - -static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) -{ - if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM)) - return false; - - if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) - return false; - - if (!riscv_isa_extension_available(NULL, ZICBOM)) - return false; - - return true; -} - -/* - * Probe presence of individual extensions. - * - * This code may also be executed before kernel relocation, so we cannot u= se - * addresses generated by the address-of operator as they won't be valid in - * this context. - */ -static u32 __init_or_module cpufeature_probe(unsigned int stage) -{ - u32 cpu_req_feature =3D 0; - - if (cpufeature_probe_svpbmt(stage)) - cpu_req_feature |=3D BIT(CPUFEATURE_SVPBMT); - - if (cpufeature_probe_zicbom(stage)) - cpu_req_feature |=3D BIT(CPUFEATURE_ZICBOM); - - return cpu_req_feature; -} - void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned int stage) { - u32 cpu_req_feature =3D cpufeature_probe(stage); struct alt_entry *alt; - u32 tmp; =20 if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) return; @@ -334,18 +287,18 @@ void __init_or_module riscv_cpufeature_patch_func(str= uct alt_entry *begin, for (alt =3D begin; alt < end; alt++) { if (alt->vendor_id !=3D 0) continue; - if (alt->errata_id >=3D CPUFEATURE_NUMBER) { - WARN(1, "This feature id:%d is not in kernel cpufeature list", + if (alt->errata_id >=3D RISCV_ISA_EXT_MAX) { + WARN(1, "This extension id:%d is not in ISA extension list", alt->errata_id); continue; } =20 - tmp =3D (1U << alt->errata_id); - if (cpu_req_feature & tmp) { - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); - riscv_alternative_fix_offsets(alt->old_ptr, alt->alt_len, - alt->old_ptr - alt->alt_ptr); - } + if (!__riscv_isa_extension_available(NULL, alt->errata_id)) + continue; + + patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); + riscv_alternative_fix_offsets(alt->old_ptr, alt->alt_len, + alt->old_ptr - alt->alt_ptr); } } #endif --=20 2.38.1