From nobody Mon Sep 15 05:51:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EC5EC46467 for ; Sat, 14 Jan 2023 09:17:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229464AbjANJRF (ORCPT ); Sat, 14 Jan 2023 04:17:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229875AbjANJQ6 (ORCPT ); Sat, 14 Jan 2023 04:16:58 -0500 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8ED8F5BA2 for ; Sat, 14 Jan 2023 01:16:52 -0800 (PST) Received: from dggpeml500002.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4NvCGR6VRYzqV6d; Sat, 14 Jan 2023 17:11:59 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggpeml500002.china.huawei.com (7.185.36.158) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Sat, 14 Jan 2023 17:16:49 +0800 From: Junhao He To: , , , CC: , , , , , , , Subject: [PATCH v2] coresight: etm4x: Fix accesses to TRCSEQRSTEVR and TRCSEQSTR Date: Sat, 14 Jan 2023 17:16:32 +0800 Message-ID: <20230114091632.60095-1-hejunhao3@huawei.com> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500002.china.huawei.com (7.185.36.158) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The TRCSEQRSTEVR and TRCSEQSTR registers are not implemented if the TRCIDR5.NUMSEQSTATE =3D=3D 0. Skip accessing the registers in such cases. Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") Signed-off-by: Junhao He Reviewed-by: Mike Leach Reviewed-by: Anshuman Khandual --- .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 1cc052979e01..77bca6932f01 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -427,8 +427,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdat= a) etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); for (i =3D 0; i < drvdata->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); + if (drvdata->nrseqstate) { + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); + } etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); for (i =3D 0; i < drvdata->nr_cntr; i++) { etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); @@ -1634,8 +1636,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drv= data) for (i =3D 0; i < drvdata->nrseqstate - 1; i++) state->trcseqevr[i] =3D etm4x_read32(csa, TRCSEQEVRn(i)); =20 - state->trcseqrstevr =3D etm4x_read32(csa, TRCSEQRSTEVR); - state->trcseqstr =3D etm4x_read32(csa, TRCSEQSTR); + if (drvdata->nrseqstate) { + state->trcseqrstevr =3D etm4x_read32(csa, TRCSEQRSTEVR); + state->trcseqstr =3D etm4x_read32(csa, TRCSEQSTR); + } state->trcextinselr =3D etm4x_read32(csa, TRCEXTINSELR); =20 for (i =3D 0; i < drvdata->nr_cntr; i++) { @@ -1763,8 +1767,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata = *drvdata) for (i =3D 0; i < drvdata->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); =20 - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); + if (drvdata->nrseqstate) { + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); + } etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); =20 for (i =3D 0; i < drvdata->nr_cntr; i++) { --=20 2.33.0