From nobody Mon Sep 15 05:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2557C677F1 for ; Sat, 14 Jan 2023 07:10:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229678AbjANHK1 (ORCPT ); Sat, 14 Jan 2023 02:10:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229675AbjANHKW (ORCPT ); Sat, 14 Jan 2023 02:10:22 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C022C4EF1 for ; Fri, 13 Jan 2023 23:10:20 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id z4-20020a17090a170400b00226d331390cso26486369pjd.5 for ; Fri, 13 Jan 2023 23:10:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5rVjfkYb6kJqgDZ9JG4i2SJUUl3r5DoIs4tnSJUvhY4=; b=eZ5ExSwp3UQN9DBUZHKaI8TbK7kbsZ+5w9fWEXHl4IDEXwVSn3UUwcsSta6v8cEHVw JUxxVHRlsFh+O11XsYC31RAWos2mNkBkp1ZttJv8ueGE9GthkIuWBWttUVBr08ryDzez SV8D4ch0GT9jdm818IrtUrX08KFjzNNWOB3HtkpQci6CZmI/2bvMA2lE++MZzjRhfgRu Zz2hdh7yBKF7tPuOfZwwvYuqoF06jKH8FyBhd7cjVjpTlQEk6EbDCAWZ+Hc9G7z8y6w6 cTGMQvnWGY9jKhz4Qdu20VivWgB7vwQwXCojf/3uchvnrMXe0A6jvW8OcFYYBe9I+U9M zyJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5rVjfkYb6kJqgDZ9JG4i2SJUUl3r5DoIs4tnSJUvhY4=; b=NU1K8mxT9nTwb4capKOHCYZSM6tZdhNdsUWh/PLh68pzQN5HLKt4wfTgBdkmn1tI+L MWJ6uWqEMeroAnsc2CGrBsr3C3ue+l9qOIbovDQgAP6ALLrmR0Exhy5suIazsI29aVTX UGHQCa34s8BI9U0K3AIgFaFsgR0RXYhj1qliNJMvjIB4/GxLxgirE/rjN4iQwvFYAul/ cuqKdJPWSQiTBky2jwmi/VY6FdMf9BBxOXnhpbHNgrF9j84lw2XfcG89QxpFCvAkPr/z UOrsntCCqKeeQkskrUAcEpjQWhUpixc+Ua2sqdG6k8hDO2TcsIqSr9ErV1mobpQayhx9 ImVg== X-Gm-Message-State: AFqh2kq+d96ra29WZETLZUrPQMpMaKl7H8aTyONr4DAbMMc0vxg70r0W CvkroH2F0/PX+Kuk3+LczMmb X-Google-Smtp-Source: AMrXdXtB3Ane56nYbzPEsjF5N5tirwXzXvFmA2/yKOS7Jeu+SCt8Z6DBggsJv9HkIudUZ1jwj01AvQ== X-Received: by 2002:a17:902:ab1e:b0:193:17b7:7909 with SMTP id ik30-20020a170902ab1e00b0019317b77909mr25753372plb.5.1673680220169; Fri, 13 Jan 2023 23:10:20 -0800 (PST) Received: from localhost.localdomain ([220.158.159.156]) by smtp.gmail.com with ESMTPSA id q10-20020a170902e30a00b00192a04bc620sm15225358plc.295.2023.01.13.23.10.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 23:10:19 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 01/12] phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl definitions Date: Sat, 14 Jan 2023 12:39:58 +0530 Message-Id: <20230114071009.88102-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Following the other QMP PHY drivers like PCIe, let's remove the "_tbl" suffix from the qmp_phy_init_tbl definitions. This helps in maintaining the uniformity across all of the QMP PHY drivers. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 146 ++++++++++++------------ 1 file changed, 73 insertions(+), 73 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index d2f3cba625b8..30d098735040 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -99,7 +99,7 @@ static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYO= UT_SIZE] =3D { [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL, }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -148,12 +148,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), @@ -167,7 +167,7 @@ static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl= [] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -223,12 +223,12 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_se= rdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), @@ -246,7 +246,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15), QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), @@ -258,7 +258,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), @@ -300,13 +300,13 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_se= rdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -325,7 +325,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -336,7 +336,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), @@ -366,7 +366,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), @@ -375,7 +375,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -413,7 +413,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_t= bl[] =3D { =20 }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -423,7 +423,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), @@ -453,7 +453,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), @@ -465,7 +465,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -505,7 +505,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -637,12 +637,12 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v= 5 =3D { static const struct qmp_phy_cfg msm8996_ufs_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D msm8996_ufs_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufs_serdes_tbl), - .tx_tbl =3D msm8996_ufs_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_tx_tbl), - .rx_tbl =3D msm8996_ufs_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_rx_tbl), + .serdes_tbl =3D msm8996_ufs_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufs_serdes), + .tx_tbl =3D msm8996_ufs_tx, + .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_tx), + .rx_tbl =3D msm8996_ufs_rx, + .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_rx), =20 .clk_list =3D msm8996_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -660,14 +660,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { =20 .offsets =3D &qmp_ufs_offsets_v5, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl =3D sm8350_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl =3D sm8350_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl =3D sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8350_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx_tbl =3D sm8350_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx_tbl =3D sm8350_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs_tbl =3D sm8350_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -678,14 +678,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sdm845_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), - .tx_tbl =3D sdm845_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_tx_tbl), - .rx_tbl =3D sdm845_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_rx_tbl), - .pcs_tbl =3D sdm845_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), + .serdes_tbl =3D sdm845_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes), + .tx_tbl =3D sdm845_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_tx), + .rx_tbl =3D sdm845_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_rx), + .pcs_tbl =3D sdm845_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -700,14 +700,14 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { =20 .offsets =3D &qmp_ufs_offsets_v5, =20 - .serdes_tbl =3D sm6115_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), - .tx_tbl =3D sm6115_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_tx_tbl), - .rx_tbl =3D sm6115_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_rx_tbl), - .pcs_tbl =3D sm6115_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), + .serdes_tbl =3D sm6115_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes), + .tx_tbl =3D sm6115_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_tx), + .rx_tbl =3D sm6115_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_rx), + .pcs_tbl =3D sm6115_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -720,14 +720,14 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8150_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), - .tx_tbl =3D sm8150_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_tx_tbl), - .rx_tbl =3D sm8150_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_rx_tbl), - .pcs_tbl =3D sm8150_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8150_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx_tbl =3D sm8150_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx_tbl =3D sm8150_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs_tbl =3D sm8150_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -738,14 +738,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl =3D sm8350_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl =3D sm8350_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl =3D sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8350_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx_tbl =3D sm8350_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx_tbl =3D sm8350_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs_tbl =3D sm8350_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -756,14 +756,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl =3D sm8350_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl =3D sm8350_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl =3D sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8350_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx_tbl =3D sm8350_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx_tbl =3D sm8350_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs_tbl =3D sm8350_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Mon Sep 15 05:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80376C3DA78 for ; Sat, 14 Jan 2023 07:10:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229702AbjANHKc (ORCPT ); Sat, 14 Jan 2023 02:10:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229679AbjANHK2 (ORCPT ); Sat, 14 Jan 2023 02:10:28 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com 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smtp.gmail.com with ESMTPSA id q10-20020a170902e30a00b00192a04bc620sm15225358plc.295.2023.01.13.23.10.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 23:10:23 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 02/12] phy: qcom-qmp-ufs: Rename MSM8996 PHY definitions Date: Sat, 14 Jan 2023 12:39:59 +0530 Message-Id: <20230114071009.88102-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Only MSM8996 is using "_ufs_" naming convention for PHY definitions instead of "_ufsphy_" as like other SoCs. So to maintain the uniformity, let's rename all of the definitions to use "_ufsphy_". Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 30d098735040..5645637e7773 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -99,7 +99,7 @@ static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYO= UT_SIZE] =3D { [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL, }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -148,12 +148,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_tx[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_rx[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), @@ -634,15 +634,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v= 5 =3D { .rx2 =3D 0xa00, }; =20 -static const struct qmp_phy_cfg msm8996_ufs_cfg =3D { +static const struct qmp_phy_cfg msm8996_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D msm8996_ufs_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufs_serdes), - .tx_tbl =3D msm8996_ufs_tx, - .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_tx), - .rx_tbl =3D msm8996_ufs_rx, - .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_rx), + .serdes_tbl =3D msm8996_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_serdes), + .tx_tbl =3D msm8996_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_tx), + .rx_tbl =3D msm8996_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), =20 .clk_list =3D msm8996_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -1220,7 +1220,7 @@ static int qmp_ufs_probe(struct platform_device *pdev) static const struct of_device_id qmp_ufs_of_match_table[] =3D { { .compatible =3D "qcom,msm8996-qmp-ufs-phy", - .data =3D &msm8996_ufs_cfg, + .data =3D &msm8996_ufsphy_cfg, }, { .compatible =3D "qcom,msm8998-qmp-ufs-phy", .data =3D &sdm845_ufsphy_cfg, --=20 2.25.1 From nobody Mon Sep 15 05:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D257C46467 for ; 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Fri, 13 Jan 2023 23:10:27 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 03/12] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct Date: Sat, 14 Jan 2023 12:40:00 +0530 Message-Id: <20230114071009.88102-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As done for Qcom PCIe PHY driver, let's move the register settings to the common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY settings needed for functionalities like HS-G4 in the future by adding one more instance of the qmp_phy_cfg_tbls. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 196 ++++++++++++++---------- 1 file changed, 113 insertions(+), 83 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 5645637e7773..90d644fb321b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -532,21 +532,26 @@ struct qmp_ufs_offsets { u16 rx2; }; =20 +struct qmp_phy_cfg_tbls { + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes; + int serdes_num; + const struct qmp_phy_init_tbl *tx; + int tx_num; + const struct qmp_phy_init_tbl *rx; + int rx_num; + const struct qmp_phy_init_tbl *pcs; + int pcs_num; +}; + /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { int lanes; =20 const struct qmp_ufs_offsets *offsets; =20 - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ - const struct qmp_phy_init_tbl *serdes_tbl; - int serdes_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl; - int tx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl; - int rx_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl; - int pcs_tbl_num; + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_cfg_tbls tbls; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -637,12 +642,14 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v= 5 =3D { static const struct qmp_phy_cfg msm8996_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D msm8996_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_serdes), - .tx_tbl =3D msm8996_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_tx), - .rx_tbl =3D msm8996_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), + .tbls =3D { + .serdes =3D msm8996_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(msm8996_ufsphy_serdes), + .tx =3D msm8996_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(msm8996_ufsphy_tx), + .rx =3D msm8996_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), + }, =20 .clk_list =3D msm8996_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -660,14 +667,16 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { =20 .offsets =3D &qmp_ufs_offsets_v5, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), - .tx_tbl =3D sm8350_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), - .rx_tbl =3D sm8350_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), - .pcs_tbl =3D sm8350_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8350_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx =3D sm8350_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx =3D sm8350_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs =3D sm8350_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -678,14 +687,16 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sdm845_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes), - .tx_tbl =3D sdm845_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_tx), - .rx_tbl =3D sdm845_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_rx), - .pcs_tbl =3D sdm845_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), + .tbls =3D { + .serdes =3D sdm845_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes), + .tx =3D sdm845_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sdm845_ufsphy_tx), + .rx =3D sdm845_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sdm845_ufsphy_rx), + .pcs =3D sdm845_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -700,14 +711,16 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { =20 .offsets =3D &qmp_ufs_offsets_v5, =20 - .serdes_tbl =3D sm6115_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes), - .tx_tbl =3D sm6115_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_tx), - .rx_tbl =3D sm6115_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_rx), - .pcs_tbl =3D sm6115_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm6115_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes), + .tx =3D sm6115_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm6115_ufsphy_tx), + .rx =3D sm6115_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm6115_ufsphy_rx), + .pcs =3D sm6115_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -720,14 +733,16 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8150_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), - .tx_tbl =3D sm8150_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), - .rx_tbl =3D sm8150_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), - .pcs_tbl =3D sm8150_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8150_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx =3D sm8150_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx =3D sm8150_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs =3D sm8150_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -738,14 +753,16 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), - .tx_tbl =3D sm8350_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), - .rx_tbl =3D sm8350_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), - .pcs_tbl =3D sm8350_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8350_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx =3D sm8350_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx =3D sm8350_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs =3D sm8350_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -756,14 +773,16 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), - .tx_tbl =3D sm8350_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), - .rx_tbl =3D sm8350_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), - .pcs_tbl =3D sm8350_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8350_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx =3D sm8350_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx =3D sm8350_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs =3D sm8350_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -797,16 +816,40 @@ static void qmp_ufs_configure(void __iomem *base, qmp_ufs_configure_lane(base, tbl, num, 0xff); } =20 -static int qmp_ufs_serdes_init(struct qmp_ufs *qmp) +static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_= cfg_tbls *tbls) { - const struct qmp_phy_cfg *cfg =3D qmp->cfg; void __iomem *serdes =3D qmp->serdes; - const struct qmp_phy_init_tbl *serdes_tbl =3D cfg->serdes_tbl; - int serdes_tbl_num =3D cfg->serdes_tbl_num; =20 - qmp_ufs_configure(serdes, serdes_tbl, serdes_tbl_num); + qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num); +} =20 - return 0; +static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_c= fg_tbls *tbls) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + void __iomem *tx =3D qmp->tx; + void __iomem *rx =3D qmp->rx; + + qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1); + qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1); + + if (cfg->lanes >=3D 2) { + qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2); + qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2); + } +} + +static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg= _tbls *tbls) +{ + void __iomem *pcs =3D qmp->pcs; + + qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num); +} + +static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_p= hy_cfg *cfg) +{ + qmp_ufs_serdes_init(qmp, &cfg->tbls); + qmp_ufs_lanes_init(qmp, &cfg->tbls); + qmp_ufs_pcs_init(qmp, &cfg->tbls); } =20 static int qmp_ufs_com_init(struct qmp_ufs *qmp) @@ -893,25 +936,12 @@ static int qmp_ufs_power_on(struct phy *phy) { struct qmp_ufs *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; - void __iomem *tx =3D qmp->tx; - void __iomem *rx =3D qmp->rx; void __iomem *pcs =3D qmp->pcs; void __iomem *status; unsigned int val; int ret; =20 - qmp_ufs_serdes_init(qmp); - - /* Tx, Rx, and PCS configurations */ - qmp_ufs_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); - qmp_ufs_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); - - if (cfg->lanes >=3D 2) { - qmp_ufs_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); - qmp_ufs_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); - } - - qmp_ufs_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); + qmp_ufs_init_registers(qmp, cfg); =20 ret =3D reset_control_deassert(qmp->ufs_reset); if (ret) --=20 2.25.1 From nobody Mon Sep 15 05:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 791DCC46467 for ; Sat, 14 Jan 2023 07:11:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229597AbjANHLC (ORCPT ); Sat, 14 Jan 2023 02:11:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229726AbjANHKn (ORCPT ); Sat, 14 Jan 2023 02:10:43 -0500 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC9517A90 for ; Fri, 13 Jan 2023 23:10:32 -0800 (PST) Received: by mail-pl1-x62a.google.com with SMTP id y1so25575129plb.2 for ; Fri, 13 Jan 2023 23:10:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oDYubuABKCYBwbQruwwUwFz0u7uXQ46CcuCTpTGxi38=; b=pf6fAs3hb1DmPckJunY12j7JyQ1tkBXB9r/624sMaGryu1J9p/Nyx3CGXo0ivMZrV4 UWmb9AqkVKx3T5ygadLTeWUZapzbDHyMOfkzUz/OlWQxpKDpS0UaQe4JWBIZw6D95nb2 GLlcega7Q359rj8EBe245NVjZrbgPCeNzdhDzqiHeHsu5mDK/NkdXinVcAFUv72Ihigg 9JLpzCQ0eXCNovdxZCHkvLMZ+1PGr/iQ6tW5mAGh6tHZEfR0tu8cM2WySPks5yaoiQ7r SDc4lSWfsA95DJszAQpmBzTXxRsRAqqlnKPMAAJR2c/SCIp0Tn2FYME+Ec4pXrQZFKq5 U2YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oDYubuABKCYBwbQruwwUwFz0u7uXQ46CcuCTpTGxi38=; b=Vuy7qZ3dy1wKQmDS9YUthnLodYSnwJMz3HRTgPUvKyXR+evlpqy0StzZpISO8Y1r/U d9ZTYLfM/ZzJYpNrTJfllSYCoo8axA7yArxk7vWxnymtxafR0OGUd3t5IbmnfxiM5q1V qCeu45qlKOzp4LAREFlvnlmtdUb9NhgbB6paLuqAUEwS3rkdunSpuTeuoorzGrClJmfw ZzrXnxtEq3sC+OWDYgAOdEv5liKRiH88RSkEcxn/ABYSfDYwDxRmMxCEMCT8/pZOQ2QB mastvw1gNtpf54CXarBuIgHW6/ewA6AXiRTx878uS3O6X/U//CzZ+PSgOZCVDSZpR7WR 1XXg== X-Gm-Message-State: AFqh2kqpdXYz0rhvSr3JWjQBE4McHJf//eKYs3hu+sMnG0Ox25XggiyB 6aXknAD1Ea99blB6aDP+dgR5otqhBsu4r/w= X-Google-Smtp-Source: AMrXdXtPHSVEtucBA9uruPWUmhEAljkUs2peq8cKbos/vokW4WzkwZsgC3cWiLGEZBwca0twpfXN/w== X-Received: by 2002:a17:902:9695:b0:193:3314:540d with SMTP id n21-20020a170902969500b001933314540dmr19681376plp.51.1673680232559; Fri, 13 Jan 2023 23:10:32 -0800 (PST) Received: from localhost.localdomain ([220.158.159.156]) by smtp.gmail.com with ESMTPSA id q10-20020a170902e30a00b00192a04bc620sm15225358plc.295.2023.01.13.23.10.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 23:10:31 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 04/12] phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode Date: Sat, 14 Jan 2023 12:40:01 +0530 Message-Id: <20230114071009.88102-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add separate tables_hs_b instance to allow the PHY driver to configure the PHY in HS Series B mode. The individual SoC configs need to supply the serdes register setting in tables_hs_b and the UFS driver can request the Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 90d644fb321b..91285ddd663e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -552,6 +552,8 @@ struct qmp_phy_cfg { =20 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_cfg_tbls tbls; + /* Additional sequence for HS Series B */ + const struct qmp_phy_cfg_tbls tbls_hs_b; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -585,6 +587,7 @@ struct qmp_ufs { struct reset_control *ufs_reset; =20 struct phy *phy; + u32 mode; }; =20 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -848,6 +851,8 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const= struct qmp_phy_cfg_tbls static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_p= hy_cfg *cfg) { qmp_ufs_serdes_init(qmp, &cfg->tbls); + if (qmp->mode =3D=3D PHY_MODE_UFS_HS_B) + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b); qmp_ufs_lanes_init(qmp, &cfg->tbls); qmp_ufs_pcs_init(qmp, &cfg->tbls); } @@ -1018,9 +1023,19 @@ static int qmp_ufs_disable(struct phy *phy) return qmp_ufs_exit(phy); } =20 +static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submo= de) +{ + struct qmp_ufs *qmp =3D phy_get_drvdata(phy); + + qmp->mode =3D mode; + + return 0; +} + static const struct phy_ops qcom_qmp_ufs_phy_ops =3D { .power_on =3D qmp_ufs_enable, .power_off =3D qmp_ufs_disable, + .set_mode =3D qmp_ufs_set_mode, .owner =3D THIS_MODULE, }; =20 --=20 2.25.1 From nobody Mon Sep 15 05:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F14FC677F1 for ; Sat, 14 Jan 2023 07:11:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229578AbjANHLQ (ORCPT ); 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Fri, 13 Jan 2023 23:10:35 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 05/12] phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode Date: Sat, 14 Jan 2023 12:40:02 +0530 Message-Id: <20230114071009.88102-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add separate tables_hs_g4 instance to allow the PHY driver to configure the PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and PCS register setting in tables_hs_g4 and the UFS driver can request the Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 91285ddd663e..bb329cfbb96d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -20,6 +20,7 @@ #include #include =20 +#include #include "phy-qcom-qmp.h" #include "phy-qcom-qmp-pcs-ufs-v2.h" #include "phy-qcom-qmp-pcs-ufs-v3.h" @@ -554,6 +555,8 @@ struct qmp_phy_cfg { const struct qmp_phy_cfg_tbls tbls; /* Additional sequence for HS Series B */ const struct qmp_phy_cfg_tbls tbls_hs_b; + /* Additional sequence for HS G4 */ + const struct qmp_phy_cfg_tbls tbls_hs_g4; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -588,6 +591,7 @@ struct qmp_ufs { =20 struct phy *phy; u32 mode; + u32 submode; }; =20 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -854,7 +858,11 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp= , const struct qmp_phy_cfg if (qmp->mode =3D=3D PHY_MODE_UFS_HS_B) qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b); qmp_ufs_lanes_init(qmp, &cfg->tbls); + if (qmp->submode =3D=3D UFS_HS_G4) + qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4); qmp_ufs_pcs_init(qmp, &cfg->tbls); + if (qmp->submode =3D=3D UFS_HS_G4) + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4); } =20 static int qmp_ufs_com_init(struct qmp_ufs *qmp) @@ -1028,6 +1036,7 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy= _mode mode, int submode) struct qmp_ufs *qmp =3D phy_get_drvdata(phy); =20 qmp->mode =3D mode; + qmp->submode =3D submode; =20 return 0; } --=20 2.25.1 From nobody Mon Sep 15 05:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 851A6C3DA78 for ; Sat, 14 Jan 2023 07:11:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229836AbjANHLf (ORCPT ); Sat, 14 Jan 2023 02:11:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229457AbjANHLF (ORCPT ); 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Fri, 13 Jan 2023 23:10:39 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 06/12] phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_b Date: Sat, 14 Jan 2023 12:40:03 +0530 Message-Id: <20230114071009.88102-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since now there is support for configuring the HS Rate B mode properly, let's move the register setting to tbls_hs_b struct for all SoCs. This allows the PHY to be configured in Rate A initially and then in Rate B if requested by the UFS driver. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 37 +++++++++++++++++++++---- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index bb329cfbb96d..a7261744f971 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -219,8 +219,9 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), }; =20 @@ -296,8 +297,9 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), }; =20 @@ -362,8 +364,9 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), }; =20 @@ -411,7 +414,6 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[]= =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), - }; =20 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { @@ -449,8 +451,9 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), }; =20 @@ -684,6 +687,10 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { .pcs =3D sm8350_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8350_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -704,6 +711,10 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .pcs =3D sdm845_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sdm845_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -728,6 +739,10 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D { .pcs =3D sm6115_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm6115_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -750,6 +765,10 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .pcs =3D sm8150_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8150_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -770,6 +789,10 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .pcs =3D sm8350_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8350_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -790,6 +813,10 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .pcs =3D sm8350_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8350_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Mon Sep 15 05:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10311C3DA78 for ; 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Fri, 13 Jan 2023 23:10:43 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 07/12] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoC Date: Sat, 14 Jan 2023 12:40:04 +0530 Message-Id: <20230114071009.88102-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index a7261744f971..57d0744d18c2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -379,6 +379,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[= ] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), @@ -416,6 +420,25 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[= ] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), }; =20 +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), @@ -426,6 +449,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs= [] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] =3D { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -769,6 +797,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .serdes =3D sm8150_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8150_ufsphy_hs_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), + .rx =3D sm8150_ufsphy_hs_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), + .pcs =3D sm8150_ufsphy_hs_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Mon Sep 15 05:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 239B3C3DA78 for ; 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Fri, 13 Jan 2023 23:10:48 -0800 (PST) Received: from localhost.localdomain ([220.158.159.156]) by smtp.gmail.com with ESMTPSA id q10-20020a170902e30a00b00192a04bc620sm15225358plc.295.2023.01.13.23.10.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 23:10:48 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 08/12] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC Date: Sat, 14 Jan 2023 12:40:05 +0530 Message-Id: <20230114071009.88102-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. This also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 62 ++++++++++++++++++- 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/q= ualcomm/phy-qcom-qmp-pcs-ufs-v5.h index 43255e8bf038..07959964fcf6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h @@ -16,6 +16,7 @@ #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 57d0744d18c2..152b1b367df3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -454,6 +454,34 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_= g4_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), }; =20 +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), +}; + +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -812,6 +840,38 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .regs =3D ufsphy_v4_regs_layout, }; =20 +static const struct qmp_phy_cfg sm8250_ufsphy_cfg =3D { + .lanes =3D 2, + + .tbls =3D { + .serdes =3D sm8150_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx =3D sm8150_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx =3D sm8150_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs =3D sm8150_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + }, + .tbls_hs_b =3D { + .serdes =3D sm8150_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 =3D { + .tx =3D sm8250_ufsphy_hs_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), + .rx =3D sm8250_ufsphy_hs_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx), + .pcs =3D sm8150_ufsphy_hs_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, + .clk_list =3D sdm845_ufs_phy_clk_l, + .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D ufsphy_v4_regs_layout, +}; + static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 @@ -1364,7 +1424,7 @@ static const struct of_device_id qmp_ufs_of_match_tab= le[] =3D { .data =3D &sm8150_ufsphy_cfg, }, { .compatible =3D "qcom,sm8250-qmp-ufs-phy", - .data =3D &sm8150_ufsphy_cfg, + .data =3D &sm8250_ufsphy_cfg, }, { .compatible =3D "qcom,sm8350-qmp-ufs-phy", .data =3D &sm8350_ufsphy_cfg, --=20 2.25.1 From nobody Mon Sep 15 05:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA7D0C677F1 for ; Sat, 14 Jan 2023 07:11:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229880AbjANHLx (ORCPT ); Sat, 14 Jan 2023 02:11:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229828AbjANHLQ (ORCPT ); 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Fri, 13 Jan 2023 23:10:52 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 09/12] phy: qcom-qmp-ufs: Avoid setting HS G3 specific registers Date: Sat, 14 Jan 2023 12:40:06 +0530 Message-Id: <20230114071009.88102-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SM8350 default init sequence sets some PCS registers to HS G3, thereby disabling HS G4 mode. This has the effect on MPHY capability negotiation between the host and the device during link startup and causes the PA_MAXHSGEAR to G3 irrespective of device max gear. Due to that, the agreed gear speed determined by the UFS core will become G3 only and the platform won't run at G4. So, let's remove setting these registers for SM8350 as like other G4 compatible platforms. One downside of this is that, when the board design uses non-G4 compatible device, then MPHY will continue to run in the default mode (G4) even if UFSHCD runs in G3. But this is the case for other platforms as well. Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 152b1b367df3..421359ca62ba 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -572,13 +572,6 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs= [] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; 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Fri, 13 Jan 2023 23:10:57 -0800 (PST) Received: from localhost.localdomain ([220.158.159.156]) by smtp.gmail.com with ESMTPSA id q10-20020a170902e30a00b00192a04bc620sm15225358plc.295.2023.01.13.23.10.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 23:10:56 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 10/12] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoC Date: Sat, 14 Jan 2023 12:40:07 +0530 Message-Id: <20230114071009.88102-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8350 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 421359ca62ba..b784eed2eb1f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -576,6 +576,34 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs= [] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] =3D { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + struct qmp_ufs_offsets { u16 serdes; u16 pcs; @@ -882,6 +910,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .serdes =3D sm8350_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8350_ufsphy_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx =3D sm8350_ufsphy_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs =3D sm8350_ufsphy_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Mon Sep 15 05:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7D60C677F1 for ; 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Fri, 13 Jan 2023 23:11:00 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 11/12] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC Date: Sat, 14 Jan 2023 12:40:08 +0530 Message-Id: <20230114071009.88102-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index b784eed2eb1f..5cdac38c5fdc 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -942,6 +942,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .serdes =3D sm8350_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8350_ufsphy_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx =3D sm8350_ufsphy_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs =3D sm8350_ufsphy_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Mon Sep 15 05:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A09DC3DA78 for ; Sat, 14 Jan 2023 07:12:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229729AbjANHMN (ORCPT ); Sat, 14 Jan 2023 02:12:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229721AbjANHL2 (ORCPT ); Sat, 14 Jan 2023 02:11:28 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 272DE358D for ; Fri, 13 Jan 2023 23:11:06 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id bj3so21288707pjb.0 for ; Fri, 13 Jan 2023 23:11:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IrkQ9WSsGQbF4BcRajMW7kD5vzHIY33MCkjUr8TDVpY=; b=VL92hbwn5A4Ok8rWrnpvYu7rtsSghIgsZdlnq1gYZZAR7/lL3+dF2mCfmZWmklSDt+ brR7rLEu1ZtcSv9Hme0ZNsKhrzPg+1SGsapTBpEC3gWq23NpuMhTPjIsZ3UVXKYuroiX ie/YQ4s/Lj97ppJOT/Cb4LFAIbN5AsmUKjY9u52x8q//co1wzsUUoDgyVmp2Tu9d1i1c OOt573ShATOyuOjghyyZVW1cQLbHsC8T3oMXsyJFD6gXzAcBEugbAIm3qQiP9DxXeInJ /rRvkdgTUVz3Eegm+atXJ9imwCQIN07xQgyn9WUlWIybYZ1YqbkxWKkLt7ci5ItRaMEX PqtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IrkQ9WSsGQbF4BcRajMW7kD5vzHIY33MCkjUr8TDVpY=; b=K2o3f9o1U/1Fz8qa+uT8BlVTeX1kImlNwEHeWru7U0k0RUymJPrPCRA5+fikQohNjp xLPLSGRvwNKKN986aYjcyP1iySXanf8ZcCDmm3blCv+uLHHMj9zWpw6u20wR7dcv0Cwa YJ0NX8ADZ+IUct1X1nIs+fOgVf46bDofpjHuE6XwaNHLHVkJe50JO95DspBoEIjVejBu RV48GJ7Z25C/OLPEzK06CCSwg+FhccbRytmjdsQwtWkoHm7fCUbYPlGdjwbErLk7WZWH yFSDJV7oefJwisfkd4igD2858e/nkRkibrd39Bih0zNb3cLSndLnOtPRKS3OXuMCQh2x Rr+w== X-Gm-Message-State: AFqh2kqGRbwMd3fVi5MOpgRjSJJmjFxJpFoQESE/f/S8SP5SPV3/8jn3 jm6UKXOrlbXV8DJUNrTIA9iX X-Google-Smtp-Source: AMrXdXtoJu1I8bodRntcZZ+E141pki5zk8mww8k8+rbUfQcXcxDbyOBZt9WXtMYsV+DUq/OveKTRKg== X-Received: by 2002:a17:902:b413:b0:189:6ab3:9e64 with SMTP id x19-20020a170902b41300b001896ab39e64mr80347671plr.34.1673680265605; Fri, 13 Jan 2023 23:11:05 -0800 (PST) Received: from localhost.localdomain ([220.158.159.156]) by smtp.gmail.com with ESMTPSA id q10-20020a170902e30a00b00192a04bc620sm15225358plc.295.2023.01.13.23.11.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 23:11:04 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 12/12] phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoC Date: Sat, 14 Jan 2023 12:40:09 +0530 Message-Id: <20230114071009.88102-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SC8280XP SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 5cdac38c5fdc..110d8fb9309f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -768,6 +768,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { .serdes =3D sm8350_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8350_ufsphy_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx =3D sm8350_ufsphy_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs =3D sm8350_ufsphy_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1