From nobody Sat May 18 23:14:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43B20C63797 for ; Thu, 12 Jan 2023 21:02:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240636AbjALVCM (ORCPT ); Thu, 12 Jan 2023 16:02:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239946AbjALVAC (ORCPT ); Thu, 12 Jan 2023 16:00:02 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0C72389A; Thu, 12 Jan 2023 12:45:06 -0800 (PST) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30CKAW8B019045; Thu, 12 Jan 2023 20:45:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=FFDeHGdaPVwnu7Pd4aWCVaZM82GfVJL0BX/R+S663iQ=; b=NFSaR6gqsnRqZng1s9/0PDfJDH48a7SuZLYrBoip6aq5P/aljfJoP4aQLp2zjPDhPLQC pgRCAJsY7xT8Byt1LG/+BWKciUfwu22ft3VxIIBC+gO6EWcMW1lfRnCeHfUHXPbgj/4e kPxZxp4MGhx3ePJNd5fVPyBjQISZ2/mMgYq/b5ffOX9IB9a8BbqjAorMoVxQD9edn3EX HMWsEIN9vj7npd+4GGyRmLRPYkddrixfjc9PV0s020TK2GpTvk6IIPHSBir3//xNWJbJ zLmGSMfx14YVkMXIFlnXyLl9RO55oELCTg885voh3YrZlLfueq7jOnJ0JHkiqAHSvO9w xQ== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3n2fwpscn1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Jan 2023 20:45:02 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30CKj050031349 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Jan 2023 20:45:01 GMT Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 12 Jan 2023 12:45:00 -0800 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Michael Turquette , Konrad Dybcio , Stephen Boyd , Rob Herring , Krzysztof Kozlowski CC: Taniya Das , , , , , Melody Olvera Subject: [PATCH v6 1/2] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clocks Date: Thu, 12 Jan 2023 12:44:45 -0800 Message-ID: <20230112204446.30236-2-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230112204446.30236-1-quic_molvera@quicinc.com> References: <20230112204446.30236-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: dKYo62aVxdqTjPaEIeRN3auUA9uhBW0T X-Proofpoint-ORIG-GUID: dKYo62aVxdqTjPaEIeRN3auUA9uhBW0T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-12_12,2023-01-12_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 spamscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 bulkscore=0 suspectscore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301120147 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device tree bindings for global clock controller on QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,qdu1000-gcc.yaml | 51 +++++ include/dt-bindings/clock/qcom,qdu1000-gcc.h | 175 ++++++++++++++++++ 2 files changed, 226 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,qdu1000-gc= c.yaml create mode 100644 include/dt-bindings/clock/qcom,qdu1000-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml = b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml new file mode 100644 index 000000000000..767a9d03aa32 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qdu1000-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 + +maintainers: + - Melody Olvera + +description: | + Qualcomm global clock control module which supports the clocks, resets a= nd + power domains on QDU1000 and QRU1000 + + See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h + +properties: + compatible: + const: qcom,qdu1000-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 0 Phy Auxiliary clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible =3D "qcom,qdu1000-gcc"; + reg =3D <0x00100000 0x001f4200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie_0_pipe_clk>, <&pcie_0_phy_aux_clk>, + <&usb3_phy_wrapper_pipe_clk>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bind= ings/clock/qcom,qdu1000-gcc.h new file mode 100644 index 000000000000..ddbc6b825e80 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qdu1000-gcc.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights re= served. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H +#define _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H + +/* GCC clocks */ +#define GCC_GPLL0 0 +#define GCC_GPLL0_OUT_EVEN 1 +#define GCC_GPLL1 2 +#define GCC_GPLL2 3 +#define GCC_GPLL2_OUT_EVEN 4 +#define GCC_GPLL3 5 +#define GCC_GPLL4 6 +#define GCC_GPLL5 7 +#define GCC_GPLL5_OUT_EVEN 8 +#define GCC_GPLL6 9 +#define GCC_GPLL7 10 +#define GCC_GPLL8 11 +#define GCC_AGGRE_NOC_ECPRI_DMA_CLK 12 +#define GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC 13 +#define GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC 14 +#define GCC_BOOT_ROM_AHB_CLK 15 +#define GCC_CFG_NOC_ECPRI_CC_AHB_CLK 16 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 +#define GCC_DDRSS_ECPRI_DMA_CLK 18 +#define GCC_ECPRI_AHB_CLK 19 +#define GCC_ECPRI_CC_GPLL0_CLK_SRC 20 +#define GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC 21 +#define GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC 22 +#define GCC_ECPRI_CC_GPLL3_CLK_SRC 23 +#define GCC_ECPRI_CC_GPLL4_CLK_SRC 24 +#define GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC 25 +#define GCC_ECPRI_XO_CLK 26 +#define GCC_ETH_DBG_SNOC_AXI_CLK 27 +#define GCC_GEMNOC_PCIE_QX_CLK 28 +#define GCC_GP1_CLK 29 +#define GCC_GP1_CLK_SRC 30 +#define GCC_GP2_CLK 31 +#define GCC_GP2_CLK_SRC 32 +#define GCC_GP3_CLK 33 +#define GCC_GP3_CLK_SRC 34 +#define GCC_PCIE_0_AUX_CLK 35 +#define GCC_PCIE_0_AUX_CLK_SRC 36 +#define GCC_PCIE_0_CFG_AHB_CLK 37 +#define GCC_PCIE_0_CLKREF_EN 38 +#define GCC_PCIE_0_MSTR_AXI_CLK 39 +#define GCC_PCIE_0_PHY_AUX_CLK 40 +#define GCC_PCIE_0_PHY_RCHNG_CLK 41 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42 +#define GCC_PCIE_0_PIPE_CLK 43 +#define GCC_PCIE_0_SLV_AXI_CLK 44 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45 +#define GCC_PDM2_CLK 46 +#define GCC_PDM2_CLK_SRC 47 +#define GCC_PDM_AHB_CLK 48 +#define GCC_PDM_XO4_CLK 49 +#define GCC_QMIP_ANOC_PCIE_CLK 50 +#define GCC_QMIP_ECPRI_DMA0_CLK 51 +#define GCC_QMIP_ECPRI_DMA1_CLK 52 +#define GCC_QMIP_ECPRI_GSI_CLK 53 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 54 +#define GCC_QUPV3_WRAP0_CORE_CLK 55 +#define GCC_QUPV3_WRAP0_S0_CLK 56 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 57 +#define GCC_QUPV3_WRAP0_S1_CLK 58 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 59 +#define GCC_QUPV3_WRAP0_S2_CLK 60 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 61 +#define GCC_QUPV3_WRAP0_S3_CLK 62 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 63 +#define GCC_QUPV3_WRAP0_S4_CLK 64 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 65 +#define GCC_QUPV3_WRAP0_S5_CLK 66 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 67 +#define GCC_QUPV3_WRAP0_S6_CLK 68 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 69 +#define GCC_QUPV3_WRAP0_S7_CLK 70 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 71 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 72 +#define GCC_QUPV3_WRAP1_CORE_CLK 73 +#define GCC_QUPV3_WRAP1_S0_CLK 74 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 75 +#define GCC_QUPV3_WRAP1_S1_CLK 76 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 77 +#define GCC_QUPV3_WRAP1_S2_CLK 78 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 79 +#define GCC_QUPV3_WRAP1_S3_CLK 80 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 81 +#define GCC_QUPV3_WRAP1_S4_CLK 82 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 83 +#define GCC_QUPV3_WRAP1_S5_CLK 84 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 85 +#define GCC_QUPV3_WRAP1_S6_CLK 86 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 87 +#define GCC_QUPV3_WRAP1_S7_CLK 88 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 89 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 90 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 91 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 92 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 93 +#define GCC_SDCC5_AHB_CLK 94 +#define GCC_SDCC5_APPS_CLK 95 +#define GCC_SDCC5_APPS_CLK_SRC 96 +#define GCC_SDCC5_ICE_CORE_CLK 97 +#define GCC_SDCC5_ICE_CORE_CLK_SRC 98 +#define GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK 99 +#define GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK 100 +#define GCC_SNOC_CNOC_PCIE_QX_CLK 101 +#define GCC_SNOC_PCIE_SF_CENTER_QX_CLK 102 +#define GCC_SNOC_PCIE_SF_SOUTH_QX_CLK 103 +#define GCC_TSC_CFG_AHB_CLK 104 +#define GCC_TSC_CLK_SRC 105 +#define GCC_TSC_CNTR_CLK 106 +#define GCC_TSC_ETU_CLK 107 +#define GCC_USB2_CLKREF_EN 108 +#define GCC_USB30_PRIM_MASTER_CLK 109 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 113 +#define GCC_USB30_PRIM_SLEEP_CLK 114 +#define GCC_USB3_PRIM_PHY_AUX_CLK 115 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118 +#define GCC_SM_BUS_AHB_CLK 119 +#define GCC_SM_BUS_XO_CLK 120 +#define GCC_SM_BUS_XO_CLK_SRC 121 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 122 +#define GCC_ETH_100G_C2C_HM_APB_CLK 123 +#define GCC_ETH_100G_FH_HM_APB_0_CLK 124 +#define GCC_ETH_100G_FH_HM_APB_1_CLK 125 +#define GCC_ETH_100G_FH_HM_APB_2_CLK 126 +#define GCC_ETH_DBG_C2C_HM_APB_CLK 127 +#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128 +#define GCC_PCIE_0_PIPE_CLK_SRC 129 +#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130 + +/* GCC resets */ +#define GCC_ECPRI_CC_BCR 0 +#define GCC_ECPRI_SS_BCR 1 +#define GCC_ETH_WRAPPER_BCR 2 +#define GCC_PCIE_0_BCR 3 +#define GCC_PCIE_0_LINK_DOWN_BCR 4 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_PHY_BCR 6 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PCIE_PHY_CFG_AHB_BCR 8 +#define GCC_PCIE_PHY_COM_BCR 9 +#define GCC_PDM_BCR 10 +#define GCC_QUPV3_WRAPPER_0_BCR 11 +#define GCC_QUPV3_WRAPPER_1_BCR 12 +#define GCC_QUSB2PHY_PRIM_BCR 13 +#define GCC_QUSB2PHY_SEC_BCR 14 +#define GCC_SDCC5_BCR 15 +#define GCC_TCSR_PCIE_BCR 16 +#define GCC_TSC_BCR 17 +#define GCC_USB30_PRIM_BCR 18 +#define GCC_USB3_DP_PHY_PRIM_BCR 19 +#define GCC_USB3_DP_PHY_SEC_BCR 20 +#define GCC_USB3_PHY_PRIM_BCR 21 +#define GCC_USB3_PHY_SEC_BCR 22 +#define GCC_USB3PHY_PHY_PRIM_BCR 23 +#define GCC_USB3PHY_PHY_SEC_BCR 24 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 25 + +/* GCC power domains */ +#define PCIE_0_GDSC 0 +#define PCIE_0_PHY_GDSC 1 +#define USB30_PRIM_GDSC 2 + +#endif --=20 2.38.1 From nobody Sat May 18 23:14:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABD33C63797 for ; Thu, 12 Jan 2023 21:02:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240880AbjALVCU (ORCPT ); Thu, 12 Jan 2023 16:02:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239077AbjALVAB (ORCPT ); Thu, 12 Jan 2023 16:00:01 -0500 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FAAD3882; Thu, 12 Jan 2023 12:45:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1673556302; x=1705092302; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o3zzME6+AfsNL0Yjdoltmz06CR5HyW6XxD191TQIr0w=; b=SXKHHEc0Sfvw4Brvm5WgQSEHDKnJwPU0xjsvqt4j+fIM97AQBIfr0XfG 0rppPZ26XpxuhsQ33HTTXTRPXfN22/JHwp6VJKvR7HRJWkOAlt0rRGkWQ zZY12KUCij8TJsmXNoxa27HnuB4dsJAHlgg0bvJ3by7ai2yocjTVYQ0MJ U=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 12 Jan 2023 12:45:01 -0800 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 12:45:01 -0800 Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 12 Jan 2023 12:45:00 -0800 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Michael Turquette , Konrad Dybcio , Stephen Boyd , Rob Herring , Krzysztof Kozlowski CC: Taniya Das , , , , , Melody Olvera , Dmitry Baryshkov Subject: [PATCH v6 2/2] clk: qcom: Add QDU1000 and QRU1000 GCC support Date: Thu, 12 Jan 2023 12:44:46 -0800 Message-ID: <20230112204446.30236-3-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230112204446.30236-1-quic_molvera@quicinc.com> References: <20230112204446.30236-1-quic_molvera@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Taniya Das Add Global Clock Controller (GCC) support for QDU1000 and QRU1000 SoCs. Signed-off-by: Taniya Das Signed-off-by: Melody Olvera Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-qdu1000.c | 2653 ++++++++++++++++++++++++++++++++ 3 files changed, 2662 insertions(+) create mode 100644 drivers/clk/qcom/gcc-qdu1000.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 1b6615fe1dba..da65bb9da5ce 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -569,6 +569,14 @@ config QCS_Q6SSTOP_404 Say Y if you want to use the Q6SSTOP branch clocks of the WCSS clock controller to reset the Q6SSTOP subsystem. =20 +config QDU_GCC_1000 + tristate "QDU1000/QRU1000 Global Clock Controller" + select QCOM_GDSC + help + Support for the global clock controller on QDU1000 and + QRU1000 devices. Say Y if you want to use peripheral + devices such as UART, SPI, I2C, USB, SD, PCIe, etc. + config SDM_GCC_845 tristate "SDM845/SDM670 Global Clock Controller" select QCOM_GDSC diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 6c589f671003..eac136bb13e9 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_QCM_DISPCC_2290) +=3D dispcc-qcm2290.o obj-$(CONFIG_QCS_GCC_404) +=3D gcc-qcs404.o obj-$(CONFIG_QCS_Q6SSTOP_404) +=3D q6sstop-qcs404.o obj-$(CONFIG_QCS_TURING_404) +=3D turingcc-qcs404.o +obj-$(CONFIG_QDU_GCC_1000) +=3D gcc-qdu1000.o obj-$(CONFIG_SC_CAMCC_7180) +=3D camcc-sc7180.o obj-$(CONFIG_SC_CAMCC_7280) +=3D camcc-sc7280.o obj-$(CONFIG_SC_DISPCC_7180) +=3D dispcc-sc7180.o diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c new file mode 100644 index 000000000000..376f1667a1ec --- /dev/null +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -0,0 +1,2653 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "reset.h" + +enum { + P_BI_TCXO, + P_GCC_GPLL0_OUT_EVEN, + P_GCC_GPLL0_OUT_MAIN, + P_GCC_GPLL1_OUT_MAIN, + P_GCC_GPLL2_OUT_MAIN, + P_GCC_GPLL3_OUT_MAIN, + P_GCC_GPLL4_OUT_MAIN, + P_GCC_GPLL5_OUT_MAIN, + P_GCC_GPLL6_OUT_MAIN, + P_GCC_GPLL7_OUT_MAIN, + P_GCC_GPLL8_OUT_MAIN, + P_PCIE_0_PHY_AUX_CLK, + P_PCIE_0_PIPE_CLK, + P_SLEEP_CLK, + P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, +}; + +enum { + DT_TCXO_IDX, + DT_SLEEP_CLK_IDX, + DT_PCIE_0_PIPE_CLK_IDX, + DT_PCIE_0_PHY_AUX_CLK_IDX, + DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX, +}; + +static struct clk_alpha_pll gcc_gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x62018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_TCXO_IDX, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] =3D { + { 0x1, 2 } +}; + +static struct clk_alpha_pll_postdiv gcc_gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gcc_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static struct clk_alpha_pll gcc_gpll1 =3D { + .offset =3D 0x1000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x62018, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_TCXO_IDX, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv gcc_gpll1_out_even =3D { + .offset =3D 0x1000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gcc_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll1_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll1.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static struct clk_alpha_pll gcc_gpll2 =3D { + .offset =3D 0x2000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x62018, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_TCXO_IDX, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv gcc_gpll2_out_even =3D { + .offset =3D 0x2000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gcc_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll2_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll2.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static struct clk_alpha_pll gcc_gpll3 =3D { + .offset =3D 0x3000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x62018, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll3", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_TCXO_IDX, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll4 =3D { + .offset =3D 0x4000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x62018, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll4", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_TCXO_IDX, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll5 =3D { + .offset =3D 0x5000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x62018, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll5", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_TCXO_IDX, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv gcc_gpll5_out_even =3D { + .offset =3D 0x5000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gcc_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll5_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll5.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static struct clk_alpha_pll gcc_gpll6 =3D { + .offset =3D 0x6000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x62018, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll6", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_TCXO_IDX, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll7 =3D { + .offset =3D 0x7000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x62018, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll7", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_TCXO_IDX, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll8 =3D { + .offset =3D 0x8000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x62018, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll8", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_TCXO_IDX, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_TCXO_IDX }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_TCXO_IDX }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK_IDX }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL5_OUT_MAIN, 3 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_TCXO_IDX }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll5.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_TCXO_IDX }, + { .index =3D DT_SLEEP_CLK_IDX }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL2_OUT_MAIN, 2 }, + { P_GCC_GPLL5_OUT_MAIN, 3 }, + { P_GCC_GPLL1_OUT_MAIN, 4 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, + { P_GCC_GPLL3_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .index =3D DT_TCXO_IDX }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll2.clkr.hw }, + { .hw =3D &gcc_gpll5.clkr.hw }, + { .hw =3D &gcc_gpll1.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, + { .hw =3D &gcc_gpll3.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL2_OUT_MAIN, 2 }, + { P_GCC_GPLL6_OUT_MAIN, 3 }, + { P_GCC_GPLL1_OUT_MAIN, 4 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, + { P_GCC_GPLL3_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .index =3D DT_TCXO_IDX }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll2.clkr.hw }, + { .hw =3D &gcc_gpll6.clkr.hw }, + { .hw =3D &gcc_gpll1.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, + { .hw =3D &gcc_gpll3.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_6[] =3D { + { P_PCIE_0_PHY_AUX_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_6[] =3D { + { .index =3D DT_PCIE_0_PHY_AUX_CLK_IDX }, + { .index =3D DT_TCXO_IDX }, +}; + +static const struct parent_map gcc_parent_map_7[] =3D { + { P_PCIE_0_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_7[] =3D { + { .index =3D DT_PCIE_0_PIPE_CLK_IDX }, + { .index =3D DT_TCXO_IDX }, +}; + +static const struct parent_map gcc_parent_map_8[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL8_OUT_MAIN, 2 }, + { P_GCC_GPLL5_OUT_MAIN, 3 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_8[] =3D { + { .index =3D DT_TCXO_IDX }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll8.clkr.hw }, + { .hw =3D &gcc_gpll5.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_9[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL2_OUT_MAIN, 2 }, + { P_GCC_GPLL5_OUT_MAIN, 3 }, + { P_GCC_GPLL7_OUT_MAIN, 4 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_9[] =3D { + { .index =3D DT_TCXO_IDX }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll2.clkr.hw }, + { .hw =3D &gcc_gpll5.clkr.hw }, + { .hw =3D &gcc_gpll7.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_10[] =3D { + { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_10[] =3D { + { .index =3D DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX }, + { .index =3D DT_TCXO_IDX }, +}; + +static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src =3D { + .reg =3D 0x9d080, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_6, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src =3D { + .reg =3D 0x9d064, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_7, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_pipe_clk_src", + .parent_data =3D gcc_parent_data_7, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_7), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src =3D { + .reg =3D 0x4906c, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_10, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_pipe_clk_src", + .parent_data =3D gcc_parent_data_10, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_10), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_dma_clk_src[] =3D { + F(466500000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0), + F(500000000, P_GCC_GPLL2_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src =3D { + .cmd_rcgr =3D 0x92020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_aggre_noc_ecpri_dma_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_noc_ecpri_dma_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_gsi_clk_src[] =3D { + F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0), + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src =3D { + .cmd_rcgr =3D 0x92038, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_aggre_noc_ecpri_gsi_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_noc_ecpri_gsi_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] =3D { + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x74004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x75004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src =3D { + .cmd_rcgr =3D 0x76004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp3_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_0_aux_clk_src =3D { + .cmd_rcgr =3D 0x9d068, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_aux_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x9d04c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] =3D { + F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src =3D { + .cmd_rcgr =3D 0x43010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pdm2_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] =3D { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src =3D { + .cmd_rcgr =3D 0x27154, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src =3D { + .cmd_rcgr =3D 0x27288, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src =3D { + .cmd_rcgr =3D 0x273bc, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src =3D { + .cmd_rcgr =3D 0x274f0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src =3D { + .cmd_rcgr =3D 0x27624, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] =3D { + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src =3D { + .cmd_rcgr =3D 0x27758, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s5_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s6_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src =3D { + .cmd_rcgr =3D 0x2788c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s6_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s7_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src =3D { + .cmd_rcgr =3D 0x279c0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s7_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src =3D { + .cmd_rcgr =3D 0x28154, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src =3D { + .cmd_rcgr =3D 0x28288, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src =3D { + .cmd_rcgr =3D 0x283bc, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src =3D { + .cmd_rcgr =3D 0x284f0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src =3D { + .cmd_rcgr =3D 0x28624, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src =3D { + .cmd_rcgr =3D 0x28758, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s6_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src =3D { + .cmd_rcgr =3D 0x2888c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s6_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s7_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src =3D { + .cmd_rcgr =3D 0x289c0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s7_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc5_apps_clk_src[] =3D { + F(144000, P_BI_TCXO, 16, 3, 25), + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(20000000, P_GCC_GPLL0_OUT_MAIN, 10, 1, 3), + F(25000000, P_GCC_GPLL0_OUT_MAIN, 12, 1, 2), + F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(192000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), + F(384000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc5_apps_clk_src =3D { + .cmd_rcgr =3D 0x3b034, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_8, + .freq_tbl =3D ftbl_gcc_sdcc5_apps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc5_apps_clk_src", + .parent_data =3D gcc_parent_data_8, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc5_ice_core_clk_src[] =3D { + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x3b01c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_sdcc5_ice_core_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc5_ice_core_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_sm_bus_xo_clk_src =3D { + .cmd_rcgr =3D 0x5b00c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sm_bus_xo_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_tsc_clk_src[] =3D { + F(500000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_tsc_clk_src =3D { + .cmd_rcgr =3D 0x57010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_9, + .freq_tbl =3D ftbl_gcc_tsc_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_tsc_clk_src", + .parent_data =3D gcc_parent_data_9, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_9), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] =3D { + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_master_clk_src =3D { + .cmd_rcgr =3D 0x49028, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb30_prim_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x49044, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x49070, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0x4905c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_aggre_noc_ecpri_dma_clk =3D { + .halt_reg =3D 0x92008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x92008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x92008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_noc_ecpri_dma_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_noc_ecpri_gsi_clk =3D { + .halt_reg =3D 0x9201c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x9201c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9201c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_noc_ecpri_gsi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk =3D { + .halt_reg =3D 0x48004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x48004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_boot_rom_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_ecpri_cc_ahb_clk =3D { + .halt_reg =3D 0x3e004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x3e004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3e004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_ecpri_cc_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk =3D { + .halt_reg =3D 0x8401c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8401c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8401c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ddrss_ecpri_dma_clk =3D { + .halt_reg =3D 0x54030, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x54030, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x54030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ddrss_ecpri_dma_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gcc_ecpri_ahb_clk =3D { + .halt_reg =3D 0x3a008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x3a008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3a008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ecpri_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ecpri_cc_gpll0_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x62010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ecpri_cc_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ecpri_cc_gpll1_even_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x62010, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ecpri_cc_gpll1_even_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll1_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ecpri_cc_gpll2_even_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x62010, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ecpri_cc_gpll2_even_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll2_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ecpri_cc_gpll3_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x62010, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ecpri_cc_gpll3_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll3.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ecpri_cc_gpll4_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x62010, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ecpri_cc_gpll4_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll4.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ecpri_cc_gpll5_even_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x62010, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ecpri_cc_gpll5_even_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll5_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ecpri_xo_clk =3D { + .halt_reg =3D 0x3a004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3a004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ecpri_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eth_100g_c2c_hm_apb_clk =3D { + .halt_reg =3D 0x39010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x39010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_eth_100g_c2c_hm_apb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eth_100g_fh_hm_apb_0_clk =3D { + .halt_reg =3D 0x39004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x39004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_eth_100g_fh_hm_apb_0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eth_100g_fh_hm_apb_1_clk =3D { + .halt_reg =3D 0x39008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x39008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_eth_100g_fh_hm_apb_1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eth_100g_fh_hm_apb_2_clk =3D { + .halt_reg =3D 0x3900c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3900c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_eth_100g_fh_hm_apb_2_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eth_dbg_c2c_hm_apb_clk =3D { + .halt_reg =3D 0x39014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x39014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_eth_dbg_c2c_hm_apb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eth_dbg_snoc_axi_clk =3D { + .halt_reg =3D 0x3901c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x3901c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3901c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_eth_dbg_snoc_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gemnoc_pcie_qx_clk =3D { + .halt_reg =3D 0x5402c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x5402c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gemnoc_pcie_qx_clk", + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk =3D { + .halt_reg =3D 0x74000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x74000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk =3D { + .halt_reg =3D 0x75000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x75000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk =3D { + .halt_reg =3D 0x76000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x76000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_aux_clk =3D { + .halt_reg =3D 0x9d030, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x9d030, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(29), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_cfg_ahb_clk =3D { + .halt_reg =3D 0x9d02c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x9d02c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(28), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_clkref_en =3D { + .halt_reg =3D 0x9c004, + .halt_bit =3D 31, + .halt_check =3D BRANCH_HALT_ENABLE, + .clkr =3D { + .enable_reg =3D 0x9c004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_clkref_en", + .ops =3D &clk_branch_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_mstr_axi_clk =3D { + .halt_reg =3D 0x9d024, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x9d024, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(27), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_phy_aux_clk =3D { + .halt_reg =3D 0x9d038, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x9d038, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_0_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_phy_rchng_clk =3D { + .halt_reg =3D 0x9d048, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x9d048, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_pipe_clk =3D { + .halt_reg =3D 0x9d040, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x9d040, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(30), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_0_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_slv_axi_clk =3D { + .halt_reg =3D 0x9d01c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x9d01c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x9d018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x9d018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk =3D { + .halt_reg =3D 0x4300c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4300c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk =3D { + .halt_reg =3D 0x43004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x43004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x43004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk =3D { + .halt_reg =3D 0x43008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x43008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_xo4_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_anoc_pcie_clk =3D { + .halt_reg =3D 0x84044, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x84044, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x84044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_anoc_pcie_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_ecpri_dma0_clk =3D { + .halt_reg =3D 0x84038, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x84038, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x84038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_ecpri_dma0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_ecpri_dma1_clk =3D { + .halt_reg =3D 0x8403c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8403c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8403c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_ecpri_dma1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_ecpri_gsi_clk =3D { + .halt_reg =3D 0x84040, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x84040, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x84040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_ecpri_gsi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk =3D { + .halt_reg =3D 0x27018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(9), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk =3D { + .halt_reg =3D 0x2700c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk =3D { + .halt_reg =3D 0x2714c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk =3D { + .halt_reg =3D 0x27280, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(11), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk =3D { + .halt_reg =3D 0x273b4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk =3D { + .halt_reg =3D 0x274e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk =3D { + .halt_reg =3D 0x2761c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk =3D { + .halt_reg =3D 0x27750, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s6_clk =3D { + .halt_reg =3D 0x27884, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s7_clk =3D { + .halt_reg =3D 0x279b8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s7_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk =3D { + .halt_reg =3D 0x28018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_clk =3D { + .halt_reg =3D 0x2800c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s0_clk =3D { + .halt_reg =3D 0x2814c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s1_clk =3D { + .halt_reg =3D 0x28280, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s2_clk =3D { + .halt_reg =3D 0x283b4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s3_clk =3D { + .halt_reg =3D 0x284e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s4_clk =3D { + .halt_reg =3D 0x2861c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s5_clk =3D { + .halt_reg =3D 0x28750, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(27), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s6_clk =3D { + .halt_reg =3D 0x28884, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(28), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s7_clk =3D { + .halt_reg =3D 0x289b8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(29), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s7_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk =3D { + .halt_reg =3D 0x27004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x27004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_0_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk =3D { + .halt_reg =3D 0x27008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x27008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_0_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk =3D { + .halt_reg =3D 0x28004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x28004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_1_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk =3D { + .halt_reg =3D 0x28008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x28008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62008, + .enable_mask =3D BIT(21), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_1_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc5_ahb_clk =3D { + .halt_reg =3D 0x3b00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3b00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc5_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc5_apps_clk =3D { + .halt_reg =3D 0x3b004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3b004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc5_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc5_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc5_ice_core_clk =3D { + .halt_reg =3D 0x3b010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3b010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc5_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc5_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sm_bus_ahb_clk =3D { + .halt_reg =3D 0x5b004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5b004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sm_bus_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sm_bus_xo_clk =3D { + .halt_reg =3D 0x5b008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5b008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sm_bus_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sm_bus_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_qx_clk =3D { + .halt_reg =3D 0x9200c, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x9200c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(11), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_cnoc_gemnoc_pcie_qx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk =3D { + .halt_reg =3D 0x92010, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x92010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_cnoc_pcie_qx_clk =3D { + .halt_reg =3D 0x84030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x84030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_cnoc_pcie_qx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_pcie_sf_center_qx_clk =3D { + .halt_reg =3D 0x92014, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x92014, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_pcie_sf_center_qx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_pcie_sf_south_qx_clk =3D { + .halt_reg =3D 0x92018, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x92018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x62000, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_pcie_sf_south_qx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tsc_cfg_ahb_clk =3D { + .halt_reg =3D 0x5700c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5700c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_tsc_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tsc_cntr_clk =3D { + .halt_reg =3D 0x57004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x57004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_tsc_cntr_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_tsc_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tsc_etu_clk =3D { + .halt_reg =3D 0x57008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x57008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_tsc_etu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_tsc_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb2_clkref_en =3D { + .halt_reg =3D 0x9c008, + .halt_bit =3D 31, + .halt_check =3D BRANCH_HALT_ENABLE, + .clkr =3D { + .enable_reg =3D 0x9c008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb2_clkref_en", + .ops =3D &clk_branch_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_master_clk =3D { + .halt_reg =3D 0x49018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x49018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_mock_utmi_clk =3D { + .halt_reg =3D 0x49024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x49024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_sleep_clk =3D { + .halt_reg =3D 0x49020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x49020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_aux_clk =3D { + .halt_reg =3D 0x49060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x49060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk =3D { + .halt_reg =3D 0x49064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x49064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_com_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_pipe_clk =3D { + .halt_reg =3D 0x49068, + .halt_check =3D BRANCH_HALT_DELAY, + .hwcg_reg =3D 0x49068, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x49068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gcc_qdu1000_clocks[] =3D { + [GCC_AGGRE_NOC_ECPRI_DMA_CLK] =3D &gcc_aggre_noc_ecpri_dma_clk.clkr, + [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] =3D &gcc_aggre_noc_ecpri_dma_clk_src.cl= kr, + [GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC] =3D &gcc_aggre_noc_ecpri_gsi_clk_src.cl= kr, + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_CFG_NOC_ECPRI_CC_AHB_CLK] =3D &gcc_cfg_noc_ecpri_cc_ahb_clk.clkr, + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_cfg_noc_usb3_prim_axi_clk.clkr, + [GCC_DDRSS_ECPRI_DMA_CLK] =3D &gcc_ddrss_ecpri_dma_clk.clkr, + [GCC_ECPRI_AHB_CLK] =3D &gcc_ecpri_ahb_clk.clkr, + [GCC_ECPRI_CC_GPLL0_CLK_SRC] =3D &gcc_ecpri_cc_gpll0_clk_src.clkr, + [GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC] =3D &gcc_ecpri_cc_gpll1_even_clk_src.cl= kr, + [GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC] =3D &gcc_ecpri_cc_gpll2_even_clk_src.cl= kr, + [GCC_ECPRI_CC_GPLL3_CLK_SRC] =3D &gcc_ecpri_cc_gpll3_clk_src.clkr, + [GCC_ECPRI_CC_GPLL4_CLK_SRC] =3D &gcc_ecpri_cc_gpll4_clk_src.clkr, + [GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC] =3D &gcc_ecpri_cc_gpll5_even_clk_src.cl= kr, + [GCC_ECPRI_XO_CLK] =3D &gcc_ecpri_xo_clk.clkr, + [GCC_ETH_DBG_SNOC_AXI_CLK] =3D &gcc_eth_dbg_snoc_axi_clk.clkr, + [GCC_GEMNOC_PCIE_QX_CLK] =3D &gcc_gemnoc_pcie_qx_clk.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, + [GCC_GPLL0] =3D &gcc_gpll0.clkr, + [GCC_GPLL0_OUT_EVEN] =3D &gcc_gpll0_out_even.clkr, + [GCC_GPLL1] =3D &gcc_gpll1.clkr, + [GCC_GPLL2] =3D &gcc_gpll2.clkr, + [GCC_GPLL2_OUT_EVEN] =3D &gcc_gpll2_out_even.clkr, + [GCC_GPLL3] =3D &gcc_gpll3.clkr, + [GCC_GPLL4] =3D &gcc_gpll4.clkr, + [GCC_GPLL5] =3D &gcc_gpll5.clkr, + [GCC_GPLL5_OUT_EVEN] =3D &gcc_gpll5_out_even.clkr, + [GCC_GPLL6] =3D &gcc_gpll6.clkr, + [GCC_GPLL7] =3D &gcc_gpll7.clkr, + [GCC_GPLL8] =3D &gcc_gpll8.clkr, + [GCC_PCIE_0_AUX_CLK] =3D &gcc_pcie_0_aux_clk.clkr, + [GCC_PCIE_0_AUX_CLK_SRC] =3D &gcc_pcie_0_aux_clk_src.clkr, + [GCC_PCIE_0_CFG_AHB_CLK] =3D &gcc_pcie_0_cfg_ahb_clk.clkr, + [GCC_PCIE_0_CLKREF_EN] =3D &gcc_pcie_0_clkref_en.clkr, + [GCC_PCIE_0_MSTR_AXI_CLK] =3D &gcc_pcie_0_mstr_axi_clk.clkr, + [GCC_PCIE_0_PHY_AUX_CLK] =3D &gcc_pcie_0_phy_aux_clk.clkr, + [GCC_PCIE_0_PHY_RCHNG_CLK] =3D &gcc_pcie_0_phy_rchng_clk.clkr, + [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_0_phy_rchng_clk_src.clkr, + [GCC_PCIE_0_PIPE_CLK] =3D &gcc_pcie_0_pipe_clk.clkr, + [GCC_PCIE_0_SLV_AXI_CLK] =3D &gcc_pcie_0_slv_axi_clk.clkr, + [GCC_PCIE_0_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_0_slv_q2a_axi_clk.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] =3D &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] =3D &gcc_pdm_xo4_clk.clkr, + [GCC_QMIP_ANOC_PCIE_CLK] =3D &gcc_qmip_anoc_pcie_clk.clkr, + [GCC_QMIP_ECPRI_DMA0_CLK] =3D &gcc_qmip_ecpri_dma0_clk.clkr, + [GCC_QMIP_ECPRI_DMA1_CLK] =3D &gcc_qmip_ecpri_dma1_clk.clkr, + [GCC_QMIP_ECPRI_GSI_CLK] =3D &gcc_qmip_ecpri_gsi_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] =3D &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] =3D &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] =3D &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] =3D &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] =3D &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] =3D &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] =3D &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] =3D &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] =3D &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] =3D &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] =3D &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] =3D &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP0_S5_CLK] =3D &gcc_qupv3_wrap0_s5_clk.clkr, + [GCC_QUPV3_WRAP0_S5_CLK_SRC] =3D &gcc_qupv3_wrap0_s5_clk_src.clkr, + [GCC_QUPV3_WRAP0_S6_CLK] =3D &gcc_qupv3_wrap0_s6_clk.clkr, + [GCC_QUPV3_WRAP0_S6_CLK_SRC] =3D &gcc_qupv3_wrap0_s6_clk_src.clkr, + [GCC_QUPV3_WRAP0_S7_CLK] =3D &gcc_qupv3_wrap0_s7_clk.clkr, + [GCC_QUPV3_WRAP0_S7_CLK_SRC] =3D &gcc_qupv3_wrap0_s7_clk_src.clkr, + [GCC_QUPV3_WRAP1_CORE_2X_CLK] =3D &gcc_qupv3_wrap1_core_2x_clk.clkr, + [GCC_QUPV3_WRAP1_CORE_CLK] =3D &gcc_qupv3_wrap1_core_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK] =3D &gcc_qupv3_wrap1_s0_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK_SRC] =3D &gcc_qupv3_wrap1_s0_clk_src.clkr, + [GCC_QUPV3_WRAP1_S1_CLK] =3D &gcc_qupv3_wrap1_s1_clk.clkr, + [GCC_QUPV3_WRAP1_S1_CLK_SRC] =3D &gcc_qupv3_wrap1_s1_clk_src.clkr, + [GCC_QUPV3_WRAP1_S2_CLK] =3D &gcc_qupv3_wrap1_s2_clk.clkr, + [GCC_QUPV3_WRAP1_S2_CLK_SRC] =3D &gcc_qupv3_wrap1_s2_clk_src.clkr, + [GCC_QUPV3_WRAP1_S3_CLK] =3D &gcc_qupv3_wrap1_s3_clk.clkr, + [GCC_QUPV3_WRAP1_S3_CLK_SRC] =3D &gcc_qupv3_wrap1_s3_clk_src.clkr, + [GCC_QUPV3_WRAP1_S4_CLK] =3D &gcc_qupv3_wrap1_s4_clk.clkr, + [GCC_QUPV3_WRAP1_S4_CLK_SRC] =3D &gcc_qupv3_wrap1_s4_clk_src.clkr, + [GCC_QUPV3_WRAP1_S5_CLK] =3D &gcc_qupv3_wrap1_s5_clk.clkr, + [GCC_QUPV3_WRAP1_S5_CLK_SRC] =3D &gcc_qupv3_wrap1_s5_clk_src.clkr, + [GCC_QUPV3_WRAP1_S6_CLK] =3D &gcc_qupv3_wrap1_s6_clk.clkr, + [GCC_QUPV3_WRAP1_S6_CLK_SRC] =3D &gcc_qupv3_wrap1_s6_clk_src.clkr, + [GCC_QUPV3_WRAP1_S7_CLK] =3D &gcc_qupv3_wrap1_s7_clk.clkr, + [GCC_QUPV3_WRAP1_S7_CLK_SRC] =3D &gcc_qupv3_wrap1_s7_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] =3D &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] =3D &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_M_AHB_CLK] =3D &gcc_qupv3_wrap_1_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_S_AHB_CLK] =3D &gcc_qupv3_wrap_1_s_ahb_clk.clkr, + [GCC_SDCC5_AHB_CLK] =3D &gcc_sdcc5_ahb_clk.clkr, + [GCC_SDCC5_APPS_CLK] =3D &gcc_sdcc5_apps_clk.clkr, + [GCC_SDCC5_APPS_CLK_SRC] =3D &gcc_sdcc5_apps_clk_src.clkr, + [GCC_SDCC5_ICE_CORE_CLK] =3D &gcc_sdcc5_ice_core_clk.clkr, + [GCC_SDCC5_ICE_CORE_CLK_SRC] =3D &gcc_sdcc5_ice_core_clk_src.clkr, + [GCC_SM_BUS_AHB_CLK] =3D &gcc_sm_bus_ahb_clk.clkr, + [GCC_SM_BUS_XO_CLK] =3D &gcc_sm_bus_xo_clk.clkr, + [GCC_SM_BUS_XO_CLK_SRC] =3D &gcc_sm_bus_xo_clk_src.clkr, + [GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK] =3D &gcc_snoc_cnoc_gemnoc_pcie_qx_clk.= clkr, + [GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK] =3D &gcc_snoc_cnoc_gemnoc_pcie_s= outh_qx_clk.clkr, + [GCC_SNOC_CNOC_PCIE_QX_CLK] =3D &gcc_snoc_cnoc_pcie_qx_clk.clkr, + [GCC_SNOC_PCIE_SF_CENTER_QX_CLK] =3D &gcc_snoc_pcie_sf_center_qx_clk.clkr, + [GCC_SNOC_PCIE_SF_SOUTH_QX_CLK] =3D &gcc_snoc_pcie_sf_south_qx_clk.clkr, + [GCC_TSC_CFG_AHB_CLK] =3D &gcc_tsc_cfg_ahb_clk.clkr, + [GCC_TSC_CLK_SRC] =3D &gcc_tsc_clk_src.clkr, + [GCC_TSC_CNTR_CLK] =3D &gcc_tsc_cntr_clk.clkr, + [GCC_TSC_ETU_CLK] =3D &gcc_tsc_etu_clk.clkr, + [GCC_USB2_CLKREF_EN] =3D &gcc_usb2_clkref_en.clkr, + [GCC_USB30_PRIM_MASTER_CLK] =3D &gcc_usb30_prim_master_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK_SRC] =3D &gcc_usb30_prim_master_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK] =3D &gcc_usb30_prim_mock_utmi_clk.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =3D &gcc_usb30_prim_mock_utmi_clk_src.= clkr, + [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb30_prim_mock_utmi_= postdiv_clk_src.clkr, + [GCC_USB30_PRIM_SLEEP_CLK] =3D &gcc_usb30_prim_sleep_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK] =3D &gcc_usb3_prim_phy_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] =3D &gcc_usb3_prim_phy_aux_clk_src.clkr, + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] =3D &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] =3D &gcc_usb3_prim_phy_pipe_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] =3D &gcc_usb3_prim_phy_pipe_clk_src.clkr, + [GCC_ETH_100G_C2C_HM_APB_CLK] =3D &gcc_eth_100g_c2c_hm_apb_clk.clkr, + [GCC_ETH_100G_FH_HM_APB_0_CLK] =3D &gcc_eth_100g_fh_hm_apb_0_clk.clkr, + [GCC_ETH_100G_FH_HM_APB_1_CLK] =3D &gcc_eth_100g_fh_hm_apb_1_clk.clkr, + [GCC_ETH_100G_FH_HM_APB_2_CLK] =3D &gcc_eth_100g_fh_hm_apb_2_clk.clkr, + [GCC_ETH_DBG_C2C_HM_APB_CLK] =3D &gcc_eth_dbg_c2c_hm_apb_clk.clkr, + [GCC_AGGRE_NOC_ECPRI_GSI_CLK] =3D &gcc_aggre_noc_ecpri_gsi_clk.clkr, + [GCC_PCIE_0_PHY_AUX_CLK_SRC] =3D &gcc_pcie_0_phy_aux_clk_src.clkr, + [GCC_PCIE_0_PIPE_CLK_SRC] =3D &gcc_pcie_0_pipe_clk_src.clkr, +}; + +static const struct qcom_reset_map gcc_qdu1000_resets[] =3D { + [GCC_ECPRI_CC_BCR] =3D { 0x3e000 }, + [GCC_ECPRI_SS_BCR] =3D { 0x3a000 }, + [GCC_ETH_WRAPPER_BCR] =3D { 0x39000 }, + [GCC_PCIE_0_BCR] =3D { 0x9d000 }, + [GCC_PCIE_0_LINK_DOWN_BCR] =3D { 0x9e014 }, + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] =3D { 0x9e020 }, + [GCC_PCIE_0_PHY_BCR] =3D { 0x7c000 }, + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] =3D { 0x9e000 }, + [GCC_PCIE_PHY_CFG_AHB_BCR] =3D { 0x7f00c }, + [GCC_PCIE_PHY_COM_BCR] =3D { 0x7f010 }, + [GCC_PDM_BCR] =3D { 0x43000 }, + [GCC_QUPV3_WRAPPER_0_BCR] =3D { 0x27000 }, + [GCC_QUPV3_WRAPPER_1_BCR] =3D { 0x28000 }, + [GCC_QUSB2PHY_PRIM_BCR] =3D { 0x22000 }, + [GCC_QUSB2PHY_SEC_BCR] =3D { 0x22004 }, + [GCC_SDCC5_BCR] =3D { 0x3b000 }, + [GCC_TSC_BCR] =3D { 0x57000 }, + [GCC_USB30_PRIM_BCR] =3D { 0x49000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] =3D { 0x60008 }, + [GCC_USB3_DP_PHY_SEC_BCR] =3D { 0x60014 }, + [GCC_USB3_PHY_PRIM_BCR] =3D { 0x60000 }, + [GCC_USB3_PHY_SEC_BCR] =3D { 0x6000c }, + [GCC_USB3PHY_PHY_PRIM_BCR] =3D { 0x60004 }, + [GCC_USB3PHY_PHY_SEC_BCR] =3D { 0x60010 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] =3D { 0x7a000 }, +}; + +static const struct clk_rcg_dfs_data gcc_dfs_clocks[] =3D { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), +}; + +static const struct regmap_config gcc_qdu1000_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1f41f0, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc gcc_qdu1000_desc =3D { + .config =3D &gcc_qdu1000_regmap_config, + .clks =3D gcc_qdu1000_clocks, + .num_clks =3D ARRAY_SIZE(gcc_qdu1000_clocks), + .resets =3D gcc_qdu1000_resets, + .num_resets =3D ARRAY_SIZE(gcc_qdu1000_resets), +}; + +static const struct of_device_id gcc_qdu1000_match_table[] =3D { + { .compatible =3D "qcom,qdu1000-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_qdu1000_match_table); + +static int gcc_qdu1000_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap =3D qcom_cc_map(pdev, &gcc_qdu1000_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */ + regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14)); + + ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, + ARRAY_SIZE(gcc_dfs_clocks)); + if (ret) + return ret; + + ret =3D qcom_cc_really_probe(pdev, &gcc_qdu1000_desc, regmap); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n"); + + return ret; +} + +static struct platform_driver gcc_qdu1000_driver =3D { + .probe =3D gcc_qdu1000_probe, + .driver =3D { + .name =3D "gcc-qdu1000", + .of_match_table =3D gcc_qdu1000_match_table, + }, +}; + +static int __init gcc_qdu1000_init(void) +{ + return platform_driver_register(&gcc_qdu1000_driver); +} +subsys_initcall(gcc_qdu1000_init); + +static void __exit gcc_qdu1000_exit(void) +{ + platform_driver_unregister(&gcc_qdu1000_driver); +} +module_exit(gcc_qdu1000_exit); + +MODULE_DESCRIPTION("QTI GCC QDU1000 Driver"); +MODULE_LICENSE("GPL"); --=20 2.38.1