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Thu, 12 Jan 2023 16:45:08 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 12 Jan 2023 16:45:06 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 12 Jan 2023 16:45:05 +0800 From: Irui Wang To: Hans Verkuil , Rob Herring , Krzysztof Kozlowski , Mauro Carvalho Chehab , Matthias Brugger , , , kyrie wu CC: , , , , , , Tomasz Figa , , , Irui Wang Subject: [V1,1/2] arm64: dts: mt8195: add jpeg encode device node Date: Thu, 12 Jan 2023 16:45:02 +0800 Message-ID: <20230112084503.4277-2-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230112084503.4277-1-irui.wang@mediatek.com> References: <20230112084503.4277-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: kyrie wu add mt8195 jpegenc device node Signed-off-by: kyrie wu Signed-off-by: irui wang --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 40 ++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 5d31536f4c48..af49ec352bfe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2152,6 +2152,46 @@ #clock-cells =3D <1>; }; =20 + + jpgenc-master { + compatible =3D "mediatek,mt8195-jpgenc"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + iommus =3D <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; + dma-ranges =3D <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + jpgenc@1a030000 { + compatible =3D "mediatek,mt8195-jpgenc-hw"; + reg =3D <0 0x1a030000 0 0x10000>; + iommus =3D <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, + <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, + <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, + <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; + interrupts =3D ; + clocks =3D <&vencsys CLK_VENC_JPGENC>; + clock-names =3D "jpgenc"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VENC>; + }; + + jpgenc@1b030000 { + compatible =3D "mediatek,mt8195-jpgenc-hw"; + reg =3D <0 0x1b030000 0 0x10000>; + iommus =3D <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; + interrupts =3D ; + clocks =3D <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; + clock-names =3D "jpgenc"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + }; + }; + larb20: larb@1b010000 { compatible =3D "mediatek,mt8195-smi-larb"; reg =3D <0 0x1b010000 0 0x1000>; --=20 2.18.0