From nobody Mon Sep 15 16:12:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9FC0C678D6 for ; Wed, 11 Jan 2023 17:21:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235681AbjAKRVE (ORCPT ); Wed, 11 Jan 2023 12:21:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234544AbjAKRUu (ORCPT ); Wed, 11 Jan 2023 12:20:50 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB8E23057E; Wed, 11 Jan 2023 09:20:49 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 856EBB81C8A; Wed, 11 Jan 2023 17:20:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F28B5C433EF; Wed, 11 Jan 2023 17:20:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673457647; bh=KRbUD/DoZCTDQnpByHlFlnPMc8QCP2Jn97CVBSFQEdU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KA9Tw53YhdOGsvk3g+hlq8uCbsDTYI6F7Vkf1KEVye3JmHxcYO3VNbvGpSW/ZrGfI fX28RfMxvvX3tyEPeChS/dDgFTCRjYT/hrx5SrTxlmWmS3XKZy+xoH8rvYkMtxyvbs gjZY9M2awgxNvZE0iJy2zngMzz5Np0pWUEUW63DKEi7jORdf6jFLY7Ke74G+SqiPVR WBmwKgn3mj2+ONqvOKgvJqCrP6tt0psl+8Qpw1DPkmpXvRQ97wYiIXXeRfzEJddNvI YSHK8yZCGOKatTi7ly3InyB3Lv1bKa7jHyRe9YIyknwmQ7CFMABeU/jPKIuuVFqDXI xebX0eOKIQoBA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Heiko Stuebner Subject: [PATCH v3 01/13] riscv: fix jal offsets in patched alternatives Date: Thu, 12 Jan 2023 01:10:15 +0800 Message-Id: <20230111171027.2392-2-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111171027.2392-1-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Alternatives live in a different section, so offsets used by jal instruction will point to wrong locations after the patch got applied. Similar to arm64, adjust the location to consider that offset. Co-developed-by: Heiko Stuebner Signed-off-by: Heiko Stuebner Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/include/asm/insn.h | 27 +++++++++++++++++++++++++++ arch/riscv/kernel/alternative.c | 27 +++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index 98453535324a..1d2df245d0bd 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -291,6 +291,33 @@ static __always_inline bool riscv_insn_is_branch(u32 c= ode) (RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF)= | \ (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); }) =20 +/* + * Get the immediate from a J-type instruction. + * + * @insn: instruction to process + * Return: immediate + */ +static inline s32 riscv_insn_extract_jtype_imm(u32 insn) +{ + return RV_EXTRACT_JTYPE_IMM(insn); +} + +/* + * Update a J-type instruction with an immediate value. + * + * @insn: pointer to the jtype instruction + * @imm: the immediate to insert into the instruction + */ +static inline void riscv_insn_insert_jtype_imm(u32 *insn, s32 imm) +{ + /* drop the old IMMs, all jal IMM bits sit at 31:12 */ + *insn &=3D ~GENMASK(31, 12); + *insn |=3D (RV_X(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_= 10_1_OPOFF) | + (RV_X(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) | + (RV_X(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_O= POFF) | + (RV_X(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF); +} + /* * Put together one immediate from a U-type and I-type instruction pair. * diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternativ= e.c index 6212ea0eed72..3d4f1f32c7f6 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -79,6 +79,21 @@ static void riscv_alternative_fix_auipc_jalr(void *ptr, = u32 auipc_insn, patch_text_nosync(ptr, call, sizeof(u32) * 2); } =20 +static void riscv_alternative_fix_jal(void *ptr, u32 jal_insn, int patch_o= ffset) +{ + s32 imm; + + /* get and adjust new target address */ + imm =3D riscv_insn_extract_jtype_imm(jal_insn); + imm -=3D patch_offset; + + /* update instruction */ + riscv_insn_insert_jtype_imm(&jal_insn, imm); + + /* patch the call place again */ + patch_text_nosync(ptr, &jal_insn, sizeof(u32)); +} + void riscv_alternative_fix_offsets(void *alt_ptr, unsigned int len, int patch_offset) { @@ -106,6 +121,18 @@ void riscv_alternative_fix_offsets(void *alt_ptr, unsi= gned int len, riscv_alternative_fix_auipc_jalr(alt_ptr + i * sizeof(u32), insn, insn2, patch_offset); } + + if (riscv_insn_is_jal(insn)) { + s32 imm =3D riscv_insn_extract_jtype_imm(insn); + + /* Don't modify jumps inside the alternative block */ + if ((alt_ptr + i * sizeof(u32) + imm) >=3D alt_ptr && + (alt_ptr + i * sizeof(u32) + imm) < (alt_ptr + len)) + continue; + + riscv_alternative_fix_jal(alt_ptr + i * sizeof(u32), + insn, patch_offset); + } } } =20 --=20 2.38.1 From nobody Mon Sep 15 16:12:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE324C678D8 for ; Wed, 11 Jan 2023 17:21:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236627AbjAKRVI (ORCPT ); Wed, 11 Jan 2023 12:21:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234665AbjAKRUy (ORCPT ); Wed, 11 Jan 2023 12:20:54 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECE1C214; Wed, 11 Jan 2023 09:20:51 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 82D3A61D9E; Wed, 11 Jan 2023 17:20:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B06EEC433D2; Wed, 11 Jan 2023 17:20:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673457650; bh=srRoyMhEcGCbVrLyfi/YwhTea+Yq+TgoCP9PTzDvRWQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E8P7e3DgoRR0f4oVsM+IeXcbwq+Pqj2apye5Vlha8rab1w4XjqQnU9RjsHt9Il2HT 1l5sHlkLlVGjvYBulYoUKJwazR6wsDqPDSwbN8J9SLgy1UYo7pVch6Rm3IuBr2itiS d/7dfcPo1RDjT73MkOeGwINvd3XOHxbUZAZRQQPg/en1zdBbQefOoNjGD57CBsubS9 DGwO1N5+tWkIwRzUHgqJhTcy4Rma0Z7xjiwE7HjqDDIdVdd3K+cNwUU3xpLcqdHj6p 8fqp1VpToe81uoDdi2ZqRZQiL91Heaqoe0l1mEMnE9JBg2E2kuDUKytBfyvdm/fHbJ ZhisnXHbdLewA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Andrew Jones , Conor Dooley Subject: [PATCH v3 02/13] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Date: Thu, 12 Jan 2023 01:10:16 +0800 Message-Id: <20230111171027.2392-3-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111171027.2392-1-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It's a bit weird to call riscv_noncoherent_supported() each time when insmoding a module. Move the calling out of feature patch func. Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 1 - arch/riscv/kernel/setup.c | 3 +++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 205bbd6b1fce..421b3d9578cc 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -297,7 +297,6 @@ static bool __init_or_module cpufeature_probe_zicbom(un= signed int stage) if (!riscv_isa_extension_available(NULL, ZICBOM)) return false; =20 - riscv_noncoherent_supported(); return true; } =20 diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 86acd690d529..376d2827e736 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -300,6 +300,9 @@ void __init setup_arch(char **cmdline_p) riscv_init_cbom_blocksize(); riscv_fill_hwcap(); apply_boot_alternatives(); + if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && + riscv_isa_extension_available(NULL, ZICBOM)) + riscv_noncoherent_supported(); } =20 static int __init topology_init(void) --=20 2.38.1 From nobody Mon Sep 15 16:12:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08862C678D7 for ; Wed, 11 Jan 2023 17:21:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238417AbjAKRVL (ORCPT ); Wed, 11 Jan 2023 12:21:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234749AbjAKRU4 (ORCPT ); Wed, 11 Jan 2023 12:20:56 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8E4AE26; Wed, 11 Jan 2023 09:20:54 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 469BC61D9E; Wed, 11 Jan 2023 17:20:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 62672C433F1; Wed, 11 Jan 2023 17:20:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673457653; bh=XfFLNWhAd8k4qxV8rXLEBaM1QQgAKaJ6LOhZRHyHg+Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=muCp1adDcrT3TviFaKXdg0Pic8fXJRdvzrirnhFO1zFdeYWn/dET9sP7d1RdUdFAp DWxW08xXfBBtPd1rb+d48sLNkQQPnmss5DhciXz35D4n8UHO1DE1JhNEGLkAKHE6Ah taBSW9mbljzQvG+6oD+fvAHKEKilx/yD8HaAvHvgMPbQAEbjKvGzZEEIvHXTQUX+EE GJNrEsSIE5bWQtkY0U7nD1VanPzihUX3CuDncZoPfDPiG1gtMhGXnBxxQlPtONq+r1 5jLS2amJ5VeyhyBDjO5dH5DSMV6q4r8JBsdz9yhre14+cpSkEmEE43VsFskr8J5qEj wx7SU9f2rQEkg== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Andrew Jones Subject: [PATCH v3 03/13] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Date: Thu, 12 Jan 2023 01:10:17 +0800 Message-Id: <20230111171027.2392-4-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111171027.2392-1-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently riscv_cpufeature_patch_func() does nothing at the RISCV_ALTERNATIVES_EARLY_BOOT stage. Add a check to detect whether we are in this stage and exit early. This will allow us to use riscv_cpufeature_patch_func() for scanning of all ISA extensions. Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 421b3d9578cc..37e8c5e69754 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -328,6 +328,9 @@ void __init_or_module riscv_cpufeature_patch_func(struc= t alt_entry *begin, struct alt_entry *alt; u32 tmp; =20 + if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) + return; + for (alt =3D begin; alt < end; alt++) { if (alt->vendor_id !=3D 0) continue; --=20 2.38.1 From nobody Mon Sep 15 16:12:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC954C677F1 for ; Wed, 11 Jan 2023 17:21:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238513AbjAKRVX (ORCPT ); Wed, 11 Jan 2023 12:21:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235155AbjAKRU7 (ORCPT ); Wed, 11 Jan 2023 12:20:59 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5319636C; Wed, 11 Jan 2023 09:20:57 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5F8E161D9E; Wed, 11 Jan 2023 17:20:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 20CB5C433D2; Wed, 11 Jan 2023 17:20:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673457656; bh=dAysKavLBgtoJS8P4lvmpl+vDfyTE4+Ks8sj1E2vbYI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qOf6vUeScpKNvgQpXtmSRX8BqAsT4NdMIcRbdgsmCDpNXtYAkAs6PMN+71a6+xFL6 YMY99c2+oBl4B2RLUWT7XsPmj6lldWpTuHoB6uFU9AgtxgA8SfyxTQm3D/zI8c9i8v w9VVfYyka84foBQChriHCMRAJ09sci0CQbga1/XeNpxGKwRaJ+Oy9j5XWjCPNZ1cjc wfFYC0Pj6Z+4u/NZnNZ0gTGlnNgQtQl0dC3KY9eNDVFFuJdghhY3sWpxYGmMKAnZVf vMfXrpnEUGACa/dCOWjXSYTaKYMDVEOgjLuxiwkRTKroCmJJQtS/pMbqKlHimRxNJj YU1g2InMipajA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Andrew Jones Subject: [PATCH v3 04/13] riscv: hwcap: make ISA extension ids can be used in asm Date: Thu, 12 Jan 2023 01:10:18 +0800 Message-Id: <20230111171027.2392-5-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111171027.2392-1-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We will make use of ISA extension in asm files, so make the multi-letter RISC-V ISA extension IDs macros rather than enums and move them and those base ISA extension IDs to suitable place. Signed-off-by: Jisheng Zhang Reviewed-by: Heiko Stuebner Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 45 ++++++++++++++++------------------ 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 86328e3acb02..09a7767723f6 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -12,20 +12,6 @@ #include #include =20 -#ifndef __ASSEMBLY__ -#include -/* - * This yields a mask that user programs can use to figure out what - * instruction set this cpu supports. - */ -#define ELF_HWCAP (elf_hwcap) - -enum { - CAP_HWCAP =3D 1, -}; - -extern unsigned long elf_hwcap; - #define RISCV_ISA_EXT_a ('a' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') #define RISCV_ISA_EXT_d ('d' - 'a') @@ -46,22 +32,33 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_BASE 26 =20 /* - * This enum represent the logical ID for each multi-letter RISC-V ISA ext= ension. + * These macros represent the logical ID for each multi-letter RISC-V ISA = extension. * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter * extensions while all the multi-letter extensions should define the next * available logical extension id. */ -enum riscv_isa_ext_id { - RISCV_ISA_EXT_SSCOFPMF =3D RISCV_ISA_EXT_BASE, - RISCV_ISA_EXT_SVPBMT, - RISCV_ISA_EXT_ZICBOM, - RISCV_ISA_EXT_ZIHINTPAUSE, - RISCV_ISA_EXT_SSTC, - RISCV_ISA_EXT_SVINVAL, - RISCV_ISA_EXT_ID_MAX +#define RISCV_ISA_EXT_SSCOFPMF 26 +#define RISCV_ISA_EXT_SVPBMT 27 +#define RISCV_ISA_EXT_ZICBOM 28 +#define RISCV_ISA_EXT_ZIHINTPAUSE 29 +#define RISCV_ISA_EXT_SSTC 30 +#define RISCV_ISA_EXT_SVINVAL 31 + +#ifndef __ASSEMBLY__ +#include +/* + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ +#define ELF_HWCAP (elf_hwcap) + +enum { + CAP_HWCAP =3D 1, }; -static_assert(RISCV_ISA_EXT_ID_MAX <=3D RISCV_ISA_EXT_MAX); + +extern unsigned long elf_hwcap; + =20 /* * This enum represents the logical ID for each RISC-V ISA extension static --=20 2.38.1 From nobody Mon Sep 15 16:12:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0BCAC46467 for ; Wed, 11 Jan 2023 17:21:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238909AbjAKRV1 (ORCPT ); Wed, 11 Jan 2023 12:21:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235713AbjAKRVF (ORCPT ); Wed, 11 Jan 2023 12:21:05 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C79E63F2; Wed, 11 Jan 2023 09:21:03 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id A6BB8CE1C0C; Wed, 11 Jan 2023 17:21:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B130C433F2; Wed, 11 Jan 2023 17:20:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673457659; bh=vPXGohzIg9MzmCW43xmcC2ITGNCEVk5AktBiL5z/Ws8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nOoNNEcFEVhCee5gk+9LqtY5VRpz2i3GEeUIO+A9fh8H3RWKG6VA0wUNfg8T0uryj F3w+RVlgWl1BsnGl5pTi/fkXr8uu56kHKdu0sg/ELL42NqVWlq3G3Wt2NCyCzDjWGA NgBqbA+cGAlhyQWC51DWH53vq/36G/KlLTgMGWaxx6skfFeaS5khO2LgtfR61ZLY/o Ol+MEbbT2A9uKiqWD7HDYiQeR1gpKd052fkhASGmqENheAXYG0/3qg8TvY68u4H0Kq LAsXbxD6sLepDlwSUIf5glBwMJZ7VrCLwgg13YuQUAoHKTjlRVjY0ucKwhJqYVaI3b bN8WJ7iNVQCxw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Andrew Jones Subject: [PATCH v3 05/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Date: Thu, 12 Jan 2023 01:10:19 +0800 Message-Id: <20230111171027.2392-6-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111171027.2392-1-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" riscv_cpufeature_patch_func() currently only scans a limited set of cpufeatures, explicitly defined with macros. Extend it to probe for all ISA extensions. Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Heiko Stuebner --- arch/riscv/include/asm/errata_list.h | 9 ++-- arch/riscv/kernel/cpufeature.c | 63 ++++------------------------ 2 files changed, 11 insertions(+), 61 deletions(-) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 4180312d2a70..274c6f889602 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -7,6 +7,7 @@ =20 #include #include +#include #include =20 #ifdef CONFIG_ERRATA_SIFIVE @@ -22,10 +23,6 @@ #define ERRATA_THEAD_NUMBER 3 #endif =20 -#define CPUFEATURE_SVPBMT 0 -#define CPUFEATURE_ZICBOM 1 -#define CPUFEATURE_NUMBER 2 - #ifdef __ASSEMBLY__ =20 #define ALT_INSN_FAULT(x) \ @@ -55,7 +52,7 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VEN= DOR_ID, \ #define ALT_SVPBMT(_val, prot) \ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ "li %0, %1\t\nslli %0,%0,%3", 0, \ - CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ + RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ : "=3Dr"(_val) \ @@ -129,7 +126,7 @@ asm volatile(ALTERNATIVE_2( \ "add a0, a0, %0\n\t" \ "2:\n\t" \ "bltu a0, %2, 3b\n\t" \ - "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ + "nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ "mv a0, %1\n\t" \ "j 2f\n\t" \ "3:\n\t" \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 37e8c5e69754..6db8b31d9149 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -275,58 +275,11 @@ void __init riscv_fill_hwcap(void) } =20 #ifdef CONFIG_RISCV_ALTERNATIVE -static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage) -{ - if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT)) - return false; - - if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) - return false; - - return riscv_isa_extension_available(NULL, SVPBMT); -} - -static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) -{ - if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM)) - return false; - - if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) - return false; - - if (!riscv_isa_extension_available(NULL, ZICBOM)) - return false; - - return true; -} - -/* - * Probe presence of individual extensions. - * - * This code may also be executed before kernel relocation, so we cannot u= se - * addresses generated by the address-of operator as they won't be valid in - * this context. - */ -static u32 __init_or_module cpufeature_probe(unsigned int stage) -{ - u32 cpu_req_feature =3D 0; - - if (cpufeature_probe_svpbmt(stage)) - cpu_req_feature |=3D BIT(CPUFEATURE_SVPBMT); - - if (cpufeature_probe_zicbom(stage)) - cpu_req_feature |=3D BIT(CPUFEATURE_ZICBOM); - - return cpu_req_feature; -} - void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned int stage) { - u32 cpu_req_feature =3D cpufeature_probe(stage); struct alt_entry *alt; - u32 tmp; =20 if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) return; @@ -334,18 +287,18 @@ void __init_or_module riscv_cpufeature_patch_func(str= uct alt_entry *begin, for (alt =3D begin; alt < end; alt++) { if (alt->vendor_id !=3D 0) continue; - if (alt->errata_id >=3D CPUFEATURE_NUMBER) { - WARN(1, "This feature id:%d is not in kernel cpufeature list", + if (alt->errata_id >=3D RISCV_ISA_EXT_MAX) { + WARN(1, "This extension id:%d is not in ISA extension list", alt->errata_id); continue; } =20 - tmp =3D (1U << alt->errata_id); - if (cpu_req_feature & tmp) { - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); - riscv_alternative_fix_offsets(alt->old_ptr, alt->alt_len, - alt->old_ptr - alt->alt_ptr); - } + if (!__riscv_isa_extension_available(NULL, alt->errata_id)) + continue; + + patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); + riscv_alternative_fix_offsets(alt->old_ptr, alt->alt_len, + alt->old_ptr - alt->alt_ptr); } } #endif --=20 2.38.1 From nobody Mon Sep 15 16:12:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93413C5479D for ; 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d=kernel.org; s=k20201202; t=1673457663; bh=mINO93PYoIl2Le02IWiuk8J2800U31qq9j/6NT8h4Nc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j8O0/kRMnkMh6I08+s4abnchp7uRi0Y69jnQCXoxMYVSjkHdoUObVkpuPS/Z7FlJo N+cevInTRe40SvOKdCAWROfrbl7JT4HHuaMZI3kHcF1gnr8UTAi5Gx2i0RRmXvKyWp iY65QJ4r30iOqO9EQbCBX0Ukaljf+s22gwj/O59SJcReuTyzkhpDBSeOeLc5ICa+Oi vjn27YoSkrZpu8XZWnWA2pmmwPxP4zSrjt3FvnIyCPuaGHA07jW9pF6iLAFBN8xVx3 TDQwRCSfekPthJawpjziENNYx3+6fkIrq9e5PzrTz/xSlS1zdpcuyz8Muflrrt6+fW iqnfyjvrjMFIQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Andrew Jones Subject: [PATCH v3 06/13] riscv: introduce riscv_has_extension_[un]likely() Date: Thu, 12 Jan 2023 01:10:20 +0800 Message-Id: <20230111171027.2392-7-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111171027.2392-1-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Generally, riscv ISA extensions are fixed for any specific hardware platform, so a hart's features won't change after booting. This chacteristic makes it straightforward to use a static branch to check if a specific ISA extension is supported or not to optimize performance. However, some ISA extensions such as SVPBMT and ZICBOM are handled via. the alternative sequences. Basically, for ease of maintenance, we prefer to use static branches in C code, but recently, Samuel found that the static branch usage in cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As Samuel pointed out, "Having a static branch in cpu_relax() is problematic because that function is widely inlined, including in some quite complex functions like in the VDSO. A quick measurement shows this static branch is responsible by itself for around 40% of the jump table." Samuel's findings pointed out one of a few downsides of static branches usage in C code to handle ISA extensions detected at boot time: static branch's metadata in the __jump_table section, which is not discarded after ISA extensions are finalized, wastes some space. I want to try to solve the issue for all possible dynamic handling of ISA extensions at boot time. Inspired by Mark[2], this patch introduces riscv_has_extension_*() helpers, which work like static branches but are patched using alternatives, thus the metadata can be freed after patching. Link: https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sho= lland.org/ [1] Link: https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mar= k.rutland@arm.com/ [2] Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones --- arch/riscv/include/asm/hwcap.h | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 09a7767723f6..1767a9ce1a04 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -8,6 +8,7 @@ #ifndef _ASM_RISCV_HWCAP_H #define _ASM_RISCV_HWCAP_H =20 +#include #include #include #include @@ -97,6 +98,42 @@ static __always_inline int riscv_isa_ext2key(int num) } } =20 +static __always_inline bool +riscv_has_extension_likely(const unsigned long ext) +{ + compiletime_assert(ext < RISCV_ISA_EXT_MAX, + "ext must be < RISCV_ISA_EXT_MAX"); + + asm_volatile_goto( + ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1) + : + : [ext] "i" (ext) + : + : l_no); + + return true; +l_no: + return false; +} + +static __always_inline bool +riscv_has_extension_unlikely(const unsigned long ext) +{ + compiletime_assert(ext < RISCV_ISA_EXT_MAX, + "ext must be < RISCV_ISA_EXT_MAX"); + + asm_volatile_goto( + ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1) + : + : [ext] "i" (ext) + : + : l_yes); + + return false; +l_yes: + return true; +} + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) --=20 2.38.1 From nobody Mon Sep 15 16:12:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93D89C678D5 for ; Wed, 11 Jan 2023 17:21:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239322AbjAKRVi (ORCPT ); Wed, 11 Jan 2023 12:21:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238284AbjAKRVK (ORCPT ); Wed, 11 Jan 2023 12:21:10 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D47D3164B7; Wed, 11 Jan 2023 09:21:09 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 85B1AB81B79; Wed, 11 Jan 2023 17:21:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C764EC433F1; Wed, 11 Jan 2023 17:21:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673457667; bh=ZZbNK1MSY8P4rukKkUHVGmvzf9kfXc1zq+8A+JZHFy4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=u1gsJ0ZpyP7xSdrHXOtzajlWsoeDRdoq0kC7WCc/j084lmL33+LWIDjc8kZ+DBFAv 7V7nETI9PWsBz6XDcxxpXogkfBxx4BXKXdSuUV8R2mGo5RzRfucP5qxNl5xl5SKDbU AfKARehtE7S77bev8DMfOL5Q367VEFp2vXobvBxiRTVyM+5fvgExVytYF6gVj99vFM wIVEcf2E7iGhjtxCfzW7Hbqvi1Aw8dKOHgz8o9H1N5X9IU+xpz2M89sxgPfAI4oCHv ny6h3H9ejIT1bKEDqADSEYemvJkq/HGJuVSUfTZzyPcFnfQ9U/wxXA3OYLUiv29dRM GfCO2qYI7uyVw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Andrew Jones Subject: [PATCH v3 07/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Date: Thu, 12 Jan 2023 01:10:21 +0800 Message-Id: <20230111171027.2392-8-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111171027.2392-1-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Switch has_fpu() from statich branch to the new helper riscv_has_extension_likely(). Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley --- arch/riscv/include/asm/switch_to.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 11463489fec6..60f8ca01d36e 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -59,7 +59,8 @@ static inline void __switch_to_aux(struct task_struct *pr= ev, =20 static __always_inline bool has_fpu(void) { - return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]); + return riscv_has_extension_likely(RISCV_ISA_EXT_f) || + riscv_has_extension_likely(RISCV_ISA_EXT_d); } #else static __always_inline bool has_fpu(void) { return false; } --=20 2.38.1 From nobody Mon Sep 15 16:12:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0E5BC678D7 for ; Wed, 11 Jan 2023 17:21:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239488AbjAKRVo (ORCPT ); Wed, 11 Jan 2023 12:21:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234749AbjAKRVO (ORCPT ); Wed, 11 Jan 2023 12:21:14 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3306B164B7; Wed, 11 Jan 2023 09:21:13 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C9B88B81C8B; Wed, 11 Jan 2023 17:21:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A29E1C433D2; Wed, 11 Jan 2023 17:21:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673457670; bh=W6NwJoOq7fauyX3aaR9QaMpoEnd1BqGf85SXKRegHDA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D75d/A9S64ANT2vjpZ+W99c0WJYeqx+r15lfor+IxsMitzgTgU10xNLFTWpmbRDLN 6jW2Zr/fM9GV0/5QYkLSMvxupgVx2erpfOTVicmDa1psTbljVBz6d1ZubDKPL2L3Rp 1YkkbIU+r1h7nk+TRby5FwlbSvTAM53aQfl4c5+TMePgndziOABuxLgyWxYe6p0NDs l6Qg4Ec0UoJyjAcMDJQwV4IwhBUzd2EKU6AO7tthfq0ke9ieI9+UJdAHz7SK6dXpkq SuYQEe190aAoWRm+S9Uc1ehFjUUZBp94uClqma9e3x5GghUChM9yD2tR/xHMoXT6rF +zcLfe4WuD1kw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Conor Dooley , Andrew Jones Subject: [PATCH v3 08/13] riscv: module: move find_section to module.h Date: Thu, 12 Jan 2023 01:10:22 +0800 Message-Id: <20230111171027.2392-9-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111171027.2392-1-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move find_section() to module.h so that the implementation can be shared by the alternatives code. This will allow us to use alternatives in the vdso. Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/module.h | 16 ++++++++++++++++ arch/riscv/kernel/module.c | 15 --------------- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/arch/riscv/include/asm/module.h b/arch/riscv/include/asm/modul= e.h index 76aa96a9fc08..0f3baaa6a9a8 100644 --- a/arch/riscv/include/asm/module.h +++ b/arch/riscv/include/asm/module.h @@ -5,6 +5,7 @@ #define _ASM_RISCV_MODULE_H =20 #include +#include =20 struct module; unsigned long module_emit_got_entry(struct module *mod, unsigned long val); @@ -111,4 +112,19 @@ static inline struct plt_entry *get_plt_entry(unsigned= long val, =20 #endif /* CONFIG_MODULE_SECTIONS */ =20 +static inline const Elf_Shdr *find_section(const Elf_Ehdr *hdr, + const Elf_Shdr *sechdrs, + const char *name) +{ + const Elf_Shdr *s, *se; + const char *secstrs =3D (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; + + for (s =3D sechdrs, se =3D sechdrs + hdr->e_shnum; s < se; s++) { + if (strcmp(name, secstrs + s->sh_name) =3D=3D 0) + return s; + } + + return NULL; +} + #endif /* _ASM_RISCV_MODULE_H */ diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 91fe16bfaa07..76f4b9c2ec5b 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -429,21 +429,6 @@ void *module_alloc(unsigned long size) } #endif =20 -static const Elf_Shdr *find_section(const Elf_Ehdr *hdr, - const Elf_Shdr *sechdrs, - const char *name) -{ - const Elf_Shdr *s, *se; - const char *secstrs =3D (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; - - for (s =3D sechdrs, se =3D sechdrs + hdr->e_shnum; s < se; s++) { - if (strcmp(name, secstrs + s->sh_name) =3D=3D 0) - return s; - } - - return NULL; -} - int module_finalize(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs, struct module *me) --=20 2.38.1 From nobody Mon Sep 15 16:12:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E62A4C678D6 for ; Wed, 11 Jan 2023 17:21:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239517AbjAKRVs (ORCPT ); Wed, 11 Jan 2023 12:21:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238445AbjAKRVP (ORCPT ); Wed, 11 Jan 2023 12:21:15 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EACD164B7; Wed, 11 Jan 2023 09:21:14 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E387761D7C; Wed, 11 Jan 2023 17:21:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DFAA1C433F2; Wed, 11 Jan 2023 17:21:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673457673; bh=QXCl9/YRGYDijYF1P0JxIQVW7KGO4TZ6w3gbD/nga80=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AYo4JFB4doghBAFFM+7KRWpmdPSTOW7aijVSBCtkqv4opIq/EBx92+5Q64DqjqDOx Tu9T+ts4HBkqEd9Tyj4+VnEoMes4Bz4iTX5uAlyS7w+eLfrTuTDtrCuzBOSI2CMqt9 nAaVGFLaVjjjL9h7Dw/bDFPsNMM9nBGsK8TOatmcd9oDTYkbehG3CwdCzCbwMhGwp7 kIHQWSddJUAKpddWPJhGNxnFiZ1oA//vOiBdKHTRnvyqE/n9XvVb931ePpuYGNhlGu BadmOPhJpe2dImcTdAYgO9MJC3q5mD3Vau3zYMe45HK/Z7yHjgmcpXNGpjCpieVzGL NO9uQETcM0lPQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v3 09/13] riscv: switch to relative alternative entries Date: Thu, 12 Jan 2023 01:10:23 +0800 Message-Id: <20230111171027.2392-10-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111171027.2392-1-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of using absolute addresses for both the old instrucions and the alternative instructions, use offsets relative to the alt_entry values. So this not only cuts the size of the alternative entry, but also meets the prerequisite for patching alternatives in the vDSO, since absolute alternative entries are subject to dynamic relocation, which is incompatible with the vDSO building. Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones --- arch/riscv/errata/sifive/errata.c | 4 +++- arch/riscv/errata/thead/errata.c | 11 ++++++++--- arch/riscv/include/asm/alternative-macros.h | 20 ++++++++++---------- arch/riscv/include/asm/alternative.h | 12 ++++++------ arch/riscv/kernel/cpufeature.c | 8 +++++--- 5 files changed, 32 insertions(+), 23 deletions(-) diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/e= rrata.c index 1031038423e7..0e537cdfd324 100644 --- a/arch/riscv/errata/sifive/errata.c +++ b/arch/riscv/errata/sifive/errata.c @@ -107,7 +107,9 @@ void __init_or_module sifive_errata_patch_func(struct a= lt_entry *begin, =20 tmp =3D (1U << alt->errata_id); if (cpu_req_errata & tmp) { - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); + patch_text_nosync((void *)&alt->old_offset + alt->old_offset, + (void *)&alt->alt_offset + alt->alt_offset, + alt->alt_len); cpu_apply_errata |=3D tmp; } } diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index fac5742d1c1e..d56d76a529b5 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -87,6 +87,7 @@ void __init_or_module thead_errata_patch_func(struct alt_= entry *begin, struct al struct alt_entry *alt; u32 cpu_req_errata =3D thead_errata_probe(stage, archid, impid); u32 tmp; + void *oldptr, *altptr; =20 for (alt =3D begin; alt < end; alt++) { if (alt->vendor_id !=3D THEAD_VENDOR_ID) @@ -96,12 +97,16 @@ void __init_or_module thead_errata_patch_func(struct al= t_entry *begin, struct al =20 tmp =3D (1U << alt->errata_id); if (cpu_req_errata & tmp) { + oldptr =3D (void *)&alt->old_offset + alt->old_offset; + altptr =3D (void *)&alt->alt_offset + alt->alt_offset; + /* On vm-alternatives, the mmu isn't running yet */ if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) - memcpy((void *)__pa_symbol(alt->old_ptr), - (void *)__pa_symbol(alt->alt_ptr), alt->alt_len); + memcpy((void *)__pa_symbol(oldptr), + (void *)__pa_symbol(altptr), + alt->alt_len); else - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); + patch_text_nosync(oldptr, altptr, alt->alt_len); } } =20 diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/inclu= de/asm/alternative-macros.h index 7226e2462584..3c3ca65e521b 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -7,11 +7,11 @@ #ifdef __ASSEMBLY__ =20 .macro ALT_ENTRY oldptr newptr vendor_id errata_id new_len - RISCV_PTR \oldptr - RISCV_PTR \newptr - REG_ASM \vendor_id - REG_ASM \new_len - .word \errata_id + .long \oldptr - . + .long \newptr - . + .short \vendor_id + .short \new_len + .long \errata_id .endm =20 .macro ALT_NEW_CONTENT vendor_id, errata_id, enable =3D 1, new_c : vararg @@ -59,11 +59,11 @@ #include =20 #define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \ - RISCV_PTR " " oldptr "\n" \ - RISCV_PTR " " newptr "\n" \ - REG_ASM " " vendor_id "\n" \ - REG_ASM " " newlen "\n" \ - ".word " errata_id "\n" + ".long ((" oldptr ") - .) \n" \ + ".long ((" newptr ") - .) \n" \ + ".short " vendor_id "\n" \ + ".short " newlen "\n" \ + ".long " errata_id "\n" =20 #define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \ ".if " __stringify(enable) " =3D=3D 1\n" \ diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/= alternative.h index 1bd4027d34ca..b6050a235f50 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -31,12 +31,12 @@ void riscv_alternative_fix_offsets(void *alt_ptr, unsig= ned int len, int patch_offset); =20 struct alt_entry { - void *old_ptr; /* address of original instruciton or data */ - void *alt_ptr; /* address of replacement instruction or data */ - unsigned long vendor_id; /* cpu vendor id */ - unsigned long alt_len; /* The replacement size */ - unsigned int errata_id; /* The errata id */ -} __packed; + s32 old_offset; /* offset relative to original instruciton or data */ + s32 alt_offset; /* offset relative to replacement instruction or data */ + u16 vendor_id; /* cpu vendor id */ + u16 alt_len; /* The replacement size */ + u32 errata_id; /* The errata id */ +}; =20 struct errata_checkfunc_id { unsigned long vendor_id; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 6db8b31d9149..c394cde2560b 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -280,6 +280,7 @@ void __init_or_module riscv_cpufeature_patch_func(struc= t alt_entry *begin, unsigned int stage) { struct alt_entry *alt; + void *oldptr, *altptr; =20 if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) return; @@ -293,12 +294,13 @@ void __init_or_module riscv_cpufeature_patch_func(str= uct alt_entry *begin, continue; } =20 + oldptr =3D (void *)&alt->old_offset + alt->old_offset; + altptr =3D (void *)&alt->alt_offset + alt->alt_offset; if (!__riscv_isa_extension_available(NULL, alt->errata_id)) continue; =20 - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); - riscv_alternative_fix_offsets(alt->old_ptr, alt->alt_len, - alt->old_ptr - alt->alt_ptr); + patch_text_nosync(oldptr, altptr, alt->alt_len); + riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr); } } #endif --=20 2.38.1 From nobody Mon Sep 15 16:12:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFF46C54EBC for ; Wed, 11 Jan 2023 17:21:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238685AbjAKRVx (ORCPT ); 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b=MA/U+XhExNf+fuYB7IqjgrugfJkHiRS6aw7i1XlatIvpnKCSUmj6NEGFRa4rsthPS jibd7VDhON/0KD0gFuDXjtZan8MrILnJmpnAMuTh/rSWgJ2AcKE2tI5sdgCc8moT4f v+3yvhyOXIMQR4tICFtxQGH9Np12dsL6SmUJWfMuMNMaaO5MMLP5udx1IxRU9ThKBf kCmQZl6al1ZA/R2wcVbu3pn/iTeARnAWCG5fwRdKcTnf+ZYfroqVygo63+ZuDF6vdK NWtOvwlG31jA98tq69Wcz8B1VGGA5UZ4PvA1m90xxAt+F6KG312mh/yMMoWvJRlYfR Nt6rC9358gCXA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Guo Ren , Andrew Jones Subject: [PATCH v3 10/13] riscv: alternative: patch alternatives in the vDSO Date: Thu, 12 Jan 2023 01:10:24 +0800 Message-Id: <20230111171027.2392-11-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111171027.2392-1-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make it possible to use alternatives in the vDSO, so that better implementations can be used if possible. Signed-off-by: Jisheng Zhang Reviewed-by: Guo Ren Reviewed-by: Andrew Jones --- arch/riscv/include/asm/vdso.h | 4 ++++ arch/riscv/kernel/alternative.c | 25 +++++++++++++++++++++++++ arch/riscv/kernel/vdso.c | 5 ----- arch/riscv/kernel/vdso/vdso.lds.S | 7 +++++++ 4 files changed, 36 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/vdso.h b/arch/riscv/include/asm/vdso.h index a7644f46d0e5..f891478829a5 100644 --- a/arch/riscv/include/asm/vdso.h +++ b/arch/riscv/include/asm/vdso.h @@ -28,8 +28,12 @@ #define COMPAT_VDSO_SYMBOL(base, name) \ (void __user *)((unsigned long)(base) + compat__vdso_##name##_offset) =20 +extern char compat_vdso_start[], compat_vdso_end[]; + #endif /* CONFIG_COMPAT */ =20 +extern char vdso_start[], vdso_end[]; + #endif /* !__ASSEMBLY__ */ =20 #endif /* CONFIG_MMU */ diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternativ= e.c index 3d4f1f32c7f6..a883a309139f 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -11,7 +11,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -160,6 +162,27 @@ static void __init_or_module _apply_alternatives(struc= t alt_entry *begin, stage); } =20 +static void __init apply_vdso_alternatives(void) +{ + const struct elf64_hdr *hdr; + const struct elf64_shdr *shdr; + const struct elf64_shdr *alt; + struct alt_entry *begin, *end; + + hdr =3D (struct elf64_hdr *)vdso_start; + shdr =3D (void *)hdr + hdr->e_shoff; + alt =3D find_section(hdr, shdr, ".alternative"); + if (!alt) + return; + + begin =3D (void *)hdr + alt->sh_offset, + end =3D (void *)hdr + alt->sh_offset + alt->sh_size, + + _apply_alternatives((struct alt_entry *)begin, + (struct alt_entry *)end, + RISCV_ALTERNATIVES_BOOT); +} + void __init apply_boot_alternatives(void) { /* If called on non-boot cpu things could go wrong */ @@ -168,6 +191,8 @@ void __init apply_boot_alternatives(void) _apply_alternatives((struct alt_entry *)__alt_start, (struct alt_entry *)__alt_end, RISCV_ALTERNATIVES_BOOT); + + apply_vdso_alternatives(); } =20 /* diff --git a/arch/riscv/kernel/vdso.c b/arch/riscv/kernel/vdso.c index e410275918ac..4e631c098f4d 100644 --- a/arch/riscv/kernel/vdso.c +++ b/arch/riscv/kernel/vdso.c @@ -22,11 +22,6 @@ struct vdso_data { }; #endif =20 -extern char vdso_start[], vdso_end[]; -#ifdef CONFIG_COMPAT -extern char compat_vdso_start[], compat_vdso_end[]; -#endif - enum vvar_pages { VVAR_DATA_PAGE_OFFSET, VVAR_TIMENS_PAGE_OFFSET, diff --git a/arch/riscv/kernel/vdso/vdso.lds.S b/arch/riscv/kernel/vdso/vds= o.lds.S index 150b1a572e61..4a0606633290 100644 --- a/arch/riscv/kernel/vdso/vdso.lds.S +++ b/arch/riscv/kernel/vdso/vdso.lds.S @@ -40,6 +40,13 @@ SECTIONS . =3D 0x800; .text : { *(.text .text.*) } :text =20 + . =3D ALIGN(4); + .alternative : { + __alt_start =3D .; + *(.alternative) + __alt_end =3D .; + } + .data : { *(.got.plt) *(.got) *(.data .data.* .gnu.linkonce.d.*) --=20 2.38.1 From nobody Mon Sep 15 16:12:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF47BC46467 for ; Wed, 11 Jan 2023 17:22:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239024AbjAKRV6 (ORCPT ); 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b=KKs/0/VFSvU2SnllZ+uG+nxnYXbVkIe8lRcr3KSHKo6td8KIyNPrEPYX+QoGpC/0v IEbh7jBwyWqO20/l1BHxElXPwMPMBVvoezH1TdXTGQoiHcIwGQpsHFy0v3rlQqddgY By77PW+uxHCcFntfWDM/+0mG7/riTiw+S30o/6l2ZOJUBQO0YoFdFC9aEcmFfeRvmM bJTABO8ubZBVg0mlVot9/EPqeoJcuk/QIINFGIiQ/ueeC+sMXAXsIOSDWnLhZ/2L5J irN93MKeyPBSmq6NGqqcrtZ2sLqS2WNNOmDUEKlKjfKfsxSz/V8vsHWLrURyC51ALz y0y3ESvmyldoA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Andrew Jones , Guo Ren Subject: [PATCH v3 11/13] riscv: cpu_relax: switch to riscv_has_extension_likely() Date: Thu, 12 Jan 2023 01:10:25 +0800 Message-Id: <20230111171027.2392-12-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111171027.2392-1-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Switch cpu_relax() from static branch to the new helper riscv_has_extension_likely() Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Heiko Stuebner Reviewed-by: Guo Ren Reviewed-by: Conor Dooley --- arch/riscv/include/asm/vdso/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/a= sm/vdso/processor.h index fa70cfe507aa..edf0e25e43d1 100644 --- a/arch/riscv/include/asm/vdso/processor.h +++ b/arch/riscv/include/asm/vdso/processor.h @@ -10,7 +10,7 @@ =20 static inline void cpu_relax(void) { - if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAU= SE])) { + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZIHINTPAUSE)) { #ifdef __riscv_muldiv int dummy; /* In lieu of a halt instruction, induce a long-latency stall. */ --=20 2.38.1 From nobody Mon Sep 15 16:12:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D164C46467 for ; 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s=k20201202; t=1673457682; bh=iakCU13SXpMb3pcvjfiiLXGeB5RnCPEYfg/spzK7YxA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QyqAUwJGdNtBpzR4nntbs1iPUTkBKiOHAmXK9MifYRWMELikATG4WriMLqpDgxpov cHYLSZFLH9EHn+oPMBvxgIhq8JwB69mMxlGzCWFVKKq5oUvR6NH/KoHX0MPpkBDaQu j4Z0J//elt3BJwT1UORJJ0DODp8Jh2NMZOlPbOeTRciGJfooU/7fF3FQLKz3+7BxtO YHcf4fCfc5HvTlUc8IQlW1PW5Nemzwft1lPPwWrdHYdLhltZif8x69g+9WgKM0ezE+ kjAConnZz54KiT8BYnQ/k4YcSufpdk1aw3s3x0HWqArA+muds8k8lw81cVsfeS4DLU XT5HZ9ozU1fdg== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Andrew Jones , Guo Ren Subject: [PATCH v3 12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() Date: Thu, 12 Jan 2023 01:10:26 +0800 Message-Id: <20230111171027.2392-13-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111171027.2392-1-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Andrew Jones Switch has_svinval() from static branch to the new helper riscv_has_extension_unlikely(). Signed-off-by: Andrew Jones Reviewed-by: Guo Ren --- arch/riscv/kvm/tlb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c index 309d79b3e5cd..aa3da18ad873 100644 --- a/arch/riscv/kvm/tlb.c +++ b/arch/riscv/kvm/tlb.c @@ -15,8 +15,7 @@ #include #include =20 -#define has_svinval() \ - static_branch_unlikely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_SVINVAL]) +#define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) =20 void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, gpa_t gpa, gpa_t gpsz, --=20 2.38.1 From nobody Mon Sep 15 16:12:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADAA7C46467 for ; Wed, 11 Jan 2023 17:22:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239569AbjAKRWc (ORCPT ); Wed, 11 Jan 2023 12:22:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239340AbjAKRVj (ORCPT ); Wed, 11 Jan 2023 12:21:39 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D8CA33D56; Wed, 11 Jan 2023 09:21:28 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id EAAEEB81C8B; Wed, 11 Jan 2023 17:21:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F416BC433EF; Wed, 11 Jan 2023 17:21:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673457685; bh=nQ/FgwW4vCV/82AO+CiVvxSVywwFvyd81VlYJvv3+mQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cu4MF1WU8L/w1VT9eJ9YbvvwI+Npsyq9vX5U3+o8YY37j9vHLXpaHY46RsetWAQ1r D/IgBo5kWDJ005wyMDlWxFogQB8ActEQXei0EwPYWaYHnJhGAPBzp7aI/I4g9ShW2i xCwZxvgoa2K+B81APqxdPMaa5SLNwyUhMob6jjYE6yngCXRtB3vAwYWDjBk5IymH9h gRIIrk9sAMms/3pyqsV5FE8iLFMPIRdaG2cVyAkTrgLg9M0VfDjgKL40FQUj4NlmAy 4u7lk9K6qWkPCCcaDQnrsbRvADI8G4uMZ1FyEVA2MJM6+3nFJLbKRjEG2kXGG1lNfY 8K5N+x+lDHHGQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Andrew Jones , Conor Dooley , Guo Ren Subject: [PATCH v3 13/13] riscv: remove riscv_isa_ext_keys[] array and related usage Date: Thu, 12 Jan 2023 01:10:27 +0800 Message-Id: <20230111171027.2392-14-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111171027.2392-1-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All users have switched to riscv_has_extension_*, remove unused definitions, vars and related setting code. Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley Reviewed-by: Guo Ren --- arch/riscv/include/asm/hwcap.h | 31 ------------------------------- arch/riscv/kernel/cpufeature.c | 9 --------- 2 files changed, 40 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 1767a9ce1a04..e3749bee5c24 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -60,19 +60,6 @@ enum { =20 extern unsigned long elf_hwcap; =20 - -/* - * This enum represents the logical ID for each RISC-V ISA extension static - * keys. We can use static key to optimize code path if some ISA extensions - * are available. - */ -enum riscv_isa_ext_key { - RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */ - RISCV_ISA_EXT_KEY_ZIHINTPAUSE, - RISCV_ISA_EXT_KEY_SVINVAL, - RISCV_ISA_EXT_KEY_MAX, -}; - struct riscv_isa_ext_data { /* Name of the extension displayed to userspace via /proc/cpuinfo */ char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; @@ -80,24 +67,6 @@ struct riscv_isa_ext_data { unsigned int isa_ext_id; }; =20 -extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX]; - -static __always_inline int riscv_isa_ext2key(int num) -{ - switch (num) { - case RISCV_ISA_EXT_f: - return RISCV_ISA_EXT_KEY_FPU; - case RISCV_ISA_EXT_d: - return RISCV_ISA_EXT_KEY_FPU; - case RISCV_ISA_EXT_ZIHINTPAUSE: - return RISCV_ISA_EXT_KEY_ZIHINTPAUSE; - case RISCV_ISA_EXT_SVINVAL: - return RISCV_ISA_EXT_KEY_SVINVAL; - default: - return -EINVAL; - } -} - static __always_inline bool riscv_has_extension_likely(const unsigned long ext) { diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c394cde2560b..5591d45e96b5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -29,9 +29,6 @@ unsigned long elf_hwcap __read_mostly; /* Host ISA bitmap */ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; =20 -DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX); -EXPORT_SYMBOL(riscv_isa_ext_keys); - /** * riscv_isa_extension_base() - Get base extension word * @@ -266,12 +263,6 @@ void __init riscv_fill_hwcap(void) if (elf_hwcap & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str); - - for_each_set_bit(i, riscv_isa, RISCV_ISA_EXT_MAX) { - j =3D riscv_isa_ext2key(i); - if (j >=3D 0) - static_branch_enable(&riscv_isa_ext_keys[j]); - } } =20 #ifdef CONFIG_RISCV_ALTERNATIVE --=20 2.38.1