From nobody Sat Sep 21 07:47:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36615C678D7 for ; Wed, 11 Jan 2023 03:30:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235588AbjAKD34 (ORCPT ); Tue, 10 Jan 2023 22:29:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235319AbjAKD3B (ORCPT ); Tue, 10 Jan 2023 22:29:01 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1643C13D66; Tue, 10 Jan 2023 19:28:45 -0800 (PST) X-UUID: 0a13390a916011ed945fc101203acc17-20230111 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mbHqNJkSdR1rCR9KdCc2/hI6jI6Bavtsh5EvXljRiSY=; b=lHZ3DVWS3hE20MhW1YGcmm/ytMX868/3s22x1dnm1B4QEPct9uq8DepnLMn5axqgxKSxz1Q4PHnvBCD1X2tDVl5UPBy2zoOVncjpwX3MDgONrFhv9DZmH7I/KeYYDVbnDpH6XoguTIFdFKc6SXFJ2U/UMboKU5Tcl1qHbGQOt3U=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.17,REQID:085a724d-07fa-4f0f-a3c1-a9f3f2669bd0,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Release_Ham,ACT ION:release,TS:75 X-CID-INFO: VERSION:1.1.17,REQID:085a724d-07fa-4f0f-a3c1-a9f3f2669bd0,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACT ION:quarantine,TS:75 X-CID-META: VersionHash:543e81c,CLOUDID:fff475f5-ff42-4fb0-b929-626456a83c14,B ulkID:230111112645T5NW3R1R,BulkQuantity:6,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:40,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0 X-CID-APTURL: Status:success,Category:nil,Trust:0,Unknown:0,Malicious:0 X-CID-BVR: 0 X-UUID: 0a13390a916011ed945fc101203acc17-20230111 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 871350046; Wed, 11 Jan 2023 11:28:39 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 11 Jan 2023 11:28:37 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 11 Jan 2023 11:28:36 +0800 From: Jian Yang To: Lorenzo Pieralisi , Jianjun Wang , Rob Herring , Bjorn Helgaas , Matthias Brugger , Ryder Lee , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= CC: , , , , , , , , , , , Subject: [PATCH 1/2] PCI: mediatek-gen3: Add power and reset control feature for downstream component Date: Wed, 11 Jan 2023 11:28:29 +0800 Message-ID: <20230111032830.20447-2-jian.yang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230111032830.20447-1-jian.yang@mediatek.com> References: <20230111032830.20447-1-jian.yang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "jian.yang" Make MediaTek's controller driver capable of controlling power supplies and reset pin of a downstream component in power-on and power-off flow. Some downstream components (e.g., a WIFI chip) may need an extra reset other than of PERST# and their power supplies, depending on the requirements of platform, may need to controlled by their parent's driver. To meet the requirements described above, I add this feature to MediaTek's PCIe controller driver as a optional feature. Signed-off-by: jian.yang --- drivers/pci/controller/pcie-mediatek-gen3.c | 114 +++++++++++++++++++- 1 file changed, 113 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index b8612ce5f4d0..5ddbc2a0c020 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -8,6 +8,8 @@ =20 #include #include +#include +#include #include #include #include @@ -15,11 +17,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include =20 #include "../pci.h" @@ -100,6 +104,13 @@ #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) =20 +/* Downstream Component power supplies used by MediaTek PCIe */ +static const char *const dsc_power_supplies[] =3D { + "pcie1v8", + "pcie3v3", + "pcie12v", +}; + /** * struct mtk_msi_set - MSI information for each set * @base: IO mapped register base @@ -122,6 +133,10 @@ struct mtk_msi_set { * @phy: PHY controller block * @clks: PCIe clocks * @num_clks: PCIe clocks count for this port + * @supplies: Downstream Component power supplies + * @num_supplies: Downstream Component power supplies count + * @dsc_reset: The GPIO pin to reset Downstream component + * @dsc_reset_delay_ms: Delay in ms before the deassertion of reset GPIO * @irq: PCIe controller interrupt number * @saved_irq_state: IRQ enable state saved at suspend time * @irq_lock: lock protecting IRQ register access @@ -141,6 +156,10 @@ struct mtk_gen3_pcie { struct phy *phy; struct clk_bulk_data *clks; int num_clks; + struct regulator_bulk_data *supplies; + int num_supplies; + struct gpio_desc *dsc_reset; + u32 dsc_reset_delay_ms; =20 int irq; u32 saved_irq_state; @@ -763,7 +782,9 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pc= ie) struct device *dev =3D pcie->dev; struct platform_device *pdev =3D to_platform_device(dev); struct resource *regs; - int ret; + enum of_gpio_flags flags; + enum gpiod_flags dsc_reset_init_flags; + int ret, i; =20 regs =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac"); if (!regs) @@ -809,14 +830,103 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie = *pcie) return pcie->num_clks; } =20 + pcie->num_supplies =3D ARRAY_SIZE(dsc_power_supplies); + pcie->supplies =3D devm_kcalloc(dev, pcie->num_supplies, + sizeof(*pcie->supplies), + GFP_KERNEL); + if (!pcie->supplies) + return -ENOMEM; + + for (i =3D 0; i < pcie->num_supplies; i++) + pcie->supplies[i].supply =3D dsc_power_supplies[i]; + + ret =3D devm_regulator_bulk_get(dev, pcie->num_supplies, pcie->supplies); + if (ret) + return ret; + + ret =3D of_get_named_gpio_flags(dev->of_node, "dsc-reset-gpios", 0, + &flags); + if (ret < 0) { + if (ret =3D=3D -EPROBE_DEFER) + return ret; + + /* + * It's okay that the reset GPIO of a downstream component not + * defined in related devicetree node since it's an optional + * property. + */ + return 0; + } + + dsc_reset_init_flags =3D (flags & OF_GPIO_ACTIVE_LOW) ? GPIOD_OUT_HIGH : + GPIOD_OUT_LOW; + pcie->dsc_reset =3D devm_gpiod_get_optional(dev, "dsc-reset", + dsc_reset_init_flags); + if (IS_ERR(pcie->dsc_reset)) { + ret =3D PTR_ERR(pcie->dsc_reset); + if (ret !=3D -EPROBE_DEFER) + dev_err(dev, "failed to request DSC reset gpio\n"); + + return ret; + } + + ret =3D of_property_read_u32(dev->of_node, "dsc-reset-msleep", + &pcie->dsc_reset_delay_ms); + if (ret) { + dev_info(dev, "Failed to get delay time of DSC, set it to default 5ms\n"= ); + pcie->dsc_reset_delay_ms =3D 5; + } + return 0; } =20 +static int mtk_pcie_dsc_power_up(struct mtk_gen3_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + int ret; + + /* Assert Downstream Component reset */ + if (pcie->dsc_reset) + gpiod_set_value_cansleep(pcie->dsc_reset, 1); + + ret =3D regulator_bulk_enable(pcie->num_supplies, pcie->supplies); + if (ret) + dev_err(dev, "failed to enable DSC power supplies: %d\n", ret); + + /* De-assert Downstream Component reset */ + if (pcie->dsc_reset) { + /* + * Wait for a short time before we de-assert the reset GPIO. + * Depends on the requirement of a specific Downstream + * Component. + */ + usleep_range(1000 * pcie->dsc_reset_delay_ms, + 1000 * pcie->dsc_reset_delay_ms + 100); + gpiod_set_value_cansleep(pcie->dsc_reset, 0); + } + + return ret; +} + +static void mtk_pcie_dsc_power_down(struct mtk_gen3_pcie *pcie) +{ + /* Assert Downstream Component reset */ + if (pcie->dsc_reset) + gpiod_set_value_cansleep(pcie->dsc_reset, 1); + + regulator_bulk_disable(pcie->num_supplies, pcie->supplies); +} + static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) { struct device *dev =3D pcie->dev; int err; =20 + /* Downstream Component power up before RC */ + err =3D mtk_pcie_dsc_power_up(pcie); + if (err) + return err; + /* PHY power on and enable pipe clock */ reset_control_deassert(pcie->phy_reset); =20 @@ -855,6 +965,7 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) phy_exit(pcie->phy); err_phy_init: reset_control_assert(pcie->phy_reset); + mtk_pcie_dsc_power_down(pcie); =20 return err; } @@ -870,6 +981,7 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *p= cie) phy_power_off(pcie->phy); phy_exit(pcie->phy); reset_control_assert(pcie->phy_reset); + mtk_pcie_dsc_power_down(pcie); } =20 static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) --=20 2.18.0 From nobody Sat Sep 21 07:47:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25596C678D5 for ; Wed, 11 Jan 2023 03:30:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235316AbjAKD3v (ORCPT ); Tue, 10 Jan 2023 22:29:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235385AbjAKD3B (ORCPT ); Tue, 10 Jan 2023 22:29:01 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D4E3F00B; Tue, 10 Jan 2023 19:28:50 -0800 (PST) X-UUID: 0ce976b2916011eda06fc9ecc4dadd91-20230111 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; 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Wed, 11 Jan 2023 11:28:43 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 11 Jan 2023 11:28:42 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 11 Jan 2023 11:28:41 +0800 From: Jian Yang To: Lorenzo Pieralisi , Jianjun Wang , Rob Herring , Bjorn Helgaas , Matthias Brugger , Ryder Lee , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= CC: , , , , , , , , , , , Subject: [PATCH 2/2] dt-bindings: PCI: mediatek-gen3: Add support for controlling power and reset Date: Wed, 11 Jan 2023 11:28:30 +0800 Message-ID: <20230111032830.20447-3-jian.yang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230111032830.20447-1-jian.yang@mediatek.com> References: <20230111032830.20447-1-jian.yang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "jian.yang" Add new properties to support control power supplies and reset pin of a downstream component. Signed-off-by: jian.yang --- .../bindings/pci/mediatek-pcie-gen3.yaml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml = b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 7e8c7a2a5f9b..46149cc63989 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -84,6 +84,29 @@ properties: items: enum: [ phy, mac ] =20 + pcie1v8-supply: + description: + The regulator phandle that provides 1.8V power to downstream compone= nt. + + pcie3v3-supply: + description: + The regulator phandle that provides 3.3V power to downstream compone= nt. + + pcie12v-supply: + description: + The regulator phandle that provides 12V power to downstream componen= t. + + dsc-reset-gpios: + description: + The reset GPIO of a downstream component. + maxItems: 1 + + dsc-reset-msleep: + description: + The delay time between assertion and de-assertion of a downstream + component's reset GPIO. + maxItems: 1 + clocks: minItems: 4 maxItems: 6 --=20 2.18.0