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Signed-off-by: Sinthu Raja Acked-by: Krzysztof Kozlowski --- Changes in V3: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Add Acked-by tag. Changes in V2: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D *Address review comment - add entry in alphabetical order. V1: https://lore.kernel.org/linux-arm-kernel/20221018123849.23695-2-sinthu.= raja@ti.com/ V2: https://lore.kernel.org/lkml/20221107123852.8063-2-sinthu.raja@ti.com/ Documentation/devicetree/bindings/arm/ti/k3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentati= on/devicetree/bindings/arm/ti/k3.yaml index 203faab80142..acbc25108533 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -69,6 +69,7 @@ properties: - description: K3 J721s2 SoC items: - enum: + - ti,am68-sk - ti,j721s2-evm - const: ti,j721s2 =20 --=20 2.36.1 From nobody Mon Sep 15 19:47:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91005C54EBE for ; Tue, 10 Jan 2023 11:06:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231138AbjAJLGR (ORCPT ); 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Tue, 10 Jan 2023 03:04:34 -0800 (PST) X-Google-Smtp-Source: AMrXdXsV6yl1//5x9VBSZJuTpC1cOkaM3gSS2pCstisAhNjndwaBylse+Tncu258G1GX9pKzyFf6cQ== X-Received: by 2002:a05:6a20:1a84:b0:a7:89fd:884c with SMTP id ci4-20020a056a201a8400b000a789fd884cmr74400164pzb.11.1673348673874; Tue, 10 Jan 2023 03:04:33 -0800 (PST) Received: from LAP568U.mistral.in ([106.51.227.150]) by smtp.gmail.com with ESMTPSA id i7-20020a17090332c700b001897a8b537asm7840206plr.221.2023.01.10.03.04.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 03:04:33 -0800 (PST) From: Sinthu Raja X-Google-Original-From: Sinthu Raja To: Nishanth Menon , Tero Kristo , Rob Herring Cc: Vignesh Raghavendra , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sinthu Raja Subject: [RESEND PATCH V3 2/3] arm64: dts: ti: Add initial support for AM68 SK System on Module Date: Tue, 10 Jan 2023 16:30:51 +0530 Message-Id: <20230110110052.14851-3-sinthu.raja@ti.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230110110052.14851-1-sinthu.raja@ti.com> References: <20230110110052.14851-1-sinthu.raja@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-BESS-ID: 1673348675-304915-5399-3484-1 X-BESS-VER: 2019.1_20221214.2106 X-BESS-Apparent-Source-IP: 209.85.216.70 X-BESS-Outbound-Spam-Score: 0.40 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.245372 [from cloudscan10-138.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_SC0_MISMATCH_TO META: Envelope rcpt doesn't match header 0.40 BSF_SC0_SA085b META: Custom Rule SA085b 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.40 using account:ESS91090 scores of KILL_LEVEL=7.0 tests=BSF_SC0_MISMATCH_TO, BSF_SC0_SA085b, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sinthu Raja AM68 Starter Kit (SK) is a low cost, small form factor board designed for TI=E2=80=99s AM68 SoC. TI=E2=80=99s AM68 SoC comprises of dual core A72= , high performance vision accelerators, hardware accelerators, latest C71x DSP, high bandwidth real-time IPs for capture and display. The SoC is power optimized to provide best in class performance for industrial applications. AM68 SK supports the following interfaces: * 16 GB LPDDR4 RAM * x1 Gigabit Ethernet interface * x1 USB 3.1 Type-C port * x2 USB 3.1 Type-A ports * x1 PCIe M.2 M Key * 512 Mbit OSPI flash * x2 CSI2 Camera interface (RPi and TI Camera connector) * 40-pin Raspberry Pi GPIO header SK's System on Module (SoM) contains the SoC and DDR. Therefore, add DT node for the SOC and DDR on the SoM. Schematics: https://www.ti.com/lit/zip/SPRR463 TRM: http://www.ti.com/lit/pdf/spruj28 Signed-off-by: Sinthu Raja --- Changes in V3: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Addressed review comments - Removed the unused nodes that are disabled by default. OSPI support will be added once the OSPI node is enabled for J721s2/AM68 in= main DTSI. Changes in V2: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Address review comments - drop the empty lines. V1: https://lore.kernel.org/linux-arm-kernel/20221018123849.23695-3-sinthu.= raja@ti.com/ V2: https://lore.kernel.org/lkml/20221107123852.8063-3-sinthu.raja@ti.com/ arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/d= ts/ti/k3-am68-sk-som.dtsi new file mode 100644 index 000000000000..c35f81edee8c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j721s2.dtsi" +#include + +/ { + memory@80000000 { + device_type =3D "memory"; + /* 16 GB RAM */ + reg =3D <0x00 0x80000000 0x00 0x80000000>, + <0x08 0x80000000 0x03 0x80000000>; + }; + + /* Reserving memory regions still pending */ + reserved_memory: reserved-memory { + #address-cells =3D <2>; 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Tue, 10 Jan 2023 03:04:37 -0800 (PST) Received: from LAP568U.mistral.in ([106.51.227.150]) by smtp.gmail.com with ESMTPSA id i7-20020a17090332c700b001897a8b537asm7840206plr.221.2023.01.10.03.04.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 03:04:37 -0800 (PST) From: Sinthu Raja X-Google-Original-From: Sinthu Raja To: Nishanth Menon , Tero Kristo , Rob Herring Cc: Vignesh Raghavendra , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sinthu Raja Subject: [RESEND PATCH V3 3/3] arm64: dts: ti: k3-am68-sk: Add support for AM68 SK base board Date: Tue, 10 Jan 2023 16:30:52 +0530 Message-Id: <20230110110052.14851-4-sinthu.raja@ti.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230110110052.14851-1-sinthu.raja@ti.com> References: <20230110110052.14851-1-sinthu.raja@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-BESS-ID: 1673348678-304915-5402-3488-1 X-BESS-VER: 2019.1_20221214.2106 X-BESS-Apparent-Source-IP: 209.85.216.69 X-BESS-Outbound-Spam-Score: 0.90 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.245372 [from cloudscan13-229.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_SC0_MISMATCH_TO META: Envelope rcpt doesn't match header 0.40 BSF_SC0_SA085b META: Custom Rule SA085b 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.90 using account:ESS91090 scores of KILL_LEVEL=7.0 tests=BSF_SC0_MISMATCH_TO, BSF_SC0_SA085b, BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sinthu Raja The SK architecture comprises of baseboard and a SOM board. The AM68 Starter Kit's baseboard contains most of the actual connectors, power supply etc. The System on Module (SoM) is plugged on to the base board. Therefore, add support for peripherals brought out in the base board. Schematics: https://www.ti.com/lit/zip/SPRR463 Signed-off-by: Sinthu Raja --- Changes in V3: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D *Address review comments: - Remove the unused nodes that are disabled by default. - Update the gpio regulator node: gpio-regulator-tlv to "regulator-tlv". Changes in V2: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D *Address the review comments: - Update the commit description. - Update the regulator nodes: fixedregulator to "regulator-" - Update the commit $subject to align with rest of the commits. - Drop the blank lines - Change the node names that are added with underscore("_") with "-" V1: https://lore.kernel.org/linux-arm-kernel/20221018123849.23695-4-sinthu.= raja@ti.com/ V2: https://lore.kernel.org/lkml/20221107123852.8063-4-sinthu.raja@ti.com/ arch/arm64/boot/dts/ti/Makefile | 2 + .../boot/dts/ti/k3-am68-sk-base-board.dts | 335 ++++++++++++++++++ 2 files changed, 337 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index cf7c509538a4..1b4e8b573de5 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -12,6 +12,8 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am6528-iot2050-basic-pg2.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am6548-iot2050-advanced.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am6548-iot2050-advanced-pg2.dtb =20 +dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-sk-base-board.dtb + dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-beagleboneai64.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-common-proc-board.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts new file mode 100644 index 000000000000..2091cd2431fb --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Base Board: https://www.ti.com/lit/zip/SPRR463 + */ + +/dts-v1/; + +#include "k3-am68-sk-som.dtsi" +#include +#include +#include +#include + +/ { + compatible =3D "ti,am68-sk", "ti,j721s2"; + model =3D "Texas Instruments AM68 SK"; + + chosen { + stdout-path =3D "serial2:115200n8"; + }; + + aliases { + serial2 =3D &main_uart8; + mmc1 =3D &main_sdhci1; + can0 =3D &mcu_mcan0; + can1 =3D &mcu_mcan1; + can2 =3D &main_mcan6; + can3 =3D &main_mcan7; + }; + + vusb_main: regulator-vusb-main5v0 { + /* USB MAIN INPUT 5V DC */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vusb-main5v0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: regulator-vsys3v3 { + /* Output of LM5141 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vusb_main>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-sd { + /* Output of TPS22918 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_mmc1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply =3D <&vsys_3v3>; + gpio =3D <&exp1 10 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-tlv71033 { + /* Output of TLV71033 */ + compatible =3D "regulator-gpio"; + regulator-name =3D "tlv71033"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vdd_sd_dv_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + vin-supply =3D <&vsys_3v3>; + gpios =3D <&main_gpio0 49 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_io_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_io_1v2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + transceiver1: can-phy0 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + }; + + transceiver2: can-phy1 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + }; + + transceiver3: can-phy2 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + }; + + transceiver4: can-phy3 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + }; +}; + +&main_pmx0 { + main_uart8_pins_default: main-uart8-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ + J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */ + J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ + J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ + J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ + J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ + J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ + J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 = */ + >; + }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; + + main_mcan6_pins_default: main-mcan6-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */ + J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */ + >; + }; + + main_mcan7_pins_default: main-mcan7-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */ + J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ + >; + }; +}; + +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + >; + }; + + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_= RX */ + J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1= _TX*/ + >; + }; + + mcu_i2c1_pins_default: mcu-i2c1-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_S= CL */ + J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_S= DA */ + >; + }; +}; + +&main_gpio2 { + status =3D "disabled"; +}; + +&main_gpio4 { + status =3D "disabled"; +}; + +&main_gpio6 { + status =3D "disabled"; +}; + +&wkup_gpio0 { + status =3D "disabled"; +}; + +&wkup_gpio1 { + status =3D "disabled"; +}; + +&wkup_uart0 { + status =3D "reserved"; +}; + +&main_uart8 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart8_pins_default>; + /* Shared with TFA on this platform */ + power-domains =3D <&k3_pds 357 TI_SCI_PD_SHARED>; +}; + +&main_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c0_pins_default>; + clock-frequency =3D <400000>; + + exp1: gpio@21 { + compatible =3D "ti,tca6416"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", "HDMI_PDn", + "HDMI_LS_OE", "DP0_3V3 _EN", "BOARDID_EEPROM_WP", + "CAN_STB", " ", "GPIO_uSD_PWR_EN", "eDP_ENABLE", + "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_MCU_RGMII_RSTz", + "IO_EXP_CSI2_EXP_RSTz", " ", "CSI0_B_GPIO1", + "CSI1_B_GPIO1"; + }; +}; + +&main_sdhci0 { + /* Unused */ + status =3D "disabled"; +}; + +&main_sdhci1 { + /* SD card */ + pinctrl-0 =3D <&main_mmc1_pins_default>; + pinctrl-names =3D "default"; + disable-wp; + vmmc-supply =3D <&vdd_mmc1>; + vqmmc-supply =3D <&vdd_sd_dv>; +}; + +&mcu_cpsw { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + }; +}; + +&cpsw_port1 { + phy-mode =3D "rgmii-rxid"; + phy-handle =3D <&phy0>; +}; + +&mcu_mcan0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan0_pins_default>; + phys =3D <&transceiver1>; +}; + +&mcu_mcan1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan1_pins_default>; + phys =3D <&transceiver2>; +}; + +&main_mcan6 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcan6_pins_default>; + phys =3D <&transceiver3>; +}; + +&main_mcan7 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcan7_pins_default>; + phys =3D <&transceiver4>; +}; --=20 2.36.1