From nobody Mon Sep 15 22:56:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C34FC6379F for ; Mon, 9 Jan 2023 15:40:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229821AbjAIPku (ORCPT ); Mon, 9 Jan 2023 10:40:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237256AbjAIPkQ (ORCPT ); Mon, 9 Jan 2023 10:40:16 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36F3B40849 for ; Mon, 9 Jan 2023 07:36:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673278574; x=1704814574; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=r8x3W673a81adlsPw3G0WD1BeN7NIeYVAWdht6PQCa8=; b=GAzmxuIv3hvFSwnIKe2NT6QJVHxo9UxvpGZpbyXa/ItjsZVOeMawuzGK 10d6UHwW3aPVgzztmnxJzwoKX5R7C9hlSThBcWU2qz8AFk+2AaFkQ8l/o 6Y6gzKOeKeX1eAlxr9uY/66VeiO6y0npcHAcH4oUAgksE0YTt+I821tuJ sKqiIchzxOgp+OUP21liJXJuexB77FCGfL4ssjnEDzcawyUxDCTHMJD0s RUFMF0sDo72FnnB6V7Zo6LfYAoWPzj0sIm4qFets9dqlm7r+AHgkt8EaW Cg0SauwqrbQ1IyZeZFN6aL4czHN2py11I6yqv6Dwe4MWwMS8knszT+VsA w==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="385203559" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="385203559" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:11 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="902023878" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="902023878" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:11 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Ingo Molnar , alison.schofield@intel.com, reinette.chatre@intel.com, Tom Lendacky Subject: [PATCH v4 1/6] x86/microcode: Add a parameter to microcode_check() to store CPU capabilities Date: Mon, 9 Jan 2023 07:35:50 -0800 Message-Id: <20230109153555.4986-2-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109153555.4986-1-ashok.raj@intel.com> References: <20230109153555.4986-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a parameter to store CPU capabilities before performing a microcode update so that the code later can compare CPU capabilities before and after performing the update. Signed-off-by: Ashok Raj Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky Cc: Ingo Molnar --- Changes since V3 Boris: - Fix commit log to drop "next patch". - Add documentation to new parameter to microcode_check() --- arch/x86/include/asm/processor.h | 2 +- arch/x86/kernel/cpu/common.c | 21 +++++++++++++-------- arch/x86/kernel/cpu/microcode/core.c | 3 ++- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index 4e35c66edeb7..f256a4ddd25d 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -697,7 +697,7 @@ bool xen_set_default_idle(void); #endif =20 void __noreturn stop_this_cpu(void *dummy); -void microcode_check(void); +void microcode_check(struct cpuinfo_x86 *prev_info); =20 enum l1tf_mitigations { L1TF_MITIGATION_OFF, diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9cfca3d7d0e2..0f5a173d0871 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2297,30 +2297,35 @@ void cpu_init_secondary(void) #endif =20 #ifdef CONFIG_MICROCODE_LATE_LOADING -/* +/** + * microcode_check() - Check if any CPU capabilities changed after an upda= te. + * @prev_info: CPU capabilities stored before an update. + * * The microcode loader calls this upon late microcode load to recheck fea= tures, * only when microcode has been updated. Caller holds microcode_mutex and = CPU * hotplug lock. + * + * Return: None */ -void microcode_check(void) +void microcode_check(struct cpuinfo_x86 *prev_info) { - struct cpuinfo_x86 info; - perf_check_microcode(); =20 /* Reload CPUID max function as it might've changed. */ - info.cpuid_level =3D cpuid_eax(0); + prev_info->cpuid_level =3D cpuid_eax(0); =20 /* * Copy all capability leafs to pick up the synthetic ones so that * memcmp() below doesn't fail on that. The ones coming from CPUID will * get overwritten in get_cpu_cap(). */ - memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x= 86_capability)); + memcpy(&prev_info->x86_capability, &boot_cpu_data.x86_capability, + sizeof(prev_info->x86_capability)); =20 - get_cpu_cap(&info); + get_cpu_cap(prev_info); =20 - if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(i= nfo.x86_capability))) + if (!memcmp(&prev_info->x86_capability, &boot_cpu_data.x86_capability, + sizeof(prev_info->x86_capability))) return; =20 pr_warn("x86/CPU: CPU features have changed after loading microcode, but = might not take effect.\n"); diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index c4cd7328177b..e39d83be794b 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -439,6 +439,7 @@ static int __reload_late(void *info) static int microcode_reload_late(void) { int old =3D boot_cpu_data.microcode, ret; + struct cpuinfo_x86 prev_info; =20 pr_err("Attempting late microcode loading - it is dangerous and taints th= e kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); @@ -448,7 +449,7 @@ static int microcode_reload_late(void) =20 ret =3D stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret =3D=3D 0) - microcode_check(); + microcode_check(&prev_info); =20 pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); --=20 2.34.1 From nobody Mon Sep 15 22:56:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3743C54EBD for ; Mon, 9 Jan 2023 15:41:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235133AbjAIPlD (ORCPT ); Mon, 9 Jan 2023 10:41:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237270AbjAIPkS (ORCPT ); Mon, 9 Jan 2023 10:40:18 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52B7B40C0D for ; Mon, 9 Jan 2023 07:36:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673278578; x=1704814578; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5jjcFZaBdHqUBN/poJjyv4ZtShGVhA9wItTWkhuMVPg=; b=JEUZr6MUNmAxK8oOIna6QQmldrSjXw2Sxa1P5JjnlrySOaIUaFajcHNB hGD+QTmgWt2hxT1bPZRx6MQM4dXZ0vk5NwneJmdWv/Nt5gX52qH9s/abT AvgCRPeoN4ZftCUGW2BuSJAL/G6EL9WXW8/Pwb2FPA5dfZE9LME7O2DUf qjImo6vX46w5T3MsIIrnime65mYcIEFBdQBe4ZNTzMCCQjIviVi03aVhv y58v5264qDQRqFLVpGqaqqH13qkf8/TNZUOOOt5Y0j0MyzjxjnJUBOEjn r68SicYjWtROD62bG2N9im6gM/siliszh7l+JYug997pazefl+Npp5gKd w==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="385203565" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="385203565" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:12 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="902023883" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="902023883" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:11 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Ingo Molnar , alison.schofield@intel.com, reinette.chatre@intel.com, Tom Lendacky Subject: [PATCH v4 2/6] x86/microcode/core: Take a snapshot before and after applying microcode Date: Mon, 9 Jan 2023 07:35:51 -0800 Message-Id: <20230109153555.4986-3-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109153555.4986-1-ashok.raj@intel.com> References: <20230109153555.4986-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The kernel caches features about each CPU's features at boot in an x86_capability[] structure. The microcode update takes one snapshot and compares it with the saved copy at boot. However, the capabilities in the boot copy can be turned off as a result of certain command line parameters or configuration restrictions. This can cause a mismatch when comparing the values before and after the microcode update. microcode_check() is called after an update to report any previously cached CPUID bits might have changed due to the update. store_cpu_caps() basically stores the original CPU reported values and not the OS modified values. This will avoid giving a false warning even when no capabilities have changed. Ignore the capabilities recorded at boot. Take a new snapshot before the update and compare with a snapshot after the update to eliminate the false warning. Signed-off-by: Ashok Raj Fixes: 1008c52c09dc ("x86/CPU: Add a microcode loader callback") Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky Cc: Ingo Molnar --- Changes since V3: - Boris - Change function from microcode_store_cpu_caps -> store_cpu_caps - Split comments in store_cpu_caps(). - Dave Hansen - Change parameters names to something meaninful. - Cleaned up some commit log. Changes since V2: - Boris - Keep microcode_check() inside cpu/common.c and not bleed get_cpu_caps() outside of core code. - Thomas - Commit log changes. --- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/common.c | 39 ++++++++++++++++++++-------- arch/x86/kernel/cpu/microcode/core.c | 7 +++++ 3 files changed, 36 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index f256a4ddd25d..a77dee6a2bf2 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -698,6 +698,7 @@ bool xen_set_default_idle(void); =20 void __noreturn stop_this_cpu(void *dummy); void microcode_check(struct cpuinfo_x86 *prev_info); +void store_cpu_caps(struct cpuinfo_x86 *info); =20 enum l1tf_mitigations { L1TF_MITIGATION_OFF, diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 0f5a173d0871..f5c6feed6c26 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2297,6 +2297,29 @@ void cpu_init_secondary(void) #endif =20 #ifdef CONFIG_MICROCODE_LATE_LOADING +/** + * store_cpu_caps() - Store a snapshot of CPU capabilities + * + * Returns: None + */ +void store_cpu_caps(struct cpuinfo_x86 *curr_info) +{ + /* Reload CPUID max function as it might've changed. */ + curr_info->cpuid_level =3D cpuid_eax(0); + + /* + * Copy all capability leafs to pick up the synthetic ones + */ + memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, + sizeof(curr_info->x86_capability)); + + /* + * Capabilities copied from BSP will get overwritten + * with the snapshot below + */ + get_cpu_cap(curr_info); +} + /** * microcode_check() - Check if any CPU capabilities changed after an upda= te. * @prev_info: CPU capabilities stored before an update. @@ -2309,22 +2332,16 @@ void cpu_init_secondary(void) */ void microcode_check(struct cpuinfo_x86 *prev_info) { - perf_check_microcode(); + struct cpuinfo_x86 curr_info; =20 - /* Reload CPUID max function as it might've changed. */ - prev_info->cpuid_level =3D cpuid_eax(0); + perf_check_microcode(); =20 /* - * Copy all capability leafs to pick up the synthetic ones so that - * memcmp() below doesn't fail on that. The ones coming from CPUID will - * get overwritten in get_cpu_cap(). + * Get a snapshot of CPU capabilities */ - memcpy(&prev_info->x86_capability, &boot_cpu_data.x86_capability, - sizeof(prev_info->x86_capability)); - - get_cpu_cap(prev_info); + store_cpu_caps(&curr_info); =20 - if (!memcmp(&prev_info->x86_capability, &boot_cpu_data.x86_capability, + if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, sizeof(prev_info->x86_capability))) return; =20 diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index e39d83be794b..bb943a91a364 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -447,6 +447,13 @@ static int microcode_reload_late(void) atomic_set(&late_cpus_in, 0); atomic_set(&late_cpus_out, 0); =20 + /* + * Take a snapshot before the microcode update, so we can compare + * them after the update is successful to check for any bits + * changed. + */ + store_cpu_caps(&prev_info); + ret =3D stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret =3D=3D 0) microcode_check(&prev_info); --=20 2.34.1 From nobody Mon Sep 15 22:56:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5F25C5479D for ; Mon, 9 Jan 2023 15:40:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236367AbjAIPkz (ORCPT ); Mon, 9 Jan 2023 10:40:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237264AbjAIPkR (ORCPT ); Mon, 9 Jan 2023 10:40:17 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5255B40C0C for ; Mon, 9 Jan 2023 07:36:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673278578; x=1704814578; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=z6CTujcMHROo8G6A9RLI+GRnUF8GPfe/fb1oxgWV3u0=; b=D7g61m+3ySQMlN4ebKkALhQ0JGlZQTWtQvRq8tC8tav/u4oMCrqui+ki mdeSa1leYgTZwcAz0sbjL3blVz+IyvTaoedqDYcgb5VbIX3xSJF7K7H5x eQTQaz/8okWR4VfdNXBP7zPjIpOgRRGRhC/kGV+m+a3EsVp16NgcgtYpz 7gLfQWeHlBAL+PUcu1ghYD+S4u61sdfP2VGevRIHIOGty8tyvS1FMG98Y XOZ0cB4ohebjB3jlHdHxkRMM6pzSXqSGm5PKQ1UQ7dOBxnpBLWL0pm9LS 7mFENRjgNQMz2NvpNKacVrdRSRibph1G5iBLHTb23/6iCLtD+CRqrRB8U A==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="385203571" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="385203571" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:12 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="902023886" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="902023886" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:12 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Ingo Molnar , alison.schofield@intel.com, reinette.chatre@intel.com, Tom Lendacky Subject: [PATCH v4 3/6] x86/microcode: Display revisions only when update is successful Date: Mon, 9 Jan 2023 07:35:52 -0800 Message-Id: <20230109153555.4986-4-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109153555.4986-1-ashok.raj@intel.com> References: <20230109153555.4986-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Right now, microcode loading failures and successes print the same message "Reloading completed". This is misleading to users. Display the updated revision number only if an update was successful. Display "Reload completed" only if the update was successful, otherwise report the update failed. Signed-off-by: Ashok Raj Fixes: 9bd681251b7c ("x86/microcode: Announce reload operation's completion= ") Suggested-by: Thomas Gleixner Reviewed-by: Tony Luck Link: https://lore.kernel.org/lkml/874judpqqd.ffs@tglx/ Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky Cc: Ingo Molnar --- Changes since V3: Tony, Ingo - Print clear message if the update was successful or not. --- arch/x86/kernel/cpu/microcode/core.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index bb943a91a364..d7cbc83df9b6 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -455,11 +455,15 @@ static int microcode_reload_late(void) store_cpu_caps(&prev_info); =20 ret =3D stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); - if (ret =3D=3D 0) - microcode_check(&prev_info); =20 - pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", - old, boot_cpu_data.microcode); + if (ret =3D=3D 0) { + pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", + old, boot_cpu_data.microcode); + microcode_check(&prev_info); + } else { + pr_info("Reload failed, current microcode revision: 0x%x\n", + boot_cpu_data.microcode); + } =20 return ret; } --=20 2.34.1 From nobody Mon Sep 15 22:56:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B12BC5479D for ; Mon, 9 Jan 2023 15:41:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234733AbjAIPlG (ORCPT ); Mon, 9 Jan 2023 10:41:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237273AbjAIPkS (ORCPT ); Mon, 9 Jan 2023 10:40:18 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCF0C40C18 for ; Mon, 9 Jan 2023 07:36:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673278578; x=1704814578; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oyjz6XJwnWS6TtsCd6s9DEyvm+PHR2WDUT1F7iZ6FqM=; b=UklwSdFWE8e8lGt6XHSRo/YZ6RGdRgVP8qLKeqzDv7hkfP+eIeDdUNSe 1dHe04NLldtZIaqfs8VPpxlaPx9xzSX9ZcDi+21dRCZVm0ck3SuXLTy69 kKr5bidWpgN4ZrVNJWobHHUOEmuPy3I89lHEGLMV58D+bjvmj/5lpZ5Yx PTivUlxuWhhF8/ojcSgeQCNwcsrxhxpXNoZCyYIpjADPwEpKxC96pS2U+ h2T88zv/UEZ6l+jjDlcD09xhvVKaa+RVqxFVHRuWMPgbZQqxWyrRX9rT/ +rEyUx4epiC9grBQUawj5g8YfYAM3Olu1lw/Y7ScwkCtkYr6RKvtZuvgv A==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="385203578" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="385203578" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="902023890" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="902023890" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:12 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Ingo Molnar , alison.schofield@intel.com, reinette.chatre@intel.com, Tom Lendacky Subject: [PATCH v4 4/6] x86/microcode/intel: Use a plain revision argument for print_ucode_rev() Date: Mon, 9 Jan 2023 07:35:53 -0800 Message-Id: <20230109153555.4986-5-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109153555.4986-1-ashok.raj@intel.com> References: <20230109153555.4986-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" print_ucode_rev() takes a struct ucode_cpu_info argument. The sole purpose of it is to print the microcode revision. The only available ucode_cpu_info always describes the currently loaded microcode revision. After a microcode update is successful, this is the new revision, or on failure it is the original revision. Subsequent changes need to print both the original and new revision, but the original version will be cached in a plain integer, which makes the code inconsistent. Replace the struct ucode_cpu_info argument with a plain integer which contains the revision number and adjust the call sites accordingly. No functional change. Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky Cc: Ingo Molnar --- Changes since V1: Thomas: - Updated commit log as suggested - Remove the line break after static void before print_ucode_info --- arch/x86/kernel/cpu/microcode/intel.c | 31 ++++++++------------------- 1 file changed, 9 insertions(+), 22 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 6bebc46ad8b1..1d709b72cfd0 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,13 +310,10 @@ static bool load_builtin_intel_microcode(struct cpio_= data *cp) /* * Print ucode update info. */ -static void -print_ucode_info(struct ucode_cpu_info *uci, unsigned int date) +static void print_ucode_info(unsigned int new_rev, unsigned int date) { pr_info_once("microcode updated early to revision 0x%x, date =3D %04x-%02= x-%02x\n", - uci->cpu_sig.rev, - date & 0xffff, - date >> 24, + new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } =20 @@ -334,7 +331,7 @@ void show_ucode_info_early(void) =20 if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(&uci, current_mc_date); + print_ucode_info(uci.cpu_sig.rev. current_mc_date); delay_ucode_info =3D 0; } } @@ -343,33 +340,23 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode i= nfo in * show_ucode_info_early() until printk() works. */ -static void print_ucode(struct ucode_cpu_info *uci) +static void print_ucode(int new_rev, int date) { struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; =20 - mc =3D uci->mc; - if (!mc) - return; - delay_ucode_info_p =3D (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p =3D (int *)__pa_nodebug(¤t_mc_date); =20 *delay_ucode_info_p =3D 1; - *current_mc_date_p =3D mc->hdr.date; + *current_mc_date_p =3D date; } #else =20 -static inline void print_ucode(struct ucode_cpu_info *uci) +static inline void print_ucode(int new_rev, int date) { - struct microcode_intel *mc; - - mc =3D uci->mc; - if (!mc) - return; - - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(new_rev, date); } #endif =20 @@ -409,9 +396,9 @@ static int apply_microcode_early(struct ucode_cpu_info = *uci, bool early) uci->cpu_sig.rev =3D rev; =20 if (early) - print_ucode(uci); + print_ucode(uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); =20 return 0; } --=20 2.34.1 From nobody Mon Sep 15 22:56:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90C7EC5479D for ; Mon, 9 Jan 2023 15:41:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235465AbjAIPlL (ORCPT ); Mon, 9 Jan 2023 10:41:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234001AbjAIPkS (ORCPT ); Mon, 9 Jan 2023 10:40:18 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32F3E40C00 for ; Mon, 9 Jan 2023 07:36:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673278579; x=1704814579; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xdjl9pGXxNvh2LhHThzo3G8n2sH1qvrqMnZU/btrLb0=; b=i82XtK2o/0GM5i1XNjEqUYQhRuKzn+PP5xyI8y5vYIQeb06KtbsJE0Hq +gmplA3IT9L55O+pDWuXdHqLCuCr4fTuSYuCrlHLi+cPwjhbJIhwWUhpF 7ISmD+PJ87uLsK8E2CHgOCQ1kA87Ix7UdVPsR8Yezpgl+0KTQyFxGvF/V 4fTYxI8L3CF0a1p9BQeTLXeh1AzulZ3GqW5aVHwnQBnFcRC7wmUl1cOEQ e1X/2W+MrGdSF1FgxqsbNgWPP0ql1gVL3WnJwSdCgBwWd64hfMLYoLivU BLCeSJrFh6Y4oM0jFIhJ+3nWS7IDIs9OaCl0KjAlMRmes7o0WTzyY7mhj Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="385203585" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="385203585" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="902023893" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="902023893" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:13 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Ingo Molnar , alison.schofield@intel.com, reinette.chatre@intel.com, Tom Lendacky Subject: [PATCH v4 5/6] x86/microcode/intel: Print old and new rev during early boot Date: Mon, 9 Jan 2023 07:35:54 -0800 Message-Id: <20230109153555.4986-6-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109153555.4986-1-ashok.raj@intel.com> References: <20230109153555.4986-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make early loading message to match late loading messages. Print both old and new revisions. This is helpful to know what the BIOS loaded revision is before an early update. New dmesg log is shown below. microcode: early update: 0x2b000041 -> 0x2b000070 date =3D 2000-01-01 Cache the early BIOS revision before the microcode update and change the print_ucode_info() so it prints both the old and new revision in the same format as microcode_reload_late(). Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky Cc: Ingo Molnar --- Updates since V1: Thomas: Commit log updates as suggested. --- arch/x86/kernel/cpu/microcode/intel.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 1d709b72cfd0..f24300830ed7 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,10 +310,10 @@ static bool load_builtin_intel_microcode(struct cpio_= data *cp) /* * Print ucode update info. */ -static void print_ucode_info(unsigned int new_rev, unsigned int date) +static void print_ucode_info(int old_rev, int new_rev, unsigned int date) { - pr_info_once("microcode updated early to revision 0x%x, date =3D %04x-%02= x-%02x\n", - new_rev, date & 0xffff, date >> 24, + pr_info_once("early update: 0x%x -> 0x%x, date =3D %04x-%02x-%02x\n", + old_rev, new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } =20 @@ -321,6 +321,7 @@ static void print_ucode_info(unsigned int new_rev, unsi= gned int date) =20 static int delay_ucode_info; static int current_mc_date; +static int early_old_rev; =20 /* * Print early updated ucode info after printk works. This is delayed info= dump. @@ -331,7 +332,7 @@ void show_ucode_info_early(void) =20 if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(uci.cpu_sig.rev. current_mc_date); + print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); delay_ucode_info =3D 0; } } @@ -340,30 +341,33 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode i= nfo in * show_ucode_info_early() until printk() works. */ -static void print_ucode(int new_rev, int date) +static void print_ucode(int old_rev, int new_rev, int date) { struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; + int *early_old_rev_p; =20 delay_ucode_info_p =3D (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p =3D (int *)__pa_nodebug(¤t_mc_date); + early_old_rev_p =3D (int *)__pa_nodebug(&early_old_rev); =20 *delay_ucode_info_p =3D 1; *current_mc_date_p =3D date; + *early_old_rev_p =3D old_rev; } #else =20 -static inline void print_ucode(int new_rev, int date) +static inline void print_ucode(int old_rev, int new_rev, int date) { - print_ucode_info(new_rev, date); + print_ucode_info(old_rev, new_rev, date); } #endif =20 static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; - u32 rev; + u32 rev, old_rev; =20 mc =3D uci->mc; if (!mc) @@ -389,6 +393,7 @@ static int apply_microcode_early(struct ucode_cpu_info = *uci, bool early) /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); =20 + old_rev =3D rev; rev =3D intel_get_microcode_revision(); if (rev !=3D mc->hdr.rev) return -1; @@ -396,9 +401,9 @@ static int apply_microcode_early(struct ucode_cpu_info = *uci, bool early) uci->cpu_sig.rev =3D rev; =20 if (early) - print_ucode(uci->cpu_sig.rev, mc->hdr.date); + print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); + print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); =20 return 0; } --=20 2.34.1 From nobody Mon Sep 15 22:56:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 929ACC54EBD for ; Mon, 9 Jan 2023 15:41:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237018AbjAIPlO (ORCPT ); Mon, 9 Jan 2023 10:41:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231365AbjAIPkT (ORCPT ); Mon, 9 Jan 2023 10:40:19 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABB7040C1A for ; Mon, 9 Jan 2023 07:36:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673278579; x=1704814579; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QXXGi44wA/1GusubxcaRaGB7tWBbRqkEstVsOgmVeSs=; b=WN+p0Lo1aXEdTYaFloozKoHzX2EocmSvk3Ntfa6qW3o1/r4dW2+pocez EFk5PFqttOFe3lDtF5O9XW3Totq86Ew8IB6nqkGX0uAxnoXqjv6I1tIaL pGOepCCeEscv53fPszjRlT+24InFpn86iw4LjamiCrLiNL91dnPdEppHB LjbzyP4gcc69U5ykTEaGL44/kGAEzvXxvaYdxyQot9A4DIPwc2/YUAhS/ /Z8ffwF4acSKfbzaOVkRcenv/r4kSfrStkMEVne9/T6AMicTKyr8QA02t QYyCGZL87fGqiaL5cvji1havSqtdIr8kz8B4qeFfGe1T9JXePdEGMu9ZA g==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="385203590" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="385203590" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:14 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="902023896" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="902023896" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:13 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Ingo Molnar , alison.schofield@intel.com, reinette.chatre@intel.com, Tom Lendacky Subject: [PATCH v4 6/6] x86/microcode/intel: Print when early microcode loading fails Date: Mon, 9 Jan 2023 07:35:55 -0800 Message-Id: <20230109153555.4986-7-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109153555.4986-1-ashok.raj@intel.com> References: <20230109153555.4986-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently when early microcode loading fails there is no way for the user to know that the update failed. Store the failed status and pass it to print_ucode_info() so that early loading failures are captured in dmesg. Signed-off-by: Ashok Raj Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky Cc: Ingo Molnar --- Changes since V1: Thomas: Fix commit log as suggested. --- arch/x86/kernel/cpu/microcode/intel.c | 28 +++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index f24300830ed7..0cdff9ed2a4e 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,11 +310,11 @@ static bool load_builtin_intel_microcode(struct cpio_= data *cp) /* * Print ucode update info. */ -static void print_ucode_info(int old_rev, int new_rev, unsigned int date) +static void print_ucode_info(bool failed, int old_rev, int new_rev, unsign= ed int date) { - pr_info_once("early update: 0x%x -> 0x%x, date =3D %04x-%02x-%02x\n", + pr_info_once("early update: 0x%x -> 0x%x, date =3D %04x-%02x-%02x %s\n", old_rev, new_rev, date & 0xffff, date >> 24, - (date >> 16) & 0xff); + (date >> 16) & 0xff, failed ? "FAILED" : ""); } =20 #ifdef CONFIG_X86_32 @@ -322,6 +322,7 @@ static void print_ucode_info(int old_rev, int new_rev, = unsigned int date) static int delay_ucode_info; static int current_mc_date; static int early_old_rev; +static bool early_failed; =20 /* * Print early updated ucode info after printk works. This is delayed info= dump. @@ -332,7 +333,7 @@ void show_ucode_info_early(void) =20 if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); + print_ucode_info(early_failed, early_old_rev, uci.cpu_sig.rev, current_m= c_date); delay_ucode_info =3D 0; } } @@ -341,26 +342,28 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode i= nfo in * show_ucode_info_early() until printk() works. */ -static void print_ucode(int old_rev, int new_rev, int date) +static void print_ucode(bool failed, int old_rev, int new_rev, int date) { - struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; int *early_old_rev_p; + bool *early_failed_p; =20 delay_ucode_info_p =3D (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p =3D (int *)__pa_nodebug(¤t_mc_date); early_old_rev_p =3D (int *)__pa_nodebug(&early_old_rev); + early_failed_p =3D (bool *)__pa_nodebug(&early_failed); =20 *delay_ucode_info_p =3D 1; *current_mc_date_p =3D date; *early_old_rev_p =3D old_rev; + *early_failed_p =3D failed; } #else =20 -static inline void print_ucode(int old_rev, int new_rev, int date) +static inline void print_ucode(bool failed, int old_rev, int new_rev, int = date) { - print_ucode_info(old_rev, new_rev, date); + print_ucode_info(failed, old_rev, new_rev, date); } #endif =20 @@ -368,6 +371,7 @@ static int apply_microcode_early(struct ucode_cpu_info = *uci, bool early) { struct microcode_intel *mc; u32 rev, old_rev; + int retval =3D 0; =20 mc =3D uci->mc; if (!mc) @@ -396,16 +400,16 @@ static int apply_microcode_early(struct ucode_cpu_inf= o *uci, bool early) old_rev =3D rev; rev =3D intel_get_microcode_revision(); if (rev !=3D mc->hdr.rev) - return -1; + retval =3D -1; =20 uci->cpu_sig.rev =3D rev; =20 if (early) - print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); + print_ucode(retval, old_rev, mc->hdr.rev, mc->hdr.date); else - print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); + print_ucode_info(retval, old_rev, uci->cpu_sig.rev, mc->hdr.date); =20 - return 0; + return retval; } =20 int __init save_microcode_in_initrd_intel(void) --=20 2.34.1