From nobody Tue Sep 16 02:28:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0207C677F1 for ; Mon, 9 Jan 2023 14:45:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234789AbjAIOpJ (ORCPT ); Mon, 9 Jan 2023 09:45:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233849AbjAIOo1 (ORCPT ); Mon, 9 Jan 2023 09:44:27 -0500 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 894351EC73 for ; Mon, 9 Jan 2023 06:44:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=Dv8TSHDNAro72IZgP4TBGST9tD70PdSgMAoaPaXFYjA=; b=dMseIfbldn976aWH7M42s84hjC e/k/kalfXPDw9ej+Ie0mXfYT7p+QWyIG3OK5iNBnnTFZeMj+/Ux/pSceAd7QiJWyTCFIG65houhAm znB5K2uIJkvZZxFV2LhaGj4LEc5OKtofnFuI8IU7JXbveSk7bPGgmtt3WOs3YyzD1teQbdGVHWpE6 sqq6G/LyZE6kWa6Uc+kGlaZEbMN5fW6BgFzsBycjV7xZCxU1HtxP62hNeN0hjT82DPNHYMU7DDc0S 755Wku2S7ww5JOdcfmh/QA9bD237HYOU6uX2LB3u8z1GuHAeJ0vsqv+bG4uiJUx+HmERR9OMDzLXB u3mEW2kQ==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtNk-003TyM-1d; Mon, 09 Jan 2023 15:44:12 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , alex.hung@amd.com, nicholas.kazlauskas@amd.com, sungjoon.kim@amd.com, seanpaul@chromium.org, bhawanpreet.lakha@amd.com, Shashank Sharma , ville.syrjala@linux.intel.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, kernel-dev@igalia.com, laurent.pinchart+renesas@ideasonboard.com, Melissa Wen , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 09/18] drm/amd/display: encapsulate atomic regamma operation Date: Mon, 9 Jan 2023 13:38:37 -0100 Message-Id: <20230109143846.1966301-10-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We are introducing DRM 3D LUT property to DM color pipeline in the next patch, but so far, only for atomic interface. By checking .set_output_transfer_func in DC drivers with MPC 3D LUT support, we can verify that regamma is only programmed when 3D LUT programming fails. As a groundwork to introduce 3D LUT programming and better understand each step, detach atomic regamma programming from the crtc colocr updating code. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 52 ++++++++++++------- 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index b54ef1392895..54d95745f0f0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -291,6 +291,36 @@ static int __set_output_tf(struct dc_transfer_func *fu= nc, return res ? 0 : -ENOMEM; } =20 +static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, + const struct drm_color_lut *regamma_lut, + uint32_t regamma_size) +{ + int ret =3D 0; + + if (regamma_size) { + /* CRTC RGM goes into RGM LUT. + * + * Note: here there is no implicit sRGB regamma. We are using + * degamma calculation from color module to calculate the curve + * from a linear base. + */ + stream->out_transfer_func->type =3D TF_TYPE_DISTRIBUTED_POINTS; + stream->out_transfer_func->tf =3D TRANSFER_FUNCTION_LINEAR; + + ret =3D __set_output_tf(stream->out_transfer_func, regamma_lut, + regamma_size); + } else { + /* + * No CRTC RGM means we can just put the block into bypass + * since we don't have any plane level adjustments using it. + */ + stream->out_transfer_func->type =3D TF_TYPE_BYPASS; + stream->out_transfer_func->tf =3D TRANSFER_FUNCTION_LINEAR; + } + + return ret; +} + /** * __set_input_tf - calculates the input transfer function based on expect= ed * input space. @@ -438,27 +468,11 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_s= tate *crtc) regamma_size, has_rom); if (r) return r; - } else if (has_regamma) { - /* CRTC RGM goes into RGM LUT. - * - * Note: here there is no implicit sRGB regamma. We are using - * degamma calculation from color module to calculate the curve - * from a linear base. - */ - stream->out_transfer_func->type =3D TF_TYPE_DISTRIBUTED_POINTS; - stream->out_transfer_func->tf =3D TRANSFER_FUNCTION_LINEAR; - - r =3D __set_output_tf(stream->out_transfer_func, regamma_lut, - regamma_size); + } else { + regamma_size =3D has_regamma ? regamma_size : 0; + r =3D amdgpu_dm_set_atomic_regamma(stream, regamma_lut, regamma_size); if (r) return r; - } else { - /* - * No CRTC RGM means we can just put the block into bypass - * since we don't have any plane level adjustments using it. - */ - stream->out_transfer_func->type =3D TF_TYPE_BYPASS; - stream->out_transfer_func->tf =3D TRANSFER_FUNCTION_LINEAR; } =20 /* --=20 2.35.1