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[92.176.231.205]) by smtp.gmail.com with ESMTPSA id bp28-20020a5d5a9c000000b00273cd321a1bsm4553900wrb.107.2023.01.07.11.18.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 11:18:41 -0800 (PST) From: Javier Martinez Canillas To: linux-kernel@vger.kernel.org Cc: Javier Martinez Canillas , Sam Ravnborg , Daniel Vetter , David Airlie , Thierry Reding , dri-devel@lists.freedesktop.org Subject: [PATCH v2 08/13] drm/panel-samsung-s6e88a0-ams452ef01: Drop custom DSI write macro Date: Sat, 7 Jan 2023 20:18:17 +0100 Message-Id: <20230107191822.3787147-9-javierm@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230107191822.3787147-1-javierm@redhat.com> References: <20230107191822.3787147-1-javierm@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There is a macro for this already in the header, use that instead and delete the custom DSI write macro defined in the driver. Signed-off-by: Javier Martinez Canillas Reviewed-by: Sam Ravnborg --- Changes in v2: - Add Sam Ravnborg's Reviewed-by tag. - Fix identation on macro usage (Sam Ravnborg). .../panel/panel-samsung-s6e88a0-ams452ef01.c | 44 ++++++++----------- 1 file changed, 18 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c b/dri= vers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c index 97ff7a18545c..7431cae7427e 100644 --- a/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c +++ b/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c @@ -28,14 +28,6 @@ s6e88a0_ams452ef01 *to_s6e88a0_ams452ef01(struct drm_pan= el *panel) return container_of(panel, struct s6e88a0_ams452ef01, panel); } =20 -#define dsi_dcs_write_seq(dsi, seq...) do { \ - static const u8 d[] =3D { seq }; \ - int ret; \ - ret =3D mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \ - if (ret < 0) \ - return ret; \ - } while (0) - static void s6e88a0_ams452ef01_reset(struct s6e88a0_ams452ef01 *ctx) { gpiod_set_value_cansleep(ctx->reset_gpio, 1); @@ -54,8 +46,8 @@ static int s6e88a0_ams452ef01_on(struct s6e88a0_ams452ef0= 1 *ctx) =20 dsi->mode_flags |=3D MIPI_DSI_MODE_LPM; =20 - dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands - dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity + mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands + mipi_dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polar= ity =20 ret =3D mipi_dsi_dcs_exit_sleep_mode(dsi); if (ret < 0) { @@ -65,23 +57,23 @@ static int s6e88a0_ams452ef01_on(struct s6e88a0_ams452e= f01 *ctx) msleep(120); =20 // set default brightness/gama - dsi_dcs_write_seq(dsi, 0xca, - 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, // V255 RR,GG,BB - 0x80, 0x80, 0x80, // V203 R,G,B - 0x80, 0x80, 0x80, // V151 R,G,B - 0x80, 0x80, 0x80, // V87 R,G,B - 0x80, 0x80, 0x80, // V51 R,G,B - 0x80, 0x80, 0x80, // V35 R,G,B - 0x80, 0x80, 0x80, // V23 R,G,B - 0x80, 0x80, 0x80, // V11 R,G,B - 0x6b, 0x68, 0x71, // V3 R,G,B - 0x00, 0x00, 0x00); // V1 R,G,B + mipi_dsi_dcs_write_seq(dsi, 0xca, + 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, // V255 RR,GG,BB + 0x80, 0x80, 0x80, // V203 R,G,B + 0x80, 0x80, 0x80, // V151 R,G,B + 0x80, 0x80, 0x80, // V87 R,G,B + 0x80, 0x80, 0x80, // V51 R,G,B + 0x80, 0x80, 0x80, // V35 R,G,B + 0x80, 0x80, 0x80, // V23 R,G,B + 0x80, 0x80, 0x80, // V11 R,G,B + 0x6b, 0x68, 0x71, // V3 R,G,B + 0x00, 0x00, 0x00); // V1 R,G,B // set default Amoled Off Ratio - dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a); - dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage - dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); - dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update - dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands + mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a); + mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss volta= ge + mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update + mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands =20 ret =3D mipi_dsi_dcs_set_display_on(dsi); if (ret < 0) { --=20 2.38.1