From nobody Fri Dec 19 02:49:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A828C61DB3 for ; Fri, 6 Jan 2023 20:12:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236652AbjAFUMJ (ORCPT ); Fri, 6 Jan 2023 15:12:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236509AbjAFULP (ORCPT ); Fri, 6 Jan 2023 15:11:15 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F336A3C0C1 for ; Fri, 6 Jan 2023 12:10:56 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id bg13-20020a05600c3c8d00b003d9712b29d2so4357454wmb.2 for ; Fri, 06 Jan 2023 12:10:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BFnUrWdhcpbNtSqH6LxEFiIYrDwMlWVSmVEBxpFj6cM=; b=mvWNmxWZiAXb3M0bCWC6WeMr0cnhJ78K19CTFV24cLloA2Z9GDssXD6y8YoofoDGPO qXyLmxNG2ISmO5pEjvDDNg6Efbxd8NxM9va1pCx7COSqxEMJoYQ4rq9ScOD1Y2MYm7nB WZqgcGZOGnPhlKt/IGqH0OwQnDAUpy1YrcmeMwv3G7G2v/oDmQphcHsZAEU164yWWp/u MfSA35xdhq5QvRCR1fNDbb1mg0L0KctDRyNw/f85EuyMxYOTo4Fa25JjU6l+8tEFWgud /bJgqi1WTdBvaK4YtjohzZS1SVdjOEsMQbRh88lDrABv0tY25LVeV/77ITHFDF0vJS7o r9DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BFnUrWdhcpbNtSqH6LxEFiIYrDwMlWVSmVEBxpFj6cM=; b=0bOmq7mwK6sDQ0d4lhNy9GK6jJIDIyZgrmp/zuNbjTJCzGC39GpgxguoxzqjumOSbM uRhSh9oNmElPeF+2MEAnHvxwlDXO3PX0RCctIZZCfxtWBRG6CWn61zXQCJJwi6VkHPqh kK0oKA/4noxNn4Lq8obXY/74jSPhEC7Op58x/ClnqznbjA6/gGAuh59+Bmh1xITPuY6p LXt+hsO7jlSK9lDz5DtjhdbDPecnNLCJm9NxZmjv4BCVxd+jl9x/VpC/I8/Ww6z6xWx9 QftvX3P/QjF13Oh8zZPPkvPb5YUkDwlkUZQkmhCCvBb39l8OhmtWtIlmg1dwFgPaPmI/ Gm7g== X-Gm-Message-State: AFqh2kpmj1jhXQHMnG9H9+QSHSKqbE/6R58CyUx+HxHkp06shGdkJQO3 008puBke0J2+ICFCOMXxCVmVuQ== X-Google-Smtp-Source: AMrXdXuDgG4Cvk8z78KMgAIg8T9lDwPHaDfoKaBgZ6dSjWaFFwpKcE4Lb4ba+QSog5vYq/U57wXwPQ== X-Received: by 2002:a05:600c:348b:b0:3d2:2a72:2577 with SMTP id a11-20020a05600c348b00b003d22a722577mr39300378wmq.27.1673035855451; Fri, 06 Jan 2023 12:10:55 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id z14-20020a05600c220e00b003d99fad7511sm2665240wml.22.2023.01.06.12.10.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jan 2023 12:10:54 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Neil Armstrong , Dmitry Baryshkov Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v9 01/10] dt-bindings: arm: qcom: Document SM8550 SoC and boards Date: Fri, 6 Jan 2023 22:10:38 +0200 Message-Id: <20230106201047.337409-2-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106201047.337409-1-abel.vesa@linaro.org> References: <20230106201047.337409-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the SM8550 SoC binding and the MTP board. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 27063a045bd0..f5a8fb4aa288 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -70,6 +70,7 @@ description: | sm8250 sm8350 sm8450 + sm8550 =20 The 'board' element must be one of the following strings: =20 @@ -845,6 +846,11 @@ properties: - sony,pdx224 - const: qcom,sm8450 =20 + - items: + - enum: + - qcom,sm8550-mtp + - const: qcom,sm8550 + # Board compatibles go above =20 qcom,msm-id: --=20 2.34.1 From nobody Fri Dec 19 02:49:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F318BC63797 for ; Fri, 6 Jan 2023 20:12:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236894AbjAFUMZ (ORCPT ); Fri, 6 Jan 2023 15:12:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236570AbjAFULP (ORCPT ); Fri, 6 Jan 2023 15:11:15 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 447797622C for ; Fri, 6 Jan 2023 12:10:59 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id m3so1848168wmq.0 for ; Fri, 06 Jan 2023 12:10:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9r1Vml2dkeb6yrrBPNKdw29kVVt0hKLXNCcTb0/ykrI=; b=qxY7JZ7YN0cbxJ3vDka0LXqunwCOTc+KQKK0wnYPCOlXNVaJ8hu4LocdfBjhC6tQvv DdKjBsKJa4dFf7Jk/llA7ItT3MnAkeY1HE+/hhNIoZiB4EtLn5/9YKwX2hzRVcL7i9Y4 UMkwrU4nTQQCLNzj+6jc/Tg/iyJcW3X1XUVZa8j8wlGLhHCGEPdVskegfRENQre1ZVVm TbdrVtVwsvSouCKdzlWVJB30EyBNyUjh8giegfAs2ar2KlzebJcgvwxTrwA7sYL4MJWO t1JpyAO7N/rTaqjzJY2nlrYN9BuIFvencct6xQeGAqGzDk4QpF3fIA4u1O3D0vXOr28v Y4Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9r1Vml2dkeb6yrrBPNKdw29kVVt0hKLXNCcTb0/ykrI=; b=sbKMiRpKAWWmBZdhERqvcCpb56E1wPYhkWV8B0sIZ0qUGkGWqSsxwHkoJsglEmLZNT y8fh5SKqyN5SEJNSyTXNV0qCR+mcJ/jslNzW4jZz/PL7PZtI/DNzZZQCgzQIMdBqWV3y Ovi0DN3YVHfuS3GSmMCHMc1oNDLN4WfbkRBOuz/a7xxGmAmeyr9Dl82EFU6XiuOBTpoS BO290BNIFiuLy0GnGabCYawXRAgUFYNz9pkhfu5wLjFT55y3cW7af15sFe3vhcg+uT+y LzQApJlOXZAvgfUxdfka8ZhlzZSiaUZ2ZttWS581cGG82oZGVDwhfHi3+fUpHgMKI4Ps h1Yg== X-Gm-Message-State: AFqh2kprlRAlZw4vewIzpFDF2R0AV/bOrvY+/ioLIds72DMPTGfCKWQR hQbRoac1mUwdm8pbdRX2ftzJxw== X-Google-Smtp-Source: AMrXdXuzylbTo6awrAEnLaqgonXh9+NdnvkJuDSIHnH6H3XfB5cSZwKXxheckD9tXzXdo4dLmjW54A== X-Received: by 2002:a05:600c:34cf:b0:3d0:7415:c5a9 with SMTP id d15-20020a05600c34cf00b003d07415c5a9mr41811215wmq.21.1673035857010; Fri, 06 Jan 2023 12:10:57 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id z14-20020a05600c220e00b003d99fad7511sm2665240wml.22.2023.01.06.12.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jan 2023 12:10:56 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Neil Armstrong , Dmitry Baryshkov Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Sai Prakash Ranjan Subject: [PATCH v9 02/10] arm64: dts: qcom: Add base SM8550 dtsi Date: Fri, 6 Jan 2023 22:10:39 +0200 Message-Id: <20230106201047.337409-3-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106201047.337409-1-abel.vesa@linaro.org> References: <20230106201047.337409-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add base dtsi for SM8550 SoC and includes base description of CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, interconnect, thermal sensor, cpu cooling maps and SMMU nodes which helps boot to shell with console on boards with this SoC. Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Sai Prakash Ranjan --- Changes since v8: * fixed indentation issues reported by Krzysztof * added cache-level property to each cache node, like Krzysztof suggested * added bi_tcxo and bi_tcxo_ao fixed factor dividers to the top level /clocks node arch/arm64/boot/dts/qcom/sm8550.dtsi | 3549 ++++++++++++++++++++++++++ 1 file changed, 3549 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8550.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi new file mode 100644 index 000000000000..2d9377e01c3f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -0,0 +1,3549 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0 0>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + power-domains =3D <&CPU_PD0>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + #cooling-cells =3D <2>; + L2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + next-level-cache =3D <&L3_0>; + L3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0 0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_100>; + power-domains =3D <&CPU_PD1>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + #cooling-cells =3D <2>; + L2_100: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0 0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_200>; + power-domains =3D <&CPU_PD2>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + #cooling-cells =3D <2>; + L2_200: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0 0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_300>; + power-domains =3D <&CPU_PD3>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + capacity-dmips-mhz =3D <1792>; + dynamic-power-coefficient =3D <270>; + #cooling-cells =3D <2>; + L2_300: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0 0x400>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_400>; + power-domains =3D <&CPU_PD4>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + capacity-dmips-mhz =3D <1792>; + dynamic-power-coefficient =3D <270>; + #cooling-cells =3D <2>; + L2_400: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0 0x500>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_500>; + power-domains =3D <&CPU_PD5>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + capacity-dmips-mhz =3D <1792>; + dynamic-power-coefficient =3D <270>; + #cooling-cells =3D <2>; + L2_500: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0 0x600>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_600>; + power-domains =3D <&CPU_PD6>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + capacity-dmips-mhz =3D <1792>; + dynamic-power-coefficient =3D <270>; + #cooling-cells =3D <2>; + L2_600: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0 0x700>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_700>; + power-domains =3D <&CPU_PD7>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 2>; + capacity-dmips-mhz =3D <1894>; + dynamic-power-coefficient =3D <588>; + #cooling-cells =3D <2>; + L2_700: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + next-level-cache =3D <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&CPU0>; + }; + + core1 { + cpu =3D <&CPU1>; + }; + + core2 { + cpu =3D <&CPU2>; + }; + + core3 { + cpu =3D <&CPU3>; + }; + + core4 { + cpu =3D <&CPU4>; + }; + + core5 { + cpu =3D <&CPU5>; + }; + + core6 { + cpu =3D <&CPU6>; + }; + + core7 { + cpu =3D <&CPU7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <800>; + exit-latency-us =3D <750>; + min-residency-us =3D <4090>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <600>; + exit-latency-us =3D <1550>; + min-residency-us =3D <4791>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000044>; + entry-latency-us =3D <1050>; + exit-latency-us =3D <2500>; + min-residency-us =3D <5309>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x4100c344>; + entry-latency-us =3D <2700>; + exit-latency-us =3D <3500>; + min-residency-us =3D <13959>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-sm8550", "qcom,scm"; + }; + }; + + clk_virt: interconnect-0 { + compatible =3D "qcom,sm8550-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible =3D "qcom,sm8550-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + memory@a0000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0 0xa0000000 0 0>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hyp_mem: hyp-region@80000000 { + reg =3D <0 0x80000000 0 0xa00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm-region@80a00000 { + reg =3D <0 0x80a00000 0 0x400000>; + no-map; + }; + + hyp_tags_mem: hyp-tags-region@80e00000 { + reg =3D <0 0x80e00000 0 0x3d0000>; + no-map; + }; + + xbl_sc_mem: xbl-sc-region@d8100000 { + reg =3D <0 0xd8100000 0 0x40000>; + no-map; + }; + + + hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { + reg =3D <0 0x811d0000 0 0x30000>; + no-map; + }; + + /* merged xbl_dt_log, xbl_ramdump, aop_image */ + xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { + reg =3D <0 0x81a00000 0 0x260000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-region@81c60000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0 0x81c60000 0 0x20000>; + no-map; + }; + + /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ + aop_config_merged_mem: aop-config-merged-region@81c80000 { + reg =3D <0 0x81c80000 0 0x74000>; + no-map; + }; + + /* secdata region can be reused by apps */ + smem: smem@81d00000 { + compatible =3D "qcom,smem"; + reg =3D <0 0x81d00000 0 0x200000>; + hwlocks =3D <&tcsr_mutex 3>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi-region@81f00000 { + reg =3D <0 0x81f00000 0 0x20000>; + no-map; + }; + + global_sync_mem: global-sync-region@82600000 { + reg =3D <0 0x82600000 0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat-region@82700000 { + reg =3D <0 0x82700000 0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { + reg =3D <0 0x82800000 0 0x4600000>; + no-map; + }; + + mpss_mem: mpss-region@8a800000 { + reg =3D <0 0x8a800000 0 0x10800000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { + reg =3D <0 0x9b000000 0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@9b080000 { + reg =3D <0 0x9b080000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@9b090000 { + reg =3D <0 0x9b090000 0 0xa000>; + no-map; + }; + + gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { + reg =3D <0 0x9b09a000 0 0x2000>; + no-map; + }; + + spss_region_mem: spss-region@9b100000 { + reg =3D <0 0x9b100000 0 0x180000>; + no-map; + }; + + /* First part of the "SPU secure shared memory" region */ + spu_tz_shared_mem: spu-tz-shared-region@9b280000 { + reg =3D <0 0x9b280000 0 0x60000>; + no-map; + }; + + /* Second part of the "SPU secure shared memory" region */ + spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { + reg =3D <0 0x9b2e0000 0 0x20000>; + no-map; + }; + + camera_mem: camera-region@9b300000 { + reg =3D <0 0x9b300000 0 0x800000>; + no-map; + }; + + video_mem: video-region@9bb00000 { + reg =3D <0 0x9bb00000 0 0x700000>; + no-map; + }; + + cvp_mem: cvp-region@9c200000 { + reg =3D <0 0x9c200000 0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp-region@9c900000 { + reg =3D <0 0x9c900000 0 0x2000000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { + reg =3D <0 0x9e900000 0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { + reg =3D <0 0x9e980000 0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi-region@9ea00000 { + reg =3D <0 0x9ea00000 0 0x4080000>; + no-map; + }; + + /* uefi region can be reused by apps */ + + /* Linux kernel image is loaded at 0xa8000000 */ + + mpss_dsm_mem: mpss-dsm-region@d4d00000 { + reg =3D <0 0xd4d00000 0 0x3300000>; + no-map; + }; + + tz_reserved_mem: tz-reserved-region@d8000000 { + reg =3D <0 0xd8000000 0 0x100000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw-region@d8140000 { + reg =3D <0 0xd8140000 0 0x1c0000>; + no-map; + }; + + qtee_mem: qtee-region@d8300000 { + reg =3D <0 0xd8300000 0 0x500000>; + no-map; + }; + + ta_mem: ta-region@d8800000 { + reg =3D <0 0xd8800000 0 0x8a00000>; + no-map; + }; + + tz_tags_mem: tz-tags-region@e1200000 { + reg =3D <0 0xe1200000 0 0x2740000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf-region@e6440000 { + reg =3D <0 0xe6440000 0 0x279000>; + no-map; + }; + + trust_ui_vm_mem: trust-ui-vm-region@f3600000 { + reg =3D <0 0xf3600000 0 0x4aee000>; + no-map; + }; + + trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { + reg =3D <0 0xf80ee000 0 0x1000>; + no-map; + }; + + trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { + reg =3D <0 0xf80ef000 0 0x9000>; + no-map; + }; + + trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { + reg =3D <0 0xf80f8000 0 0x4000>; + no-map; + }; + + trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { + reg =3D <0 0xf80fc000 0 0x4000>; + no-map; + }; + + trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { + reg =3D <0 0xf8100000 0 0x100000>; + no-map; + }; + + oem_vm_mem: oem-vm-region@f8400000 { + reg =3D <0 0xf8400000 0 0x4800000>; + no-map; + }; + + oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { + reg =3D <0 0xfcc00000 0 0x4000>; + no-map; + }; + + oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { + reg =3D <0 0xfcc04000 0 0x100000>; + no-map; + }; + + hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { + reg =3D <0 0xfce00000 0 0x2900000>; + no-map; + }; + + hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { + reg =3D <0 0xff700000 0 0x100000>; + no-map; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0 0x10 0>; + dma-ranges =3D <0 0 0 0 0x10 0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,sm8550-gcc"; + reg =3D <0 0x00100000 0 0x1f4200>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + clocks =3D <&bi_tcxo_div2>, <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + }; + + ipcc: mailbox@408000 { + compatible =3D "qcom,sm8550-ipcc", "qcom,ipcc"; + reg =3D <0 0x00408000 0 0x1000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + #mbox-cells =3D <2>; + }; + + gpi_dma2: dma-controller@800000 { + compatible =3D "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; + #dma-cells =3D <3>; + reg =3D <0 0x00800000 0 0x60000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels =3D <12>; + dma-channel-mask =3D <0x3e>; + iommus =3D <&apps_smmu 0x436 0>; + status =3D "disabled"; + }; + + qupv3_id_1: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0 0x008c0000 0 0x2000>; + ranges; + clock-names =3D "m-ahb", "s-ahb"; + clocks =3D <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus =3D <&apps_smmu 0x423 0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + status =3D "disabled"; + + i2c8: i2c@880000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00880000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c8_data_clk>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi8: spi@880000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00880000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi8_data_clk>, <&qup_spi8_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c9: i2c@884000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00884000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c9_data_clk>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi9: spi@884000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00884000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi9_data_clk>, <&qup_spi9_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c10: i2c@888000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00888000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c10_data_clk>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi10: spi@888000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00888000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi10_data_clk>, <&qup_spi10_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c11: i2c@88c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x0088c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c11_data_clk>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi11: spi@88c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0088c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi11_data_clk>, <&qup_spi11_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c12: i2c@890000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00890000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c12_data_clk>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi12: spi@890000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00890000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi12_data_clk>, <&qup_spi12_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c13: i2c@894000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00894000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c13_data_clk>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi13: spi@894000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00894000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi13_data_clk>, <&qup_spi13_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c15: i2c@89c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x0089c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c15_data_clk>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi15: spi@89c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0089c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi15_data_clk>, <&qup_spi15_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible =3D "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; + #dma-cells =3D <3>; + reg =3D <0 0x00a00000 0 0x60000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels =3D <12>; + dma-channel-mask =3D <0x1e>; + iommus =3D <&apps_smmu 0xb6 0>; + status =3D "disabled"; + }; + + qupv3_id_0: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0 0x00ac0000 0 0x2000>; + ranges; + clock-names =3D "m-ahb", "s-ahb"; + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus =3D <&apps_smmu 0xa3 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CO= RE_1 0>; + interconnect-names =3D "qup-core"; + #address-cells =3D <2>; + #size-cells =3D <2>; + status =3D "disabled"; + + i2c0: i2c@a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a80000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c0_data_clk>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi0: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a80000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi0_data_clk>, <&qup_spi0_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a84000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c1_data_clk>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi1: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a84000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi1_data_clk>, <&qup_spi1_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a88000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c2_data_clk>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi2: spi@a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a88000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi2_data_clk>, <&qup_spi2_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a8c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c3_data_clk>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi3: spi@a8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a8c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi3_data_clk>, <&qup_spi3_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a90000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c4_data_clk>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + spi4: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a90000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi4_data_clk>, <&qup_spi4_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a94000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c5_data_clk>; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi5: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a94000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi5_data_clk>, <&qup_spi5_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c6: i2c@a98000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a98000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_i2c6_data_clk>; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi6: spi@a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a98000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi6_data_clk>, <&qup_spi6_cs>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart7: serial@a9c000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0 0x00a9c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_uart7_default>; + interrupts =3D ; + interconnect-names =3D "qup-core", "qup-config"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + cnoc_main: interconnect@1500000 { + compatible =3D "qcom,sm8550-cnoc-main"; + reg =3D <0 0x01500000 0 0x13080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + config_noc: interconnect@1600000 { + compatible =3D "qcom,sm8550-config-noc"; + reg =3D <0 0x01600000 0 0x6200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,sm8550-system-noc"; + reg =3D <0 0x01680000 0 0x1d080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie_noc: interconnect@16c0000 { + compatible =3D "qcom,sm8550-pcie-anoc"; + reg =3D <0 0x016c0000 0 0x12200>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible =3D "qcom,sm8550-aggre1-noc"; + reg =3D <0 0x016e0000 0 0x14400>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,sm8550-aggre2-noc"; + reg =3D <0 0x01700000 0 0x1e400>; + #interconnect-cells =3D <2>; + clocks =3D <&rpmhcc RPMH_IPA_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1780000 { + compatible =3D "qcom,sm8550-mmss-noc"; + reg =3D <0 0x01780000 0 0x5b800>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0 0x01f40000 0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible =3D "qcom,sm8550-tcsr", "syscon"; + reg =3D <0 0x01fc0000 0 0x30000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible =3D "qcom,sm8550-lpass-lpiaon-noc"; + reg =3D <0 0x07400000 0 0x19080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + lpass_lpicx_noc: interconnect@7430000 { + compatible =3D "qcom,sm8550-lpass-lpicx-noc"; + reg =3D <0 0x07430000 0 0x3a200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible =3D "qcom,sm8550-lpass-ag-noc"; + reg =3D <0 0x07e40000 0 0xe080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + sdhc_2: mmc@8804000 { + compatible =3D "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0 0x08804000 0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "core", "xo"; + iommus =3D <&apps_smmu 0x540 0>; + qcom,dll-config =3D <0x0007642c>; + qcom,ddr-config =3D <0x80040868>; + power-domains =3D <&rpmhpd SM8550_CX>; + operating-points-v2 =3D <&sdhc2_opp_table>; + + interconnects =3D <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; + bus-width =3D <4>; + dma-coherent; + + /* Forbid SDR104/SDR50 - broken hw! */ + sdhci-caps-mask =3D <0x3 0>; + + status =3D "disabled"; + + sdhc2_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz =3D /bits/ 64 <50000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,sm8550-pdc", "qcom,pdc"; + reg =3D <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + qcom,pdc-ranges =3D <0 480 94>, <94 609 31>, + <125 63 1>, <126 716 12>, + <138 251 5>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c271000 { + compatible =3D "qcom,sm8550-tsens", "qcom,tsens-v2"; + reg =3D <0 0x0c271000 0 0x1000>, /* TM */ + <0 0x0c222000 0 0x1000>; /* SROT */ + #qcom,sensors =3D <16>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + }; + + tsens1: thermal-sensor@c272000 { + compatible =3D "qcom,sm8550-tsens", "qcom,tsens-v2"; + reg =3D <0 0x0c272000 0 0x1000>, /* TM */ + <0 0x0c223000 0 0x1000>; /* SROT */ + #qcom,sensors =3D <16>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + }; + + tsens2: thermal-sensor@c273000 { + compatible =3D "qcom,sm8550-tsens", "qcom,tsens-v2"; + reg =3D <0 0x0c273000 0 0x1000>, /* TM */ + <0 0x0c224000 0 0x1000>; /* SROT */ + #qcom,sensors =3D <16>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + }; + + aoss_qmp: power-controller@c300000 { + compatible =3D "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0 0x0c300000 0 0x400>; + interrupt-parent =3D <&ipcc>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_= QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells =3D <0>; + }; + + sram@c3f0000 { + compatible =3D "qcom,rpmh-stats"; + reg =3D <0 0x0c3f0000 0 0x400>; + }; + + spmi_bus: spmi@c400000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0 0x0c400000 0 0x3000>, + <0 0x0c500000 0 0x4000000>, + <0 0x0c440000 0 0x80000>, + <0 0x0c4c0000 0 0x20000>, + <0 0x0c42d000 0 0x4000>; + reg-names =3D "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + qcom,bus-id =3D <0>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + + tlmm: pinctrl@f000000 { + compatible =3D "qcom,sm8550-tlmm"; + reg =3D <0 0x0f100000 0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 211>; + wakeup-parent =3D <&pdc>; + + hub_i2c0_data_clk: hub-i2c0-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio16", "gpio17"; + function =3D "i2chub0_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c1_data_clk: hub-i2c1-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio18", "gpio19"; + function =3D "i2chub0_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c2_data_clk: hub-i2c2-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio20", "gpio21"; + function =3D "i2chub0_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c3_data_clk: hub-i2c3-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio22", "gpio23"; + function =3D "i2chub0_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c4_data_clk: hub-i2c4-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio4", "gpio5"; + function =3D "i2chub0_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c5_data_clk: hub-i2c5-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio6", "gpio7"; + function =3D "i2chub0_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c6_data_clk: hub-i2c6-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio8", "gpio9"; + function =3D "i2chub0_se6"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c7_data_clk: hub-i2c7-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio10", "gpio11"; + function =3D "i2chub0_se7"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c8_data_clk: hub-i2c8-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio206", "gpio207"; + function =3D "i2chub0_se8"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c9_data_clk: hub-i2c9-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio84", "gpio85"; + function =3D "i2chub0_se9"; + drive-strength =3D <2>; + bias-pull-up; + }; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins =3D "gpio94"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + clkreq-pins { + pins =3D "gpio95"; + function =3D "pcie0_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake-pins { + pins =3D "gpio96"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins =3D "gpio97"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + clkreq-pins { + pins =3D "gpio98"; + function =3D "pcie1_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake-pins { + pins =3D "gpio99"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio28", "gpio29"; + function =3D "qup1_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio32", "gpio33"; + function =3D "qup1_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio36", "gpio37"; + function =3D "qup1_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio40", "gpio41"; + function =3D "qup1_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio44", "gpio45"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio52", "gpio53"; + function =3D "qup1_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio48", "gpio49"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + scl-pins { + pins =3D "gpio57"; + function =3D "qup2_se0_l1_mira"; + drive-strength =3D <2>; + bias-pull-up; + }; + + sda-pins { + pins =3D "gpio56"; + function =3D "qup2_se0_l0_mira"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio60", "gpio61"; + function =3D "qup2_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio64", "gpio65"; + function =3D "qup2_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio68", "gpio69"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio2", "gpio3"; + function =3D "qup2_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio80", "gpio81"; + function =3D "qup2_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio72", "gpio106"; + function =3D "qup2_se7"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + cs-pins { + pins =3D "gpio31"; + function =3D "qup1_se0"; + }; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio28", "gpio29", "gpio30"; + function =3D "qup1_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins =3D "gpio35"; + function =3D "qup1_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio32", "gpio33", "gpio34"; + function =3D "qup1_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins =3D "gpio39"; + function =3D "qup1_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio36", "gpio37", "gpio38"; + function =3D "qup1_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins =3D "gpio43"; + function =3D "qup1_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio40", "gpio41", "gpio42"; + function =3D "qup1_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins =3D "gpio47"; + function =3D "qup1_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio44", "gpio45", "gpio46"; + function =3D "qup1_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins =3D "gpio55"; + function =3D "qup1_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio52", "gpio53", "gpio54"; + function =3D "qup1_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins =3D "gpio51"; + function =3D "qup1_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio48", "gpio49", "gpio50"; + function =3D "qup1_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins =3D "gpio59"; + function =3D "qup2_se0_l3_mira"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio56", "gpio57", "gpio58"; + function =3D "qup2_se0_l2_mira"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins =3D "gpio63"; + function =3D "qup2_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio60", "gpio61", "gpio62"; + function =3D "qup2_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins =3D "gpio67"; + function =3D "qup2_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio64", "gpio65", "gpio66"; + function =3D "qup2_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins =3D "gpio71"; + function =3D "qup2_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio68", "gpio69", "gpio70"; + function =3D "qup2_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins =3D "gpio119"; + function =3D "qup2_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio2", "gpio3", "gpio118"; + function =3D "qup2_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi13_cs: qup-spi13-cs-state { + pins =3D "gpio83"; + function =3D "qup2_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio80", "gpio81", "gpio82"; + function =3D "qup2_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins =3D "gpio75"; + function =3D "qup2_se7"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio72", "gpio106", "gpio74"; + function =3D "qup2_se7"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart7_default: qup-uart7-default-state { + /* TX, RX */ + pins =3D "gpio26", "gpio27"; + function =3D "qup1_se7"; + drive-strength =3D <2>; + bias-disable; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins =3D "sdc2_clk"; + bias-disable; + drive-strength =3D <2>; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <2>; + }; + + data-pins { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <2>; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins =3D "sdc2_clk"; + bias-disable; + drive-strength =3D <16>; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <10>; + }; + + data-pins { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <10>; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0 0x15000000 0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17100000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0x17100000 0 0x10000>, /* GICD */ + <0 0x17180000 0 0x200000>; /* GICR * 8 */ + ranges; + #interrupt-cells =3D <3>; + interrupt-controller; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0 0x40000>; + interrupts =3D ; + #address-cells =3D <2>; + #size-cells =3D <2>; + + gic_its: msi-controller@17140000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0 0x17140000 0 0x20000>; + msi-controller; + #msi-cells =3D <1>; + }; + }; + + timer@17420000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0 0x17420000 0 0x1000>; + ranges =3D <0 0 0 0x20000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@17421000 { + reg =3D <0x17421000 0x1000>, + <0x17422000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + + frame@17423000 { + reg =3D <0x17423000 0x1000>; + frame-number =3D <1>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17425000 { + reg =3D <0x17425000 0x1000>; + frame-number =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17427000 { + reg =3D <0x17427000 0x1000>; + frame-number =3D <3>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17429000 { + reg =3D <0x17429000 0x1000>; + frame-number =3D <4>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@1742b000 { + reg =3D <0x1742b000 0x1000>; + frame-number =3D <5>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@1742d000 { + reg =3D <0x1742d000 0x1000>; + frame-number =3D <6>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label =3D "apps_rsc"; + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0 0x17a00000 0 0x10000>, + <0 0x17a10000 0 0x10000>, + <0 0x17a20000 0 0x10000>, + <0 0x17a30000 0 0x10000>; + reg-names =3D "drv-0", "drv-1", "drv-2", "drv-3"; + interrupts =3D , + , + ; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , , + , ; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,sm8550-rpmh-clk"; + #clock-cells =3D <1>; + clock-names =3D "xo"; + clocks =3D <&xo_board>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,sm8550-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level =3D ; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible =3D "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; + reg =3D <0 0x17d91000 0 0x1000>, + <0 0x17d92000 0 0x1000>, + <0 0x17d93000 0 0x1000>; + reg-names =3D "freq-domain0", "freq-domain1", "freq-domain2"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + interrupts =3D , + , + ; + interrupt-names =3D "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; + #freq-domain-cells =3D <1>; + }; + + pmu@24091000 { + compatible =3D "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg =3D <0 0x24091000 0 0x1000>; + interrupts =3D ; + interconnects =3D <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; + + operating-points-v2 =3D <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-0 { + opp-peak-kBps =3D <2086000>; + }; + + opp-1 { + opp-peak-kBps =3D <2929000>; + }; + + opp-2 { + opp-peak-kBps =3D <5931000>; + }; + + opp-3 { + opp-peak-kBps =3D <6515000>; + }; + + opp-4 { + opp-peak-kBps =3D <7980000>; + }; + + opp-5 { + opp-peak-kBps =3D <10437000>; + }; + + opp-6 { + opp-peak-kBps =3D <12157000>; + }; + + opp-7 { + opp-peak-kBps =3D <14060000>; + }; + + opp-8 { + opp-peak-kBps =3D <16113000>; + }; + }; + }; + + pmu@240b6400 { + compatible =3D "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon"; + reg =3D <0 0x240b6400 0 0x600>; + interrupts =3D ; + interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; + + operating-points-v2 =3D <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-0 { + opp-peak-kBps =3D <4577000>; + }; + + opp-1 { + opp-peak-kBps =3D <7110000>; + }; + + opp-2 { + opp-peak-kBps =3D <9155000>; + }; + + opp-3 { + opp-peak-kBps =3D <12298000>; + }; + + opp-4 { + opp-peak-kBps =3D <14236000>; + }; + + opp-5 { + opp-peak-kBps =3D <16265000>; + }; + }; + }; + + gem_noc: interconnect@24100000 { + compatible =3D "qcom,sm8550-gem-noc"; + reg =3D <0 0x24100000 0 0xbb800>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system-cache-controller@25000000 { + compatible =3D "qcom,sm8550-llcc"; + reg =3D <0 0x25000000 0 0x800000>, + <0 0x25800000 0 0x200000>; + reg-names =3D "llcc_base", "llcc_broadcast_base"; + interrupts =3D ; + }; + + nsp_noc: interconnect@320c0000 { + compatible =3D "qcom,sm8550-nsp-noc"; + reg =3D <0 0x320c0000 0 0xe080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + }; + + thermal-zones { + aoss0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 0>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 1>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 2>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpuss2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 3>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpuss3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 4>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu3-top-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 5>; + + trips { + cpu3_top_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu3_top_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu3_top_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu3-bottom-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 6>; + + trips { + cpu3_bottom_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu3_bottom_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu3_bottom_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu4-top-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 7>; + + trips { + cpu4_top_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4_top_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4_top_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu4-bottom-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 8>; + + trips { + cpu4_bottom_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4_bottom_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4_bottom_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu5-top-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 9>; + + trips { + cpu5_top_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5_top_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5_top_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu5-bottom-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 10>; + + trips { + cpu5_bottom_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5_bottom_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5_bottom_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu6-top-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 11>; + + trips { + cpu6_top_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6_top_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6_top_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu6-bottom-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 12>; + + trips { + cpu6_bottom_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6_bottom_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6_bottom_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-top-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 13>; + + trips { + cpu7_top_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7_top_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7_top_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-middle-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 14>; + + trips { + cpu7_middle_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7_middle_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7_middle_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-bottom-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 15>; + + trips { + cpu7_bottom_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7_bottom_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7_bottom_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 0>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu0_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu1_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu2_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cdsp0-thermal { + polling-delay-passive =3D <10>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 4>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + thermal-hal-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + cdsp0_junction_config: junction-config { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cdsp1-thermal { + polling-delay-passive =3D <10>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 5>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + thermal-hal-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + cdsp1_junction_config: junction-config { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cdsp2-thermal { + polling-delay-passive =3D <10>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 6>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + thermal-hal-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + cdsp2_junction_config: junction-config { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cdsp3-thermal { + polling-delay-passive =3D <10>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 7>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + thermal-hal-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + cdsp3_junction_config: junction-config { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + video-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 8>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + mem-thermal { + polling-delay-passive =3D <10>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 9>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + ddr_config0: ddr0-config { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 10>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + mdmss0_config0: mdmss0-config0 { + temperature =3D <102000>; + hysteresis =3D <3000>; + type =3D "passive"; + }; + + mdmss0_config1: mdmss0-config1 { + temperature =3D <105000>; + hysteresis =3D <3000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 11>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + mdmss1_config0: mdmss1-config0 { + temperature =3D <102000>; + hysteresis =3D <3000>; + type =3D "passive"; + }; + + mdmss1_config1: mdmss1-config1 { + temperature =3D <105000>; + hysteresis =3D <3000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 12>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + mdmss2_config0: mdmss2-config0 { + temperature =3D <102000>; + hysteresis =3D <3000>; + type =3D "passive"; + }; + + mdmss2_config1: mdmss2-config1 { + temperature =3D <105000>; + hysteresis =3D <3000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + modem3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 13>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + mdmss3_config0: mdmss3-config0 { + temperature =3D <102000>; + hysteresis =3D <3000>; + type =3D "passive"; + }; + + mdmss3_config1: mdmss3-config1 { + temperature =3D <105000>; + hysteresis =3D <3000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + camera0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 14>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + camera1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 15>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + aoss2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 0>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive =3D <10>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 1>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + thermal-hal-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + gpu0_junction_config: junction-config { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive =3D <10>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 2>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + thermal-hal-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + gpu1_junction_config: junction-config { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive =3D <10>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 3>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + thermal-hal-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + gpu2_junction_config: junction-config { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-3-thermal { + polling-delay-passive =3D <10>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 4>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + thermal-hal-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + gpu3_junction_config: junction-config { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-4-thermal { + polling-delay-passive =3D <10>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 5>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + thermal-hal-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + gpu4_junction_config: junction-config { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-5-thermal { + polling-delay-passive =3D <10>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 6>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + thermal-hal-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + gpu5_junction_config: junction-config { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-6-thermal { + polling-delay-passive =3D <10>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 7>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + thermal-hal-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + gpu6_junction_config: junction-config { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-7-thermal { + polling-delay-passive =3D <10>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 8>; + + trips { + thermal-engine-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + thermal-hal-config { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + reset-mon-config { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + gpu7_junction_config: junction-config { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.34.1 From nobody Fri Dec 19 02:49:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF955C63797 for ; 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Fri, 06 Jan 2023 12:10:58 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id z14-20020a05600c220e00b003d99fad7511sm2665240wml.22.2023.01.06.12.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jan 2023 12:10:57 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Neil Armstrong , Dmitry Baryshkov Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v9 03/10] arm64: dts: qcom: Add pm8010 pmic dtsi Date: Fri, 6 Jan 2023 22:10:40 +0200 Message-Id: <20230106201047.337409-4-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106201047.337409-1-abel.vesa@linaro.org> References: <20230106201047.337409-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Neil Armstrong Add nodes for pm8010 in separate dtsi file. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm8010.dtsi | 84 ++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8010.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8010.dtsi b/arch/arm64/boot/dts/qco= m/pm8010.dtsi new file mode 100644 index 000000000000..0ea641e12209 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8010.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pm8010-m-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pm8010_m_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pm8010-n-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pm8010_n_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8010_m: pmic@c { + compatible =3D "qcom,pm8010", "qcom,spmi-pmic"; + reg =3D <0xc SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8010_m_temp_alarm: temp-alarm@2400 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0x2400>; + interrupts =3D <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + }; + + pm8010_n: pmic@d { + compatible =3D "qcom,pm8010", "qcom,spmi-pmic"; + reg =3D <0xd SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8010_n_temp_alarm: temp-alarm@2400 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0x2400>; + interrupts =3D <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + }; +}; --=20 2.34.1 From nobody Fri Dec 19 02:49:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C217CC677F1 for ; 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Fri, 06 Jan 2023 12:10:59 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id z14-20020a05600c220e00b003d99fad7511sm2665240wml.22.2023.01.06.12.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jan 2023 12:10:59 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Neil Armstrong , Dmitry Baryshkov Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v9 04/10] arm64: dts: qcom: Add PM8550 pmic dtsi Date: Fri, 6 Jan 2023 22:10:41 +0200 Message-Id: <20230106201047.337409-5-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106201047.337409-1-abel.vesa@linaro.org> References: <20230106201047.337409-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Neil Armstrong Add nodes for PM8550 in separate dtsi file. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm8550.dtsi | 59 ++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8550.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qco= m/pm8550.dtsi new file mode 100644 index 000000000000..46396ec1a330 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pm8550-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pm8550_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550: pmic@1 { + compatible =3D "qcom,pm8550", "qcom,spmi-pmic"; + reg =3D <0x1 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8550_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pm8550_gpios: gpio@8800 { + compatible =3D "qcom,pm8550-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pm8550_gpios 0 0 12>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; --=20 2.34.1 From nobody Fri Dec 19 02:49:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81498C54EBD for ; Fri, 6 Jan 2023 20:12:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236434AbjAFUM2 (ORCPT ); Fri, 6 Jan 2023 15:12:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236609AbjAFULP (ORCPT ); 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Fri, 06 Jan 2023 12:11:00 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Neil Armstrong , Dmitry Baryshkov Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v9 05/10] arm64: dts: qcom: Add PM8550b pmic dtsi Date: Fri, 6 Jan 2023 22:10:42 +0200 Message-Id: <20230106201047.337409-6-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106201047.337409-1-abel.vesa@linaro.org> References: <20230106201047.337409-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Neil Armstrong Add nodes for PM8550b in separate dtsi file. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm8550b.dtsi | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8550b.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8550b.dtsi b/arch/arm64/boot/dts/qc= om/pm8550b.dtsi new file mode 100644 index 000000000000..16bcfb64d735 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550b.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pm8550b-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pm8550b_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550b: pmic@7 { + compatible =3D "qcom,pm8550", "qcom,spmi-pmic"; + reg =3D <0x7 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8550b_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pm8550b_gpios: gpio@8800 { + compatible =3D "qcom,pm8550b-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pm8550b_gpios 0 0 12>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; --=20 2.34.1 From nobody Fri Dec 19 02:49:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A276C63707 for ; Fri, 6 Jan 2023 20:12:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236832AbjAFUMS (ORCPT ); Fri, 6 Jan 2023 15:12:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236590AbjAFULP (ORCPT ); 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Fri, 06 Jan 2023 12:11:01 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Neil Armstrong , Dmitry Baryshkov Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v9 06/10] arm64: dts: qcom: Add PM8550ve pmic dtsi Date: Fri, 6 Jan 2023 22:10:43 +0200 Message-Id: <20230106201047.337409-7-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106201047.337409-1-abel.vesa@linaro.org> References: <20230106201047.337409-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Neil Armstrong Add nodes for PM8550ve in separate dtsi file. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm8550ve.dtsi | 59 ++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8550ve.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi b/arch/arm64/boot/dts/q= com/pm8550ve.dtsi new file mode 100644 index 000000000000..c47646a467be --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pm8550ve-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pm8550ve_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550ve: pmic@5 { + compatible =3D "qcom,pm8550", "qcom,spmi-pmic"; + reg =3D <0x5 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8550ve_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pm8550ve_gpios: gpio@8800 { + compatible =3D "qcom,pm8550ve-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pm8550ve_gpios 0 0 8>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; --=20 2.34.1 From nobody Fri Dec 19 02:49:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A922BC6379F for ; Fri, 6 Jan 2023 20:12:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236856AbjAFUMX (ORCPT ); Fri, 6 Jan 2023 15:12:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236614AbjAFULP (ORCPT ); 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Fri, 06 Jan 2023 12:11:02 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Neil Armstrong , Dmitry Baryshkov Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v9 07/10] arm64: dts: qcom: Add PM8550vs pmic dtsi Date: Fri, 6 Jan 2023 22:10:44 +0200 Message-Id: <20230106201047.337409-8-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106201047.337409-1-abel.vesa@linaro.org> References: <20230106201047.337409-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Neil Armstrong Add nodes for PM8550vs in separate dtsi file. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 194 +++++++++++++++++++++++++ 1 file changed, 194 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8550vs.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/q= com/pm8550vs.dtsi new file mode 100644 index 000000000000..97b1c18aa7d8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pm8550vs-c-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pm8550vs_c_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pm8550vs-d-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pm8550vs_d_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pm8550vs-e-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pm8550vs_e_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pm8550vs-g-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pm8550vs_g_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550vs_c: pmic@2 { + compatible =3D "qcom,pm8550", "qcom,spmi-pmic"; + reg =3D <0x2 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8550vs_c_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pm8550vs_c_gpios: gpio@8800 { + compatible =3D "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pm8550vs_c_gpios 0 0 6>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pm8550vs_d: pmic@3 { + compatible =3D "qcom,pm8550", "qcom,spmi-pmic"; + reg =3D <0x3 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8550vs_d_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pm8550vs_d_gpios: gpio@8800 { + compatible =3D "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pm8550vs_d_gpios 0 0 6>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pm8550vs_e: pmic@4 { + compatible =3D "qcom,pm8550", "qcom,spmi-pmic"; + reg =3D <0x4 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8550vs_e_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pm8550vs_e_gpios: gpio@8800 { + compatible =3D "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pm8550vs_e_gpios 0 0 6>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pm8550vs_g: pmic@6 { + compatible =3D "qcom,pm8550", "qcom,spmi-pmic"; + reg =3D <0x6 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8550vs_g_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pm8550vs_g_gpios: gpio@8800 { + compatible =3D "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pm8550vs_g_gpios 0 0 6>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; --=20 2.34.1 From nobody Fri Dec 19 02:49:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B439C3DA7A for ; Fri, 6 Jan 2023 20:12:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235738AbjAFUMO (ORCPT ); Fri, 6 Jan 2023 15:12:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236595AbjAFULP (ORCPT ); Fri, 6 Jan 2023 15:11:15 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D72C7FEEB for ; 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charset="utf-8" From: Neil Armstrong Add nodes for PMK8550 in separate dtsi file. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pmk8550.dtsi | 55 +++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmk8550.dtsi diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qc= om/pmk8550.dtsi new file mode 100644 index 000000000000..47213d05bf92 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include + +&spmi_bus { + pmk8550: pmic@0 { + compatible =3D "qcom,pm8550", "qcom,spmi-pmic"; + reg =3D <0x0 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmk8550_pon: pon@1300 { + compatible =3D "qcom,pm8998-pon"; + reg =3D <0x1300>, <0x800>; + reg-names =3D "hlos", "pbs"; + + pon_pwrkey: pwrkey { + compatible =3D "qcom,pmk8350-pwrkey"; + interrupts =3D <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code =3D ; + status =3D "disabled"; + }; + + pon_resin: resin { + compatible =3D "qcom,pmk8350-resin"; + interrupts =3D <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status =3D "disabled"; + }; + }; + + pmk8550_rtc: rtc@6100 { + compatible =3D "qcom,pmk8350-rtc"; + reg =3D <0x6100>, <0x6200>; + reg-names =3D "rtc", "alarm"; + interrupts =3D <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + status =3D "disabled"; + }; + + pmk8550_gpios: gpio@8800 { + compatible =3D "qcom,pmk8550-gpio", "qcom,spmi-gpio"; + reg =3D <0xb800>; + gpio-controller; + gpio-ranges =3D <&pmk8550_gpios 0 0 6>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; --=20 2.34.1 From nobody Fri Dec 19 02:49:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62A22C54EBD for ; Fri, 6 Jan 2023 20:12:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236546AbjAFUMg (ORCPT ); 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Fri, 06 Jan 2023 12:11:05 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Neil Armstrong , Dmitry Baryshkov Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v9 09/10] arm64: dts: qcom: Add PMR735d pmic dtsi Date: Fri, 6 Jan 2023 22:10:46 +0200 Message-Id: <20230106201047.337409-10-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106201047.337409-1-abel.vesa@linaro.org> References: <20230106201047.337409-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Neil Armstrong Add nodes for PMR735d in separate dtsi file. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pmr735d.dtsi | 104 ++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmr735d.dtsi diff --git a/arch/arm64/boot/dts/qcom/pmr735d.dtsi b/arch/arm64/boot/dts/qc= om/pmr735d.dtsi new file mode 100644 index 000000000000..41fb664a10b3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmr735d.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pmr735d-k-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pmr735d_k_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pmr735d-l-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pmr735d_l_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pmr735d_k: pmic@a { + compatible =3D "qcom,pmr735d", "qcom,spmi-pmic"; + reg =3D <0xa SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmr735d_k_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmr735d_k_gpios: gpio@8800 { + compatible =3D "qcom,pmr735d-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmr735d_k_gpios 0 0 2>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmr735d_l: pmic@b { + compatible =3D "qcom,pmr735d", "qcom,spmi-pmic"; + reg =3D <0xb SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmr735d_l_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0xb 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmr735d_l_gpios: gpio@8800 { + compatible =3D "qcom,pmr735d-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmr735d_l_gpios 0 0 2>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; --=20 2.34.1 From nobody Fri Dec 19 02:49:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38085C3DA7A for ; Fri, 6 Jan 2023 20:12:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236600AbjAFUMj (ORCPT ); Fri, 6 Jan 2023 15:12:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236660AbjAFULQ (ORCPT ); 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Fri, 06 Jan 2023 12:11:06 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Neil Armstrong , Dmitry Baryshkov Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v9 10/10] arm64: dts: qcom: Add base SM8550 MTP dts Date: Fri, 6 Jan 2023 22:10:47 +0200 Message-Id: <20230106201047.337409-11-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106201047.337409-1-abel.vesa@linaro.org> References: <20230106201047.337409-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dts file for Qualcomm MTP platform which uses SM8550 SoC. Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 404 ++++++++++++++++++++++++ 2 files changed, 405 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8550-mtp.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 3e79496292e7..13d8466b5445 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -178,3 +178,4 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sm8450-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8450-sony-xperia-nagara-pdx223.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8450-sony-xperia-nagara-pdx224.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sm8550-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8550-mtp.dts new file mode 100644 index 000000000000..8586e16d6079 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include +#include "sm8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +#include "pmr735d.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. SM8550 MTP"; + compatible =3D "qcom,sm8550-mtp", "qcom,sm8550"; + + aliases { + serial0 =3D &uart7; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l3-supply =3D <&vreg_s4g_1p3>; + vdd-l6-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob1>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l11-supply =3D <&vreg_s4g_1p3>; + vdd-l12-supply =3D <&vreg_s6g_1p8>; + vdd-l15-supply =3D <&vreg_s6g_1p8>; + vdd-l17-supply =3D <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2720000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name =3D "vreg_l1b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <3104000>; + regulator-max-microvolt =3D <3104000>; + regulator-initial-mode =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name =3D "vreg_l7b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name =3D "vreg_l8b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name =3D "vreg_l11b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1504000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name =3D "vreg_l12b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name =3D "vreg_l14b_3p2"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name =3D "vreg_l16b_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-l3-supply =3D <&vreg_s4e_0p9>; + + vreg_l3c_0p91: ldo3 { + regulator-name =3D "vreg_l3c_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-supply =3D <&vreg_s4e_0p9>; + + vreg_l1d_0p88: ldo1 { + regulator-name =3D "vreg_l1d_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vdd-l1-supply =3D <&vreg_s4e_0p9>; + vdd-l2-supply =3D <&vreg_s4e_0p9>; + vdd-l3-supply =3D <&vreg_s4g_1p3>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + + vreg_s4e_0p9: smps4 { + regulator-name =3D "vreg_s4e_0p9"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <984000>; + regulator-initial-mode =3D ; + }; + + vreg_s5e_1p1: smps5 { + regulator-name =3D "vreg_s5e_1p1"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1120000>; + regulator-initial-mode =3D ; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name =3D "vreg_l1e_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name =3D "vreg_l2e_0p9"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name =3D "vreg_l3e_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "f"; + + vdd-l1-supply =3D <&vreg_s4e_0p9>; + vdd-l2-supply =3D <&vreg_s4e_0p9>; + vdd-l3-supply =3D <&vreg_s4e_0p9>; + vdd-s4-supply =3D <&vph_pwr>; + + vreg_s4f_0p5: smps4 { + regulator-name =3D "vreg_s4f_0p5"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <700000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name =3D "vreg_l1f_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name =3D "vreg_l2f_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l3f_0p91: ldo3 { + regulator-name =3D "vreg_l3f_0p91"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-5 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "g"; + + vdd-l1-supply =3D <&vreg_s4g_1p3>; + vdd-l2-supply =3D <&vreg_s4g_1p3>; + vdd-l3-supply =3D <&vreg_s4g_1p3>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + vreg_s1g_1p2: smps1 { + regulator-name =3D "vreg_s1g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + }; + + vreg_s2g_0p8: smps2 { + regulator-name =3D "vreg_s2g_0p8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + }; + + vreg_s3g_0p7: smps3 { + regulator-name =3D "vreg_s3g_0p7"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_s4g_1p3: smps4 { + regulator-name =3D "vreg_s4g_1p3"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1352000>; + regulator-initial-mode =3D ; + }; + + vreg_s5g_0p8: smps5 { + regulator-name =3D "vreg_s5g_0p8"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_s6g_1p8: smps6 { + regulator-name =3D "vreg_s6g_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name =3D "vreg_l1g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l2g_1p2: ldo2 { + regulator-name =3D "vreg_l2g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name =3D "vreg_l3g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&pm8550_gpios { + sdc2_card_det_n: sdc2-card-det-state { + pins =3D "gpio12"; + function =3D "normal"; + input-enable; + output-disable; + bias-pull-up; + power-source =3D <1>; /* 1.8 V */ + }; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 =3D <&sdc2_sleep &sdc2_card_det_n>; + vmmc-supply =3D <&vreg_l9b_2p9>; + vqmmc-supply =3D <&vreg_l8b_1p8>; + bus-width =3D <4>; + no-sdio; + no-mmc; + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&tlmm { + gpio-reserved-ranges =3D <32 8>; +}; + +&uart7 { + status =3D "okay"; +}; + +&xo_board { + clock-frequency =3D <76800000>; +}; --=20 2.34.1