From nobody Tue Sep 16 07:17:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 522ACC53210 for ; Fri, 6 Jan 2023 01:04:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234584AbjAFBEA (ORCPT ); Thu, 5 Jan 2023 20:04:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236444AbjAFBDw (ORCPT ); Thu, 5 Jan 2023 20:03:52 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C86EB5F4A7; Thu, 5 Jan 2023 17:03:51 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 55B0612FC; Thu, 5 Jan 2023 17:04:33 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 000253F23F; Thu, 5 Jan 2023 17:03:48 -0800 (PST) From: Andre Przywara To: Samuel Holland , Jernej Skrabec , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski Cc: Icenowy Zheng , =?UTF-8?q?Andr=C3=A1s=20Szemz=C3=B6?= , Fabien Poussin , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Frank Rowand Subject: [PATCH 1/4] dts: add riscv include prefix link Date: Fri, 6 Jan 2023 01:01:52 +0000 Message-Id: <20230106010155.26868-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.5 In-Reply-To: <20230106010155.26868-1-andre.przywara@arm.com> References: <20230106010155.26868-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical die as their R528/T113-s siblings with ARM Cortex-A7 cores. To allow sharing the basic SoC .dtsi files across those two architectures as well, introduce a symlink to the RISC-V DT directory. Signed-off-by: Andre Przywara Acked-by: Palmer Dabbelt Reviewed-by: Conor Dooley --- scripts/dtc/include-prefixes/riscv | 1 + 1 file changed, 1 insertion(+) create mode 120000 scripts/dtc/include-prefixes/riscv diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefi= xes/riscv new file mode 120000 index 0000000000000..2025094189380 --- /dev/null +++ b/scripts/dtc/include-prefixes/riscv @@ -0,0 +1 @@ +../../../arch/riscv/boot/dts \ No newline at end of file --=20 2.35.5