From nobody Tue Sep 16 04:56:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EF96C3DA7A for ; Thu, 5 Jan 2023 18:04:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235470AbjAESEA (ORCPT ); Thu, 5 Jan 2023 13:04:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235053AbjAESDt (ORCPT ); Thu, 5 Jan 2023 13:03:49 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4321C564D1; Thu, 5 Jan 2023 10:03:46 -0800 (PST) Received: from jupiter.universe (dyndsl-085-016-198-020.ewe-ip-backbone.de [85.16.198.20]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 425D86602CA6; Thu, 5 Jan 2023 18:03:45 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1672941825; bh=Eit57BSuLLiRFOU6myIJto2e9A9VEfM0WBizgrQT8yc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TCMwnIV2hWgSnZDyenJ47ozEXjmCBJyGuEY+enk/AaIe17xPaSIZBk2PFzjZCb6UN r2W1Z0qS5rNWgM/iWrV9AIe+oCXCxPOK+Yyf5ywoPBP4uezkq029c3fc4tm1C+zeRp GBN1LAuHmS0EIzBEpLaTkjEAoV1kQH87RcsVQRThLXY5+pIecALH1oY76CxqeebjhH UyTthQriDPZyhoNxW9tf9h3nrZrd49TBJYrtRdGI9ZT+zWSHG9mqepJFrsFqhUqe49 8nckB0mLM572zFZhZbBbOn4w9Tdkl7AZNdNgcrZdeSmrkb0Fffv/kpifSwEOSyY8QQ Y7lKf90bleAqw== Received: by jupiter.universe (Postfix, from userid 1000) id A39FE480118; Thu, 5 Jan 2023 19:03:42 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner , "Rafael J. Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCHv3 1/7] thermal: rockchip: Simplify getting match data Date: Thu, 5 Jan 2023 19:03:34 +0100 Message-Id: <20230105180340.29140-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105180340.29140-1-sebastian.reichel@collabora.com> References: <20230105180340.29140-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It's possible to directly get the match data in a generic way nowadays. Reviewed-by: Heiko Stuebner Signed-off-by: Sebastian Reichel --- drivers/thermal/rockchip_thermal.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_= thermal.c index 819e059cde71..8c52700d58e8 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -1353,16 +1353,11 @@ static int rockchip_thermal_probe(struct platform_d= evice *pdev) { struct device_node *np =3D pdev->dev.of_node; struct rockchip_thermal_data *thermal; - const struct of_device_id *match; struct resource *res; int irq; int i; int error; =20 - match =3D of_match_node(of_rockchip_thermal_match, np); - if (!match) - return -ENXIO; - irq =3D platform_get_irq(pdev, 0); if (irq < 0) return -EINVAL; @@ -1374,7 +1369,7 @@ static int rockchip_thermal_probe(struct platform_dev= ice *pdev) =20 thermal->pdev =3D pdev; =20 - thermal->chip =3D (const struct rockchip_tsadc_chip *)match->data; + thermal->chip =3D device_get_match_data(&pdev->dev); if (!thermal->chip) return -EINVAL; =20 --=20 2.39.0 From nobody Tue Sep 16 04:56:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A493C54EBE for ; Thu, 5 Jan 2023 18:03:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235457AbjAESDx (ORCPT ); Thu, 5 Jan 2023 13:03:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230015AbjAESDs (ORCPT ); Thu, 5 Jan 2023 13:03:48 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43106564CB; Thu, 5 Jan 2023 10:03:47 -0800 (PST) Received: from jupiter.universe (dyndsl-085-016-198-020.ewe-ip-backbone.de [85.16.198.20]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 49DD46602CCE; Thu, 5 Jan 2023 18:03:45 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1672941825; bh=xIMSW4AOlAHM6XznKwVJh8dNalSiPuEcNwEAA+jCX+Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ARcEhpNhY8IjBHP1mZiLKhnqOgnoKS1kPMfjbrZixL0pJ13OycZhhxh8Ctc6eQAE5 soGLACoxLgOJZ3n+9Pl//W7Rz46EPVWcFNrftD2asguPWfhBn9hcTiul8ZOClVJCux lzvxPvb81YcdDhg3r+fL65mP/xI7/KFnBKUL2TaORQ6ivQlyO/mnRFy9Ov+/Fh02LD rSktOEczDffayNaMzST6/Wxf9LPIngjXFEgsIlx9JRBYOzpEm49EzZMJy1uzlDLqy2 XaZcyWpDt4VmpcJbN5AFHQBwr9Wjv9AEr93cR95bYFiVUNIlA41ZtfGCuXyv1RJEEm h0XTt4o9DLSrw== Received: by jupiter.universe (Postfix, from userid 1000) id A6CFF480119; Thu, 5 Jan 2023 19:03:42 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner , "Rafael J. Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCHv3 2/7] thermal: rockchip: Simplify clock logic Date: Thu, 5 Jan 2023 19:03:35 +0100 Message-Id: <20230105180340.29140-3-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105180340.29140-1-sebastian.reichel@collabora.com> References: <20230105180340.29140-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" By using devm_clk_get_enabled() the clock acquisition and enabling can be done in one step with automatic error handling. Reviewed-by: Heiko Stuebner Signed-off-by: Sebastian Reichel --- drivers/thermal/rockchip_thermal.c | 33 +++++------------------------- 1 file changed, 5 insertions(+), 28 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_= thermal.c index 8c52700d58e8..74e0ad001b33 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -1385,14 +1385,14 @@ static int rockchip_thermal_probe(struct platform_d= evice *pdev) return error; } =20 - thermal->clk =3D devm_clk_get(&pdev->dev, "tsadc"); + thermal->clk =3D devm_clk_get_enabled(&pdev->dev, "tsadc"); if (IS_ERR(thermal->clk)) { error =3D PTR_ERR(thermal->clk); dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); return error; } =20 - thermal->pclk =3D devm_clk_get(&pdev->dev, "apb_pclk"); + thermal->pclk =3D devm_clk_get_enabled(&pdev->dev, "apb_pclk"); if (IS_ERR(thermal->pclk)) { error =3D PTR_ERR(thermal->pclk); dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", @@ -1400,26 +1400,13 @@ static int rockchip_thermal_probe(struct platform_d= evice *pdev) return error; } =20 - error =3D clk_prepare_enable(thermal->clk); - if (error) { - dev_err(&pdev->dev, "failed to enable converter clock: %d\n", - error); - return error; - } - - error =3D clk_prepare_enable(thermal->pclk); - if (error) { - dev_err(&pdev->dev, "failed to enable pclk: %d\n", error); - goto err_disable_clk; - } - rockchip_thermal_reset_controller(thermal->reset); =20 error =3D rockchip_configure_from_dt(&pdev->dev, np, thermal); if (error) { dev_err(&pdev->dev, "failed to parse device tree data: %d\n", error); - goto err_disable_pclk; + return error; } =20 thermal->chip->initialize(thermal->grf, thermal->regs, @@ -1433,7 +1420,7 @@ static int rockchip_thermal_probe(struct platform_dev= ice *pdev) dev_err(&pdev->dev, "failed to register sensor[%d] : error =3D %d\n", i, error); - goto err_disable_pclk; + return error; } } =20 @@ -1444,7 +1431,7 @@ static int rockchip_thermal_probe(struct platform_dev= ice *pdev) if (error) { dev_err(&pdev->dev, "failed to request tsadc irq: %d\n", error); - goto err_disable_pclk; + return error; } =20 thermal->chip->control(thermal->regs, true); @@ -1462,13 +1449,6 @@ static int rockchip_thermal_probe(struct platform_de= vice *pdev) platform_set_drvdata(pdev, thermal); =20 return 0; - -err_disable_pclk: - clk_disable_unprepare(thermal->pclk); -err_disable_clk: - clk_disable_unprepare(thermal->clk); - - return error; } =20 static int rockchip_thermal_remove(struct platform_device *pdev) @@ -1485,9 +1465,6 @@ static int rockchip_thermal_remove(struct platform_de= vice *pdev) =20 thermal->chip->control(thermal->regs, false); =20 - clk_disable_unprepare(thermal->pclk); - clk_disable_unprepare(thermal->clk); - return 0; } =20 --=20 2.39.0 From nobody Tue Sep 16 04:56:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3213C3DA7D for ; Thu, 5 Jan 2023 18:04:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235455AbjAESEE (ORCPT ); Thu, 5 Jan 2023 13:04:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234788AbjAESDt (ORCPT ); Thu, 5 Jan 2023 13:03:49 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43045564CA; Thu, 5 Jan 2023 10:03:46 -0800 (PST) Received: from jupiter.universe (dyndsl-085-016-198-020.ewe-ip-backbone.de [85.16.198.20]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5D3706602CD7; Thu, 5 Jan 2023 18:03:45 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1672941825; bh=sbwbPC8CQ9pDo6+I6EbaGiqJManEPRlNV8KKXl/kDSc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gls4Mzv+c+/KPrDmXnys6tTry4Su9e0SSucEF8h5b0l+nTCgBykn2cy3CgnB8Rt3k Z5MUAGSHGjuIdLQQVRCCYMz6xMaKkKnIe6r59dm9pw+0a+gkXniPNJxeJ2YCiMLnq+ NUqrKIsBmPtcc3LNfryQsEpghqRSCzHAF5lo3OtjSsun3VOQ85XTJs2LVYLgrnxlW4 fIRIVi4MRORbXxW/UWVQ1apH1nqRBsTeu26Xn+NWAzaJahOd0Z42Q1E/qu5EjZaxlP QrNIFCgEPh6YpP7UDOD2ognfztesuKzM+OmD7DIoX0QVml7sv6Z+4NjuM27kXsF5ZC v1UzEf3wL9/wA== Received: by jupiter.universe (Postfix, from userid 1000) id A800848011A; Thu, 5 Jan 2023 19:03:42 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner , "Rafael J. Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCHv3 3/7] thermal: rockchip: Use dev_err_probe Date: Thu, 5 Jan 2023 19:03:36 +0100 Message-Id: <20230105180340.29140-4-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105180340.29140-1-sebastian.reichel@collabora.com> References: <20230105180340.29140-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use dev_err_probe to simplify error printing in the driver's probe routine. Reviewed-by: Heiko Stuebner Signed-off-by: Sebastian Reichel --- drivers/thermal/rockchip_thermal.c | 50 +++++++++++------------------- 1 file changed, 18 insertions(+), 32 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_= thermal.c index 74e0ad001b33..0670584533a5 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -1379,35 +1379,26 @@ static int rockchip_thermal_probe(struct platform_d= evice *pdev) return PTR_ERR(thermal->regs); =20 thermal->reset =3D devm_reset_control_array_get(&pdev->dev, false, false); - if (IS_ERR(thermal->reset)) { - error =3D PTR_ERR(thermal->reset); - dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); - return error; - } + if (IS_ERR(thermal->reset)) + return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset), + "failed to get tsadc reset.\n"); =20 thermal->clk =3D devm_clk_get_enabled(&pdev->dev, "tsadc"); - if (IS_ERR(thermal->clk)) { - error =3D PTR_ERR(thermal->clk); - dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); - return error; - } + if (IS_ERR(thermal->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(thermal->clk), + "failed to get tsadc clock.\n"); =20 thermal->pclk =3D devm_clk_get_enabled(&pdev->dev, "apb_pclk"); - if (IS_ERR(thermal->pclk)) { - error =3D PTR_ERR(thermal->pclk); - dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", - error); - return error; - } + if (IS_ERR(thermal->pclk)) + return dev_err_probe(&pdev->dev, PTR_ERR(thermal->pclk), + "failed to get apb_pclk clock.\n"); =20 rockchip_thermal_reset_controller(thermal->reset); =20 error =3D rockchip_configure_from_dt(&pdev->dev, np, thermal); - if (error) { - dev_err(&pdev->dev, "failed to parse device tree data: %d\n", - error); - return error; - } + if (error) + return dev_err_probe(&pdev->dev, error, + "failed to parse device tree data\n"); =20 thermal->chip->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity); @@ -1416,23 +1407,18 @@ static int rockchip_thermal_probe(struct platform_d= evice *pdev) error =3D rockchip_thermal_register_sensor(pdev, thermal, &thermal->sensors[i], thermal->chip->chn_id[i]); - if (error) { - dev_err(&pdev->dev, - "failed to register sensor[%d] : error =3D %d\n", - i, error); - return error; - } + if (error) + return dev_err_probe(&pdev->dev, error, + "failed to register sensor[%d].\n", i); } =20 error =3D devm_request_threaded_irq(&pdev->dev, irq, NULL, &rockchip_thermal_alarm_irq_thread, IRQF_ONESHOT, "rockchip_thermal", thermal); - if (error) { - dev_err(&pdev->dev, - "failed to request tsadc irq: %d\n", error); - return error; - } + if (error) + return dev_err_probe(&pdev->dev, error, + "failed to request tsadc irq.\n"); =20 thermal->chip->control(thermal->regs, true); =20 --=20 2.39.0 From nobody Tue Sep 16 04:56:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25077C4708E for ; Thu, 5 Jan 2023 18:04:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235531AbjAESEH (ORCPT ); Thu, 5 Jan 2023 13:04:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234822AbjAESDt (ORCPT ); Thu, 5 Jan 2023 13:03:49 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43159564D0; Thu, 5 Jan 2023 10:03:47 -0800 (PST) Received: from jupiter.universe (dyndsl-085-016-198-020.ewe-ip-backbone.de [85.16.198.20]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 685C06602D31; Thu, 5 Jan 2023 18:03:45 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1672941825; bh=mHh80L5ElPr39w1k3P2HJAsFvlLLjnNTUVP+BBbonS4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jPiRG+FK7BIKmHxxliBSQ5KVTX8SlArJTKNKalscLlSNPZlsJN6Z+YQbLweNhq8+t lKH5F/XEKa4SWXIczxf8UL85t4zUAxvdpx9/lQGkaT/scS/NOpOYRgszbW2MTi4Nbd op16fXQ74lzl60QaMUMsXFyyw40jziXUYnzDRSC9HdPSIWnQHXdUykAUfNhPFJ+Dhu sEkIEY3bfVB5FJxWFdD2jxMCjVRbnVJg4zl7Y7dZ01gHmbdNsBOLZr85jBu53pjT8V qqbv4sxy+7HeyO+mSaCY6KGmbV631Mw8R6DU5u4oFoTcxWhieLaW/oRRJGnBmtCl1h KpmdxJXpDKdTQ== Received: by jupiter.universe (Postfix, from userid 1000) id A9EAC48011B; Thu, 5 Jan 2023 19:03:42 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner , "Rafael J. Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCHv3 4/7] thermal: rockchip: Simplify channel id logic Date: Thu, 5 Jan 2023 19:03:37 +0100 Message-Id: <20230105180340.29140-5-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105180340.29140-1-sebastian.reichel@collabora.com> References: <20230105180340.29140-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Replace the channel ID lookup table by a simple offset, since the channel IDs are consecutive. Signed-off-by: Sebastian Reichel --- drivers/thermal/rockchip_thermal.c | 48 +++++++++++++----------------- 1 file changed, 21 insertions(+), 27 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_= thermal.c index 0670584533a5..2c8a8b365c80 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -39,15 +39,6 @@ enum tshut_polarity { TSHUT_HIGH_ACTIVE, }; =20 -/* - * The system has two Temperature Sensors. - * sensor0 is for CPU, and sensor1 is for GPU. - */ -enum sensor_id { - SENSOR_CPU =3D 0, - SENSOR_GPU, -}; - /* * The conversion table has the adc value and temperature. * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) @@ -82,7 +73,7 @@ struct chip_tsadc_table { =20 /** * struct rockchip_tsadc_chip - hold the private data of tsadc chip - * @chn_id: array of sensor ids of chip corresponding to the channel + * @chn_offset: the channel offset of the first channel * @chn_num: the channel number of tsadc chip * @tshut_temp: the hardware-controlled shutdown temperature value * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) @@ -98,7 +89,7 @@ struct chip_tsadc_table { */ struct rockchip_tsadc_chip { /* The sensor id of chip correspond to the ADC channel */ - int chn_id[SOC_MAX_SENSORS]; + int chn_offset; int chn_num; =20 /* The hardware-controlled tshut property */ @@ -925,8 +916,8 @@ static void rk_tsadcv2_tshut_mode(int chn, void __iomem= *regs, } =20 static const struct rockchip_tsadc_chip px30_tsadc_data =3D { - .chn_id[SENSOR_CPU] =3D 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] =3D 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset =3D 0, .chn_num =3D 2, /* 2 channels for tsadc */ =20 .tshut_mode =3D TSHUT_MODE_CRU, /* default TSHUT via CRU */ @@ -949,7 +940,8 @@ static const struct rockchip_tsadc_chip px30_tsadc_data= =3D { }; =20 static const struct rockchip_tsadc_chip rv1108_tsadc_data =3D { - .chn_id[SENSOR_CPU] =3D 0, /* cpu sensor is channel 0 */ + /* cpu */ + .chn_offset =3D 0, .chn_num =3D 1, /* one channel for tsadc */ =20 .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -973,7 +965,8 @@ static const struct rockchip_tsadc_chip rv1108_tsadc_da= ta =3D { }; =20 static const struct rockchip_tsadc_chip rk3228_tsadc_data =3D { - .chn_id[SENSOR_CPU] =3D 0, /* cpu sensor is channel 0 */ + /* cpu */ + .chn_offset =3D 0, .chn_num =3D 1, /* one channel for tsadc */ =20 .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -997,8 +990,8 @@ static const struct rockchip_tsadc_chip rk3228_tsadc_da= ta =3D { }; =20 static const struct rockchip_tsadc_chip rk3288_tsadc_data =3D { - .chn_id[SENSOR_CPU] =3D 1, /* cpu sensor is channel 1 */ - .chn_id[SENSOR_GPU] =3D 2, /* gpu sensor is channel 2 */ + /* cpu, gpu */ + .chn_offset =3D 1, .chn_num =3D 2, /* two channels for tsadc */ =20 .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1022,7 +1015,8 @@ static const struct rockchip_tsadc_chip rk3288_tsadc_= data =3D { }; =20 static const struct rockchip_tsadc_chip rk3328_tsadc_data =3D { - .chn_id[SENSOR_CPU] =3D 0, /* cpu sensor is channel 0 */ + /* cpu */ + .chn_offset =3D 0, .chn_num =3D 1, /* one channels for tsadc */ =20 .tshut_mode =3D TSHUT_MODE_CRU, /* default TSHUT via CRU */ @@ -1045,8 +1039,8 @@ static const struct rockchip_tsadc_chip rk3328_tsadc_= data =3D { }; =20 static const struct rockchip_tsadc_chip rk3366_tsadc_data =3D { - .chn_id[SENSOR_CPU] =3D 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] =3D 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset =3D 0, .chn_num =3D 2, /* two channels for tsadc */ =20 .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1070,8 +1064,8 @@ static const struct rockchip_tsadc_chip rk3366_tsadc_= data =3D { }; =20 static const struct rockchip_tsadc_chip rk3368_tsadc_data =3D { - .chn_id[SENSOR_CPU] =3D 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] =3D 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset =3D 0, .chn_num =3D 2, /* two channels for tsadc */ =20 .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1095,8 +1089,8 @@ static const struct rockchip_tsadc_chip rk3368_tsadc_= data =3D { }; =20 static const struct rockchip_tsadc_chip rk3399_tsadc_data =3D { - .chn_id[SENSOR_CPU] =3D 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] =3D 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset =3D 0, .chn_num =3D 2, /* two channels for tsadc */ =20 .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1120,8 +1114,8 @@ static const struct rockchip_tsadc_chip rk3399_tsadc_= data =3D { }; =20 static const struct rockchip_tsadc_chip rk3568_tsadc_data =3D { - .chn_id[SENSOR_CPU] =3D 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] =3D 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset =3D 0, .chn_num =3D 2, /* two channels for tsadc */ =20 .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1406,7 +1400,7 @@ static int rockchip_thermal_probe(struct platform_dev= ice *pdev) for (i =3D 0; i < thermal->chip->chn_num; i++) { error =3D rockchip_thermal_register_sensor(pdev, thermal, &thermal->sensors[i], - thermal->chip->chn_id[i]); + thermal->chip->chn_offset + i); if (error) return dev_err_probe(&pdev->dev, error, "failed to register sensor[%d].\n", i); --=20 2.39.0 From nobody Tue Sep 16 04:56:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BEB9C4708E for ; Thu, 5 Jan 2023 18:04:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235544AbjAESEP (ORCPT ); Thu, 5 Jan 2023 13:04:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235443AbjAESDv (ORCPT ); Thu, 5 Jan 2023 13:03:51 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 561FC564E0; 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Thu, 5 Jan 2023 19:03:42 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner , "Rafael J. Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCHv3 5/7] thermal: rockchip: Support dynamic sized sensor array Date: Thu, 5 Jan 2023 19:03:38 +0100 Message-Id: <20230105180340.29140-6-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105180340.29140-1-sebastian.reichel@collabora.com> References: <20230105180340.29140-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Dynamically allocate the sensors array based on the amount of platform sensors in preparation for rk3588 support, which needs 7 sensors. Reviewed-by: Heiko Stuebner Signed-off-by: Sebastian Reichel --- drivers/thermal/rockchip_thermal.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_= thermal.c index 2c8a8b365c80..c104c60faafd 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -51,12 +51,6 @@ enum adc_sort_mode { =20 #include "thermal_hwmon.h" =20 -/** - * The max sensors is two in rockchip SoCs. - * Two sensors: CPU and GPU sensor. - */ -#define SOC_MAX_SENSORS 2 - /** * struct chip_tsadc_table - hold information about chip-specific differen= ces * @id: conversion table @@ -147,7 +141,7 @@ struct rockchip_thermal_data { struct platform_device *pdev; struct reset_control *reset; =20 - struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS]; + struct rockchip_thermal_sensor *sensors; =20 struct clk *clk; struct clk *pclk; @@ -1367,6 +1361,11 @@ static int rockchip_thermal_probe(struct platform_de= vice *pdev) if (!thermal->chip) return -EINVAL; =20 + thermal->sensors =3D devm_kcalloc(&pdev->dev, thermal->chip->chn_num, + sizeof(*thermal->sensors), GFP_KERNEL); + if (!thermal->sensors) + return -ENOMEM; + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); thermal->regs =3D devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(thermal->regs)) --=20 2.39.0 From nobody Tue Sep 16 04:56:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35B6EC4708E for ; Thu, 5 Jan 2023 18:04:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234692AbjAESEL (ORCPT ); Thu, 5 Jan 2023 13:04:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235400AbjAESDu (ORCPT ); Thu, 5 Jan 2023 13:03:50 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 545BA564DE; Thu, 5 Jan 2023 10:03:49 -0800 (PST) Received: from jupiter.universe (dyndsl-085-016-198-020.ewe-ip-backbone.de [85.16.198.20]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id D88F26602D3C; Thu, 5 Jan 2023 18:03:47 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1672941828; bh=lTGrwZPjeKQ4ku1FY34DkLAoLXnDqkhLQCLk/igV0sM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MYmsswZvebBj63R6KxbuosFFnxjYMTOdcgGoN0RCpUCOcON++9vfPKpiXyUrQOp+z Wwkr4afYR9v9+P5Wx2GqsEa0bWVLTKGTVuqDM5sFU0wY6wfaJh2QP2F2y2VCCXaYxl ifAjLEdeprm+qX5u5+Ta5+/amnoovHdJ1SlAN0r1Qy1tNn3mcSvgcWEOQrVjZ5TRcH +Q3gPLixbnY+ZoOMcWBi89GeJCLiw83N6OPh72E3P+faRrbZoR+SvqHb3XdGd5i6eq 3kObCJCT22plyz6rfqV5cID6Aq0LM0dy3R2NySVbu5T5ZDi+u7ym+XUzrFPV4kGi+H qeB+BA5X14PWw== Received: by jupiter.universe (Postfix, from userid 1000) id ADB8F48011D; Thu, 5 Jan 2023 19:03:42 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner , "Rafael J. Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Finley Xiao , kernel@collabora.com, Sebastian Reichel Subject: [PATCHv3 6/7] thermal: rockchip: Support RK3588 SoC in the thermal driver Date: Thu, 5 Jan 2023 19:03:39 +0100 Message-Id: <20230105180340.29140-7-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105180340.29140-1-sebastian.reichel@collabora.com> References: <20230105180340.29140-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Finley Xiao The RK3588 SoC has seven temperature sensor ADC channels: - Chip Center - CPU Cluster 1 (Dual A76 "Big" Cores) - CPU Cluster 2 (Dual A76 "Big" Cores) - CPU Cluster 0 (Quad A55 "Little" Cores) - Power Domain Center - Graphics Processing Unit - Neural Processing Unit Signed-off-by: Finley Xiao [rebase, squash fixes] Reviewed-by: Heiko Stuebner Signed-off-by: Sebastian Reichel --- drivers/thermal/rockchip_thermal.c | 177 +++++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_= thermal.c index c104c60faafd..2c45558b7e35 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -165,29 +165,49 @@ struct rockchip_thermal_data { #define TSADCV2_AUTO_CON 0x04 #define TSADCV2_INT_EN 0x08 #define TSADCV2_INT_PD 0x0c +#define TSADCV3_AUTO_SRC_CON 0x0c +#define TSADCV3_HT_INT_EN 0x14 +#define TSADCV3_HSHUT_GPIO_INT_EN 0x18 +#define TSADCV3_HSHUT_CRU_INT_EN 0x1c +#define TSADCV3_INT_PD 0x24 +#define TSADCV3_HSHUT_PD 0x28 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) +#define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04) +#define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04) +#define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04) #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 +#define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c +#define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150 #define TSADCV2_AUTO_PERIOD 0x68 #define TSADCV2_AUTO_PERIOD_HT 0x6c +#define TSADCV3_AUTO_PERIOD 0x154 +#define TSADCV3_AUTO_PERIOD_HT 0x158 =20 #define TSADCV2_AUTO_EN BIT(0) +#define TSADCV2_AUTO_EN_MASK BIT(16) #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) +#define TSADCV3_AUTO_SRC_EN(chn) BIT(chn) +#define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + chn) #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) +#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24) =20 #define TSADCV3_AUTO_Q_SEL_EN BIT(1) =20 #define TSADCV2_INT_SRC_EN(chn) BIT(chn) +#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn)) #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) =20 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) +#define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff =20 #define TSADCV2_DATA_MASK 0xfff #define TSADCV3_DATA_MASK 0x3ff +#define TSADCV4_DATA_MASK 0x1ff =20 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 @@ -198,6 +218,8 @@ struct rockchip_thermal_data { =20 #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */ #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ +#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */ +#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ =20 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ @@ -214,6 +236,12 @@ struct rockchip_thermal_data { #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2) #define RK3568_GRF_TSADC_TSEN (0x10001 << 8) =20 +#define RK3588_GRF0_TSADC_CON 0x0100 + +#define RK3588_GRF0_TSADC_TRM (0xff0077 << 0) +#define RK3588_GRF0_TSADC_SHUT_2CRU (0x30003 << 10) +#define RK3588_GRF0_TSADC_SHUT_2GPIO (0x70007 << 12) + #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) #define GRF_TSADC_VCM_EN_L (0x10001 << 7) @@ -508,6 +536,15 @@ static const struct tsadc_table rk3568_code_table[] = =3D { {TSADCV2_DATA_MASK, 125000}, }; =20 +static const struct tsadc_table rk3588_code_table[] =3D { + {0, -40000}, + {215, -40000}, + {285, 25000}, + {350, 85000}, + {395, 125000}, + {TSADCV4_DATA_MASK, 125000}, +}; + static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table, int temp) { @@ -778,6 +815,25 @@ static void rk_tsadcv7_initialize(struct regmap *grf, = void __iomem *regs, } } =20 +static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs, + enum tshut_polarity tshut_polarity) +{ + writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD); + writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME, + regs + TSADCV3_AUTO_PERIOD_HT); + writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_INT_DEBOUNCE); + writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); + if (tshut_polarity =3D=3D TSHUT_HIGH_ACTIVE) + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | + TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); + else + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); +} + static void rk_tsadcv2_irq_ack(void __iomem *regs) { u32 val; @@ -794,6 +850,17 @@ static void rk_tsadcv3_irq_ack(void __iomem *regs) writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); } =20 +static void rk_tsadcv4_irq_ack(void __iomem *regs) +{ + u32 val; + + val =3D readl_relaxed(regs + TSADCV3_INT_PD); + writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD); + val =3D readl_relaxed(regs + TSADCV3_HSHUT_PD); + writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, + regs + TSADCV3_HSHUT_PD); +} + static void rk_tsadcv2_control(void __iomem *regs, bool enable) { u32 val; @@ -829,6 +896,18 @@ static void rk_tsadcv3_control(void __iomem *regs, boo= l enable) writel_relaxed(val, regs + TSADCV2_AUTO_CON); } =20 +static void rk_tsadcv4_control(void __iomem *regs, bool enable) +{ + u32 val; + + if (enable) + val =3D TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK; + else + val =3D TSADCV2_AUTO_EN_MASK; + + writel_relaxed(val, regs + TSADCV2_AUTO_CON); +} + static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int *temp) { @@ -839,6 +918,16 @@ static int rk_tsadcv2_get_temp(const struct chip_tsadc= _table *table, return rk_tsadcv2_code_to_temp(table, val, temp); } =20 +static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table, + int chn, void __iomem *regs, int *temp) +{ + u32 val; + + val =3D readl_relaxed(regs + TSADCV3_DATA(chn)); + + return rk_tsadcv2_code_to_temp(table, val, temp); +} + static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int temp) { @@ -873,6 +962,33 @@ static int rk_tsadcv2_alarm_temp(const struct chip_tsa= dc_table *table, return 0; } =20 +static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table, + int chn, void __iomem *regs, int temp) +{ + u32 alarm_value; + + /* + * In some cases, some sensors didn't need the trip points, the + * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm + * in the end, ignore this case and disable the high temperature + * interrupt. + */ + if (temp =3D=3D INT_MAX) { + writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn), + regs + TSADCV3_HT_INT_EN); + return 0; + } + /* Make sure the value is valid */ + alarm_value =3D rk_tsadcv2_temp_to_code(table, temp); + if (alarm_value =3D=3D table->data_mask) + return -ERANGE; + writel_relaxed(alarm_value & table->data_mask, + regs + TSADCV3_COMP_INT(chn)); + writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn), + regs + TSADCV3_HT_INT_EN); + return 0; +} + static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int temp) { @@ -892,6 +1008,25 @@ static int rk_tsadcv2_tshut_temp(const struct chip_ts= adc_table *table, return 0; } =20 +static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table, + int chn, void __iomem *regs, int temp) +{ + u32 tshut_value; + + /* Make sure the value is valid */ + tshut_value =3D rk_tsadcv2_temp_to_code(table, temp); + if (tshut_value =3D=3D table->data_mask) + return -ERANGE; + + writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn)); + + /* TSHUT will be valid */ + writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn), + regs + TSADCV3_AUTO_SRC_CON); + + return 0; +} + static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, enum tshut_mode mode) { @@ -909,6 +1044,22 @@ static void rk_tsadcv2_tshut_mode(int chn, void __iom= em *regs, writel_relaxed(val, regs + TSADCV2_INT_EN); } =20 +static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs, + enum tshut_mode mode) +{ + u32 val_gpio, val_cru; + + if (mode =3D=3D TSHUT_MODE_GPIO) { + val_gpio =3D TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); + val_cru =3D TSADCV2_INT_SRC_EN_MASK(chn); + } else { + val_cru =3D TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); + val_gpio =3D TSADCV2_INT_SRC_EN_MASK(chn); + } + writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN); + writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); +} + static const struct rockchip_tsadc_chip px30_tsadc_data =3D { /* cpu, gpu */ .chn_offset =3D 0, @@ -1132,6 +1283,28 @@ static const struct rockchip_tsadc_chip rk3568_tsadc= _data =3D { }, }; =20 +static const struct rockchip_tsadc_chip rk3588_tsadc_data =3D { + /* top, big_core0, big_core1, little_core, center, gpu, npu */ + .chn_offset =3D 0, + .chn_num =3D 7, /* seven channels for tsadc */ + .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ + .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ + .tshut_temp =3D 95000, + .initialize =3D rk_tsadcv8_initialize, + .irq_ack =3D rk_tsadcv4_irq_ack, + .control =3D rk_tsadcv4_control, + .get_temp =3D rk_tsadcv4_get_temp, + .set_alarm_temp =3D rk_tsadcv3_alarm_temp, + .set_tshut_temp =3D rk_tsadcv3_tshut_temp, + .set_tshut_mode =3D rk_tsadcv3_tshut_mode, + .table =3D { + .id =3D rk3588_code_table, + .length =3D ARRAY_SIZE(rk3588_code_table), + .data_mask =3D TSADCV4_DATA_MASK, + .mode =3D ADC_INCREMENT, + }, +}; + static const struct of_device_id of_rockchip_thermal_match[] =3D { { .compatible =3D "rockchip,px30-tsadc", .data =3D (void *)&px30_tsadc_data, @@ -1168,6 +1341,10 @@ static const struct of_device_id of_rockchip_thermal= _match[] =3D { .compatible =3D "rockchip,rk3568-tsadc", .data =3D (void *)&rk3568_tsadc_data, }, + { + .compatible =3D "rockchip,rk3588-tsadc", + .data =3D (void *)&rk3588_tsadc_data, + }, { /* end */ }, }; MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); --=20 2.39.0 From nobody Tue Sep 16 04:56:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDF36C3DA7D for ; Thu, 5 Jan 2023 18:04:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235528AbjAESEW (ORCPT ); Thu, 5 Jan 2023 13:04:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235445AbjAESDv (ORCPT ); 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Thu, 5 Jan 2023 19:03:42 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner , "Rafael J. Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com, Krzysztof Kozlowski Subject: [PATCHv3 7/7] dt-bindings: rockchip-thermal: Support the RK3588 SoC compatible Date: Thu, 5 Jan 2023 19:03:40 +0100 Message-Id: <20230105180340.29140-8-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105180340.29140-1-sebastian.reichel@collabora.com> References: <20230105180340.29140-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a new compatible for the thermal sensor device on RK3588 SoCs. Reviewed-by: Heiko Stuebner Acked-by: Krzysztof Kozlowski Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yam= l b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml index f6c1be226aaa..55f8ec0bec01 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -19,6 +19,7 @@ properties: - rockchip,rk3368-tsadc - rockchip,rk3399-tsadc - rockchip,rk3568-tsadc + - rockchip,rk3588-tsadc - rockchip,rv1108-tsadc =20 reg: --=20 2.39.0