From nobody Sat Sep 21 07:31:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9EE9C54EBC for ; Thu, 5 Jan 2023 17:15:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235466AbjAERO4 (ORCPT ); Thu, 5 Jan 2023 12:14:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233734AbjAEROW (ORCPT ); Thu, 5 Jan 2023 12:14:22 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75D6067BD7 for ; Thu, 5 Jan 2023 09:08:42 -0800 (PST) Received: by mail-wr1-x429.google.com with SMTP id t15so27899420wro.9 for ; Thu, 05 Jan 2023 09:08:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BGyNZMSELVhIYsmh8IQ0cClyJQ3/Pu1dOTSavukgh6c=; b=DFV2Bk7pE1z4nPsGE5YQsNh5/MwQhELQBIwLpGoUt5Kr9gGjWSCWaFcpmx/AiWgzTM CeJmBndmStn53lw/APB9JGUuZ75hK168BLWCI/aimccr/+KgtnF2uyggiH/FpeScDRZ9 +Yl4VULKayXF9MQk0OaIC5ksglOZuaQtzTLCqmwMD/1z4GQbtzQL3k7lIkYbHCrOMtow OtLWWmEESfhoGWyamVruOyv2ut8FI+UEPxH2mD3AOfjNKwJHDRXDin5IrcMvaC0GLALj YbliiPCOSz8pGhwtNyXH32N8CUQXHE6sJcSAizkGHLBmITscU38JNk17TMPNYeNMrW1I pQ+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BGyNZMSELVhIYsmh8IQ0cClyJQ3/Pu1dOTSavukgh6c=; b=e/xDxeXAuDeHHZsOuahBNBAn/4z0br2fWFocSFSdR0CuwuciGFVN1AX9obZ4h3IFrz UzFPs1v3gNTLVH0FjDr0h0ZzQzDSxMqflyOPv+jHiwbCDzrH7tg60X95fgk5ryzsk+/A 0XgXl1akLLuuUxx59Sl04YHWWK5wWTmzRu3eZd5m7+xO5qly/WyfknyqZxutwaaJtefM cMr8nYMACRXEShvxl4arNgzdeWC/ruhDSmx4OljvyP0zIPEp4M62BZuJqbgARuQesyhr XB0i/P71bF/O0SmTct623VOC5Nxg8UgYjeklDquBmgRSm8kZebdzA0Fm3bniVY+1TpZ2 tn5w== X-Gm-Message-State: AFqh2krClZN8DtJQB6hLphiaQg/6Mz/uJEyXw4roWSwc+tR9IYAZeu9n FqYUAGqlw+4xWGBWBnzTzwvL9Q== X-Google-Smtp-Source: AMrXdXuowYI8YNiqe+s1dAJFjpbJUx2V8Zot+mmm14+rnSw+zcIM7fBJvdIhDwBvmez939s1n5rILw== X-Received: by 2002:a5d:4e4c:0:b0:2b8:bcd8:1808 with SMTP id r12-20020a5d4e4c000000b002b8bcd81808mr215071wrt.44.1672938467798; Thu, 05 Jan 2023 09:07:47 -0800 (PST) Received: from blmsp.fritz.box ([2001:4091:a245:805c:9cf4:fdb8:bb61:5f4e]) by smtp.gmail.com with ESMTPSA id f14-20020adfe90e000000b002365730eae8sm37164853wrm.55.2023.01.05.09.07.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 09:07:47 -0800 (PST) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH 1/8] dt-bindings: power: Add MT8365 power domains Date: Thu, 5 Jan 2023 18:07:28 +0100 Message-Id: <20230105170735.1637416-2-msp@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105170735.1637416-1-msp@baylibre.com> References: <20230105170735.1637416-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add power domains dt-bindings for MT8365. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: Rob Herring --- Notes: Changes in v4: - Add infracfg_nao as it is used by mt8365 =20 Changes in v3: - Renamed mt8365-power.h to mediatek,mt8365-power.h =20 Changes in v2: - Made include/dt-bindings/power/mt8365-power.h dual-license. .../power/mediatek,power-controller.yaml | 6 ++++++ .../dt-bindings/power/mediatek,mt8365-power.h | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-control= ler.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controlle= r.yaml index 605ec7ab5f63..a496c43cfa16 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -30,6 +30,7 @@ properties: - mediatek,mt8186-power-controller - mediatek,mt8192-power-controller - mediatek,mt8195-power-controller + - mediatek,mt8365-power-controller =20 '#power-domain-cells': const: 1 @@ -86,6 +87,7 @@ $defs: "include/dt-bindings/power/mt8183-power.h" - for MT8183 type= power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type= power domain. "include/dt-bindings/power/mt8195-power.h" - for MT8195 type= power domain. + "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT= 8365 type power domain. maxItems: 1 =20 clocks: @@ -113,6 +115,10 @@ $defs: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the INFRACFG registe= r range. =20 + mediatek,infracfg-nao: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the device containing the INFRACFG-NAO reg= ister range. + mediatek,smi: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the SMI register ran= ge. diff --git a/include/dt-bindings/power/mediatek,mt8365-power.h b/include/dt= -bindings/power/mediatek,mt8365-power.h new file mode 100644 index 000000000000..e6cfd0ec7871 --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt8365-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H +#define _DT_BINDINGS_POWER_MT8365_POWER_H + +#define MT8365_POWER_DOMAIN_MM 0 +#define MT8365_POWER_DOMAIN_CONN 1 +#define MT8365_POWER_DOMAIN_MFG 2 +#define MT8365_POWER_DOMAIN_AUDIO 3 +#define MT8365_POWER_DOMAIN_CAM 4 +#define MT8365_POWER_DOMAIN_DSP 5 +#define MT8365_POWER_DOMAIN_VDEC 6 +#define MT8365_POWER_DOMAIN_VENC 7 +#define MT8365_POWER_DOMAIN_APU 8 + +#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */ --=20 2.39.0 From nobody Sat Sep 21 07:31:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E303C54EBF for ; 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Thu, 05 Jan 2023 09:07:48 -0800 (PST) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Markus Schneider-Pargmann Subject: [PATCH 2/8] soc: mediatek: pm-domains: Split bus_prot_mask Date: Thu, 5 Jan 2023 18:07:29 +0100 Message-Id: <20230105170735.1637416-3-msp@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105170735.1637416-1-msp@baylibre.com> References: <20230105170735.1637416-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" bus_prot_mask is used for all operations, set clear and acknowledge. In preparation of m8365 power domain support split this one mask into two, one mask for set and clear, another one for acknowledge. Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mtk-pm-domains.c | 24 ++++++++++++++---------- drivers/soc/mediatek/mtk-pm-domains.h | 14 ++++++++------ 2 files changed, 22 insertions(+), 16 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 474b272f9b02..4333cd297405 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -122,18 +122,20 @@ static int _scpsys_bus_protect_enable(const struct sc= psys_bus_prot_data *bpd, st int i, ret; =20 for (i =3D 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - u32 val, mask =3D bpd[i].bus_prot_mask; + u32 val; + u32 set_clr_mask =3D bpd[i].bus_prot_set_clr_mask; + u32 sta_mask =3D bpd[i].bus_prot_sta_mask; =20 - if (!mask) + if (!set_clr_mask) break; =20 if (bpd[i].bus_prot_reg_update) - regmap_set_bits(regmap, bpd[i].bus_prot_set, mask); + regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask); else - regmap_write(regmap, bpd[i].bus_prot_set, mask); + regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask); =20 ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, (val & mask) =3D=3D mask, + val, (val & sta_mask) =3D=3D sta_mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; @@ -159,21 +161,23 @@ static int _scpsys_bus_protect_disable(const struct s= cpsys_bus_prot_data *bpd, int i, ret; =20 for (i =3D SPM_MAX_BUS_PROT_DATA - 1; i >=3D 0; i--) { - u32 val, mask =3D bpd[i].bus_prot_mask; + u32 val; + u32 set_clr_mask =3D bpd[i].bus_prot_set_clr_mask; + u32 sta_mask =3D bpd[i].bus_prot_sta_mask; =20 - if (!mask) + if (!set_clr_mask) continue; =20 if (bpd[i].bus_prot_reg_update) - regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask); + regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask); else - regmap_write(regmap, bpd[i].bus_prot_clr, mask); + regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask); =20 if (bpd[i].ignore_clr_ack) continue; =20 ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, !(val & mask), + val, !(val & sta_mask), MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 7d3c0c36316c..8aaed1c939d7 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -41,23 +41,24 @@ =20 #define SPM_MAX_BUS_PROT_DATA 6 =20 -#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ - .bus_prot_mask =3D (_mask), \ +#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _update, _ig= nore) { \ + .bus_prot_set_clr_mask =3D (_set_clr_mask), \ .bus_prot_set =3D _set, \ .bus_prot_clr =3D _clr, \ + .bus_prot_sta_mask =3D (_sta_mask), \ .bus_prot_sta =3D _sta, \ .bus_prot_reg_update =3D _update, \ .ignore_clr_ack =3D _ignore, \ } =20 #define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, false) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, false, false) =20 #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, true) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, false, true) =20 #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, true, false) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, true, false) =20 #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ @@ -66,9 +67,10 @@ INFRA_TOPAXI_PROTECTSTA1) =20 struct scpsys_bus_prot_data { - u32 bus_prot_mask; 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Thu, 05 Jan 2023 09:07:49 -0800 (PST) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Markus Schneider-Pargmann Subject: [PATCH 3/8] soc: mediatek: pm-domains: Create bus protection operation functions Date: Thu, 5 Jan 2023 18:07:30 +0100 Message-Id: <20230105170735.1637416-4-msp@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105170735.1637416-1-msp@baylibre.com> References: <20230105170735.1637416-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Separate the register access used for bus protection enable/disable into their own functions. These will be used later for WAY_EN bits. Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mtk-pm-domains.c | 68 +++++++++++++++------------ 1 file changed, 39 insertions(+), 29 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 4333cd297405..999e1f6c86b0 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -117,26 +117,50 @@ static int scpsys_sram_disable(struct scpsys_domain *= pd) MTK_POLL_TIMEOUT); } =20 +static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap) +{ + u32 val; + u32 sta_mask =3D bpd->bus_prot_sta_mask; + + if (bpd->bus_prot_reg_update) + regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); + else + regmap_write(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); + + if (bpd->ignore_clr_ack) + return 0; + + return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + val, !(val & sta_mask), + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + +static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap) +{ + u32 val; + u32 sta_mask =3D bpd->bus_prot_sta_mask; + + if (bpd->bus_prot_reg_update) + regmap_set_bits(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); + else + regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); + + return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + val, (val & sta_mask) =3D=3D sta_mask, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *b= pd, struct regmap *regmap) { int i, ret; =20 for (i =3D 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - u32 val; - u32 set_clr_mask =3D bpd[i].bus_prot_set_clr_mask; - u32 sta_mask =3D bpd[i].bus_prot_sta_mask; - - if (!set_clr_mask) + if (!bpd[i].bus_prot_set_clr_mask) break; =20 - if (bpd[i].bus_prot_reg_update) - regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask); - else - regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask); - - ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, (val & sta_mask) =3D=3D sta_mask, - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret =3D scpsys_bus_protect_set(&bpd[i], regmap); if (ret) return ret; } @@ -161,24 +185,10 @@ static int _scpsys_bus_protect_disable(const struct s= cpsys_bus_prot_data *bpd, int i, ret; =20 for (i =3D SPM_MAX_BUS_PROT_DATA - 1; i >=3D 0; i--) { - u32 val; - u32 set_clr_mask =3D bpd[i].bus_prot_set_clr_mask; - u32 sta_mask =3D bpd[i].bus_prot_sta_mask; - - if (!set_clr_mask) - continue; - - if (bpd[i].bus_prot_reg_update) - regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask); - else - regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask); - - if (bpd[i].ignore_clr_ack) + if (!bpd[i].bus_prot_set_clr_mask) continue; =20 - ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, !(val & sta_mask), - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret =3D scpsys_bus_protect_clear(&bpd[i], regmap); if (ret) return ret; } --=20 2.39.0 From nobody Sat Sep 21 07:31:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 420C1C5479D for ; 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Thu, 05 Jan 2023 09:07:50 -0800 (PST) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Markus Schneider-Pargmann Subject: [PATCH 4/8] soc: mediatek: pm-domains: Document scpsys_bus_prot_data Date: Thu, 5 Jan 2023 18:07:31 +0100 Message-Id: <20230105170735.1637416-5-msp@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105170735.1637416-1-msp@baylibre.com> References: <20230105170735.1637416-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a short documentation for the fields in struct scpsys_bus_prot_data. Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mtk-pm-domains.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 8aaed1c939d7..da827e91d462 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -66,6 +66,18 @@ INFRA_TOPAXI_PROTECTEN, \ INFRA_TOPAXI_PROTECTSTA1) =20 +/** + * struct scpsys_bus_prot_data - Bus protection setting + * @bus_prot_set_clr_mask: Bitmask used for the set and clear registers. + * @bus_prot_set: infracfg set register. + * @bus_prot_clr: infracfg clear register. + * @bus_prot_sta_mask: Bitmask used for the status register. + * @bus_prot_sta: infracfg status register. + * @bus_prot_reg_update: Only update the register bits given in the mask, = do not + * write the whole register. + * @ignore_clk_ack: Ignore the result in the status register for clear + * operations. + */ struct scpsys_bus_prot_data { u32 bus_prot_set_clr_mask; u32 bus_prot_set; --=20 2.39.0 From nobody Sat Sep 21 07:31:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9300AC63797 for ; Thu, 5 Jan 2023 17:22:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234947AbjAERVs (ORCPT ); Thu, 5 Jan 2023 12:21:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235168AbjAERUx (ORCPT ); Thu, 5 Jan 2023 12:20:53 -0500 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 489F36319E for ; Thu, 5 Jan 2023 09:12:53 -0800 (PST) Received: by mail-wr1-f49.google.com with SMTP id bs20so34663379wrb.3 for ; Thu, 05 Jan 2023 09:12:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+AVf+pfLkaJ1Gl2NWqezqv2bXezRKHHSaj8ghEqd14w=; b=y7jLrTG7p7QjcN2Cna7QAn3CMLp/iGX9hFgyWOvIeyQoOsHM3qakRasdP5KMfs+NZ2 FPGzPh9C37o2fDUts5urh+UMB69Vw/ZtDYJo91usNWWpzFe27e91iTXgrN37D02UUx9t A9JvGt7PQ8GoRaaxdmXkthGFdlZyGOajaTqKTinkqnl+uv1XKe3UHCKFEvvr+4LtZsLL AjXOiLXb2Mb1Xe0l7+XuzUtB3Imrpgn0hRHnNjrVUHZ6R94g8p2yLgyyT+xyPCEPI3RN DYPF1DpAztnyht4GNPZeB9OWUWZVtmH+Mr01s3DiR0khgIxwjyEXhz5WtNBVPTTz3INm YZKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+AVf+pfLkaJ1Gl2NWqezqv2bXezRKHHSaj8ghEqd14w=; b=vYOj8wnfFRsxfSuJ1DQxSDs4d6WdP7Xtr5K/T0m0mYzbbEoAAx8hxPqiI9x/Xsr4Q+ 7o5L60YnrlDB9esaSDloygyvq/ATF7RQUtqdSSfoFW0swtM8wBUBZjE10u4vXtFQ90l4 LPjyR1fGAJD8BdRr/sqjhELiJvWN372xY3QRvv9om0MFc+5to7biWY//VE5NkbYVYc0x ccPj5dxIcjnZ3HXOYSk9S4ZPvhRY2/YEIqq6B1ga+ieQ5nsx5ccU618dJVwC/F+NMUwE y2xPML9K0FAfWXuk9+okO4h/Ts0lhy2Bk3er8JO/wjlYT0SjqVvCqD+p8TdUfZOBPMs6 hzLw== X-Gm-Message-State: AFqh2kqn/TJS81g6MZGhoSHiyVAnm65QN2fR+ruF5ftNz1FeDwr+Rb+9 ufkVexfmerjSD8OW9O3k9kJdwA== X-Google-Smtp-Source: AMrXdXvaEZbEf1VJvkJQZUZ0wp7+NbVXpfFjW83Omw2E04q6K1OndbNKvbHNrGOYQSYHZx9OqH/3Tw== X-Received: by 2002:adf:ea4a:0:b0:27e:8d9b:bc20 with SMTP id j10-20020adfea4a000000b0027e8d9bbc20mr26665705wrn.27.1672938471790; Thu, 05 Jan 2023 09:07:51 -0800 (PST) Received: from blmsp.fritz.box ([2001:4091:a245:805c:9cf4:fdb8:bb61:5f4e]) by smtp.gmail.com with ESMTPSA id f14-20020adfe90e000000b002365730eae8sm37164853wrm.55.2023.01.05.09.07.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 09:07:51 -0800 (PST) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Markus Schneider-Pargmann Subject: [PATCH 5/8] soc: mediatek: pm-domains: Fix caps field documentation Date: Thu, 5 Jan 2023 18:07:32 +0100 Message-Id: <20230105170735.1637416-6-msp@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105170735.1637416-1-msp@baylibre.com> References: <20230105170735.1637416-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This field is not for ACTIVE_WAKEUP exclusively. There are a lot of other flags defined as well. Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mtk-pm-domains.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index da827e91d462..34642a279213 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -95,7 +95,7 @@ struct scpsys_bus_prot_data { * @ctl_offs: The offset for main power control register. * @sram_pdn_bits: The mask for sram power control bits. * @sram_pdn_ack_bits: The mask for sram power control acked bits. - * @caps: The flag for active wake-up action. + * @caps: MTK_SCPD_* capability flags. * @bp_infracfg: bus protection for infracfg subsystem * @bp_smi: bus protection for smi subsystem */ --=20 2.39.0 From nobody Sat Sep 21 07:31:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F3F7C54EF0 for ; Thu, 5 Jan 2023 17:16:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235475AbjAERQB (ORCPT ); Thu, 5 Jan 2023 12:16:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235521AbjAERPC (ORCPT ); Thu, 5 Jan 2023 12:15:02 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08F8F69531 for ; Thu, 5 Jan 2023 09:09:13 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id ay40so28532539wmb.2 for ; Thu, 05 Jan 2023 09:09:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KPJV1qfI65vcb6ofJWhCMHNO2xRqa9GjQ0e1B9CiTNQ=; b=yNsOPbDTM0efU9dE//dgz3rHOrXf/sZWUnEGrQcLupD9McKI9FV03L2Spct4MXfF4S TU8AU8AzjfBeTcB7tDXILCKm7rE+WjqBJRRHF70S2hg6kLrq5B224CgNH004pnKtNOvh ew6qC7fSouMuSq+iVPPF3Ri49sGNgZqzNd/IOE5JOh8gV+GtaIJc5dUqr82tYrNwfI7X W7zBiIgay+TkR62pupN0EEF2sIp+F4GYUnogdRMqpgMGCCTUtyOAKDchHCrh3spQPPKY 5Zy3Mo4lrNThLPbZgiLumzbTI+GdZsyVnjzkT5v6zijPPW+7WqTu7cC8e536cUunBMZA 3bCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KPJV1qfI65vcb6ofJWhCMHNO2xRqa9GjQ0e1B9CiTNQ=; b=vY1UJI2B9U6QSdMBCupE5UpFpq37z/yziQV6TYAbW3Ym2SmMDgMRIVO2IsPo6hDP4h 4T77mcvWWIEn76betsVNVZ5rj5M3vyAnqVnercru7RGhLF7/lmnR53m5caceEcT9dqKX Kckp4ZoF3H3pqY/0KfOGcicvFCDzna8DOt/IPfuOh5g/N4LDrrgUZ07L0NglBoLbHIYj j5INbm8LjDbuOKRFk4JjYTs2n8Qzw60FTL4Y+rVsO/ZvoSjouM2YNWgvfoRtZrI7JUx9 UTISf2W8pZpqPcnVl7cPqpQPnWgWhh2EP9CXie34+2ZXRJYX7V/fHCb+I0hrqKm5qRcp OLTw== X-Gm-Message-State: AFqh2kqM6EQHSNna5+KIIrQXzI24fr/Kg/2a7KDGfzdhrOIb1gZc9bF8 PAM7hJMiLIVvrB0HmGsTVQDsBg== X-Google-Smtp-Source: AMrXdXuIXDpOZkm4ix/uQdGbtjWGymqzEfazAjrzvDtgZc3mURrErZ0nErcrf/OQqJfWoIsPn55TIw== X-Received: by 2002:a05:600c:687:b0:3cf:e7c8:494 with SMTP id a7-20020a05600c068700b003cfe7c80494mr37142812wmn.29.1672938472975; Thu, 05 Jan 2023 09:07:52 -0800 (PST) Received: from blmsp.fritz.box ([2001:4091:a245:805c:9cf4:fdb8:bb61:5f4e]) by smtp.gmail.com with ESMTPSA id f14-20020adfe90e000000b002365730eae8sm37164853wrm.55.2023.01.05.09.07.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 09:07:52 -0800 (PST) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Bailon , Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH 6/8] soc: mediatek: Add support for WAY_EN operations Date: Thu, 5 Jan 2023 18:07:33 +0100 Message-Id: <20230105170735.1637416-7-msp@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105170735.1637416-1-msp@baylibre.com> References: <20230105170735.1637416-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexandre Bailon This updates the power domain to support WAY_EN operations. These operations enable a path between different units of the chip and are labeled as 'way_en' in the register descriptions. This operation is required by the mt8365 for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- Notes: Changes in v4: - Redesigned the patch to be better to understand and have less code duplication =20 Changes in v3: - Separated the way_en functions for clarity - Added some checks for infracfg_nao =20 Changes in v2: - some minor style fixes. - Renamed 'wayen' to 'way_en' to clarify the meaning - Updated commit message drivers/soc/mediatek/mtk-pm-domains.c | 57 ++++++++++++++++++++------- drivers/soc/mediatek/mtk-pm-domains.h | 16 ++++++-- 2 files changed, 54 insertions(+), 19 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 999e1f6c86b0..d53309f050ee 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -43,6 +43,7 @@ struct scpsys_domain { struct clk_bulk_data *clks; int num_subsys_clks; struct clk_bulk_data *subsys_clks; + struct regmap *infracfg_nao; struct regmap *infracfg; struct regmap *smi; struct regulator *supply; @@ -118,10 +119,13 @@ static int scpsys_sram_disable(struct scpsys_domain *= pd) } =20 static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, - struct regmap *regmap) + struct regmap *regmap, + struct regmap *sta_regmap) { u32 val; u32 sta_mask =3D bpd->bus_prot_sta_mask; + /* way_en acknowledges successful clear with the bit being set */ + u32 expected_ack =3D (bpd->way_en ? sta_mask : 0); =20 if (bpd->bus_prot_reg_update) regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); @@ -131,13 +135,14 @@ static int scpsys_bus_protect_clear(const struct scps= ys_bus_prot_data *bpd, if (bpd->ignore_clr_ack) return 0; =20 - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, - val, !(val & sta_mask), + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, + val, (val & sta_mask) =3D=3D expected_ack, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, - struct regmap *regmap) + struct regmap *regmap, + struct regmap *sta_regmap) { u32 val; u32 sta_mask =3D bpd->bus_prot_sta_mask; @@ -147,12 +152,13 @@ static int scpsys_bus_protect_set(const struct scpsys= _bus_prot_data *bpd, else regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); =20 - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, val, (val & sta_mask) =3D=3D sta_mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 -static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *b= pd, struct regmap *regmap) +static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *b= pd, + struct regmap *regmap, struct regmap *infracfg_nao) { int i, ret; =20 @@ -160,9 +166,14 @@ static int _scpsys_bus_protect_enable(const struct scp= sys_bus_prot_data *bpd, st if (!bpd[i].bus_prot_set_clr_mask) break; =20 - ret =3D scpsys_bus_protect_set(&bpd[i], regmap); - if (ret) + if (bpd[i].way_en) + ret =3D scpsys_bus_protect_clear(&bpd[i], regmap, infracfg_nao); + else + ret =3D scpsys_bus_protect_set(&bpd[i], regmap, regmap); + if (ret) { + pr_err("%s %d %d\n", __PRETTY_FUNCTION__, __LINE__, ret); return ret; + } } =20 return 0; @@ -172,15 +183,17 @@ static int scpsys_bus_protect_enable(struct scpsys_do= main *pd) { int ret; =20 - ret =3D _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg); + ret =3D _scpsys_bus_protect_enable(pd->data->bp_infracfg, + pd->infracfg, pd->infracfg_nao); if (ret) return ret; =20 - return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi); + return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi, NULL); } =20 static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *= bpd, - struct regmap *regmap) + struct regmap *regmap, + struct regmap *infracfg_nao) { int i, ret; =20 @@ -188,9 +201,14 @@ static int _scpsys_bus_protect_disable(const struct sc= psys_bus_prot_data *bpd, if (!bpd[i].bus_prot_set_clr_mask) continue; =20 - ret =3D scpsys_bus_protect_clear(&bpd[i], regmap); - if (ret) + if (bpd[i].way_en) + ret =3D scpsys_bus_protect_set(&bpd[i], regmap, infracfg_nao); + else + ret =3D scpsys_bus_protect_clear(&bpd[i], regmap, regmap); + if (ret) { + pr_err("%s %d %d\n", __PRETTY_FUNCTION__, __LINE__, ret); return ret; + } } =20 return 0; @@ -200,11 +218,12 @@ static int scpsys_bus_protect_disable(struct scpsys_d= omain *pd) { int ret; =20 - ret =3D _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi); + ret =3D _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi, NULL); if (ret) return ret; =20 - return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); + return _scpsys_bus_protect_disable(pd->data->bp_infracfg, + pd->infracfg, pd->infracfg_nao); } =20 static int scpsys_regulator_enable(struct regulator *supply) @@ -378,6 +397,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys= *scpsys, struct device_no return ERR_CAST(pd->smi); } =20 + pd->infracfg_nao =3D syscon_regmap_lookup_by_phandle(node, "mediatek,infr= acfg-nao"); + if (IS_ERR(pd->infracfg_nao)) { + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_WAY_EN)) + return ERR_CAST(pd->infracfg_nao); + + pd->infracfg_nao =3D NULL; + } + num_clks =3D of_clk_get_parent_count(node); if (num_clks > 0) { /* Calculate number of subsys_clks */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 34642a279213..1fa634509db1 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -10,6 +10,7 @@ #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ #define MTK_SCPD_ALWAYS_ON BIT(5) +#define MTK_SCPD_HAS_WAY_EN BIT(6) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -41,7 +42,7 @@ =20 #define SPM_MAX_BUS_PROT_DATA 6 =20 -#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _update, _ig= nore) { \ +#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _update, _ig= nore, _way_en) { \ .bus_prot_set_clr_mask =3D (_set_clr_mask), \ .bus_prot_set =3D _set, \ .bus_prot_clr =3D _clr, \ @@ -49,16 +50,20 @@ .bus_prot_sta =3D _sta, \ .bus_prot_reg_update =3D _update, \ .ignore_clr_ack =3D _ignore, \ + .way_en =3D _way_en, \ } =20 #define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, false, false) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, false, false, false) =20 #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, false, true) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, false, true, false) =20 #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, true, false) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, true, false, false) + +#define BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \ + _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, true, false, true) =20 #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ @@ -77,6 +82,8 @@ * write the whole register. * @ignore_clk_ack: Ignore the result in the status register for clear * operations. + * @way_en: Enable a way in the SoC. For this type the status bit to ackno= wledge + * the change is always 1 on successful change. */ struct scpsys_bus_prot_data { u32 bus_prot_set_clr_mask; @@ -86,6 +93,7 @@ struct scpsys_bus_prot_data { u32 bus_prot_sta; bool bus_prot_reg_update; bool ignore_clr_ack; + bool way_en; }; =20 /** --=20 2.39.0 From nobody Sat Sep 21 07:31:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A77B2C54EBC for ; Thu, 5 Jan 2023 17:15:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235014AbjAERP3 (ORCPT ); Thu, 5 Jan 2023 12:15:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234975AbjAERO0 (ORCPT ); Thu, 5 Jan 2023 12:14:26 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 198C467BEC for ; Thu, 5 Jan 2023 09:08:45 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id ay2-20020a05600c1e0200b003d22e3e796dso1854930wmb.0 for ; Thu, 05 Jan 2023 09:08:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sncxYiJ19EBEMYozwgCXbGEKSdQ2+11yxAIRrAVvyso=; b=L8GGi7ni7dl6wFN8IW77qB70367v8PhZ3Sd7+oJtMLY5Ej9cNvDNLQSAsDm09a+xsP wK3c5FXsCw2fAI8nS6woEXI0BA5uhEXQAs1+yNidpxEMs39ztajNLQMH9bjXgBm615vp 3UTrsw/syO8Q2MNa9PtePGoMM7ezHfYurfTCo5Ds8UGYdF/+rmD+F7wd79Y8dZwU7VSn B14ErNIeK6oq02bUfQPt0ZEJNesP1wNbvDsX2THshhyp5+nW2Par/RJXvy52WSR2YMq1 ZFJUeYixlF/HoXntuGwSv4jBB+damvcCP4cq//5M4DNqUB6jD+nSsg5nryz18+5IskYw fWLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sncxYiJ19EBEMYozwgCXbGEKSdQ2+11yxAIRrAVvyso=; b=S53kgJI4ZQN1rqqNK4n/YdV5FlaWc/V9yH3w91msucvsRJ73rohba/7c5NMfkIHysz TqwKjE1bGBU4XBbTasnuCXNszyfozmyYsaV8x6rXeTrHUbpqVPA3nZ/xY76zRQTlpi+s 1Nl4/1szHUtn/LvqtFtGjTqR2soM6rSDCS4tVokJgOTdiwC7tr4VgBxrrsvZC+4yaLvm gUef+R2jr1K3h/h54S6p7D8UD8dx0IWMsu5bfOFVk/3tiTKcnHKpkpjmet+YysVHRQuK YsiRZIMoC5ahngFGD3nRmvkx4KeaQJxXcP+OCRph71EtT1w9TAWtfvbbz8PzUHssM5Er ZdiA== X-Gm-Message-State: AFqh2koxOxe6yqilv9c4aB7KH9FGhKqZCUD1ojzqSVppxLKhYaq8fcID BlrScrXJlsigkg64of5V3GH8hA== X-Google-Smtp-Source: AMrXdXsa25aMnGI1cayPOWzrjuYzyQhetcgmL1o5YukwOgaRADsQ2/BrQNcacZ4JwiA8kuPZNNtW5g== X-Received: by 2002:a1c:770b:0:b0:3cf:a18d:399c with SMTP id t11-20020a1c770b000000b003cfa18d399cmr39048182wmi.1.1672938474085; Thu, 05 Jan 2023 09:07:54 -0800 (PST) Received: from blmsp.fritz.box ([2001:4091:a245:805c:9cf4:fdb8:bb61:5f4e]) by smtp.gmail.com with ESMTPSA id f14-20020adfe90e000000b002365730eae8sm37164853wrm.55.2023.01.05.09.07.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 09:07:53 -0800 (PST) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Bailon , Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH 7/8] soc: mediatek: Add support for MTK_SCPD_STRICT_BUS_PROTECTION cap Date: Thu, 5 Jan 2023 18:07:34 +0100 Message-Id: <20230105170735.1637416-8-msp@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105170735.1637416-1-msp@baylibre.com> References: <20230105170735.1637416-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexandre Bailon This adds support for MTK_SCPD_STRICT_BUS_PROTECTION capability. It is a strict bus protection policy that requires the bus protection to be disabled before accessing the bus. This is required by the mt8365, for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- Notes: Changes in v4: - Change name in title and commit message =20 Changes in v3: - Rename MTK_SCPD_STRICT_BUSP to MTK_SCPD_STRICT_BUS_PROTECTION - Remove extra bool variable reflecting the capability =20 Changes in v2: - Fixup error handling path. drivers/soc/mediatek/mtk-pm-domains.c | 27 +++++++++++++++++++++++---- drivers/soc/mediatek/mtk-pm-domains.h | 1 + 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index d53309f050ee..29a9028dd9b3 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -265,9 +265,17 @@ static int scpsys_power_on(struct generic_pm_domain *g= enpd) regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); =20 - ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks); - if (ret) - goto err_pwr_ack; + /* + * In few Mediatek platforms(e.g. MT6779), the bus protect policy is + * stricter, which leads to bus protect release must be prior to bus + * access. + */ + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) { + ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_pwr_ack; + } =20 ret =3D scpsys_sram_enable(pd); if (ret < 0) @@ -277,12 +285,23 @@ static int scpsys_power_on(struct generic_pm_domain *= genpd) if (ret < 0) goto err_disable_sram; =20 + if (MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) { + ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_enable_bus_protect; + } + return 0; =20 +err_enable_bus_protect: + scpsys_bus_protect_enable(pd); err_disable_sram: scpsys_sram_disable(pd); err_disable_subsys_clks: - clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) + clk_bulk_disable_unprepare(pd->num_subsys_clks, + pd->subsys_clks); err_pwr_ack: clk_bulk_disable_unprepare(pd->num_clks, pd->clks); err_reg: diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 1fa634509db1..e5aa2348a9db 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -11,6 +11,7 @@ /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ #define MTK_SCPD_ALWAYS_ON BIT(5) #define MTK_SCPD_HAS_WAY_EN BIT(6) +#define MTK_SCPD_STRICT_BUS_PROTECTION BIT(7) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 --=20 2.39.0 From nobody Sat Sep 21 07:31:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF073C54EBF for ; Thu, 5 Jan 2023 17:15:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235215AbjAERPh (ORCPT ); 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Thu, 05 Jan 2023 09:07:54 -0800 (PST) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH 8/8] soc: mediatek: pm-domains: Add support for MT8365 Date: Thu, 5 Jan 2023 18:07:35 +0100 Message-Id: <20230105170735.1637416-9-msp@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105170735.1637416-1-msp@baylibre.com> References: <20230105170735.1637416-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add the needed board data to support MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mt8365-pm-domains.h | 147 +++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 5 + 2 files changed, 152 insertions(+) create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h diff --git a/drivers/soc/mediatek/mt8365-pm-domains.h b/drivers/soc/mediate= k/mt8365-pm-domains.h new file mode 100644 index 000000000000..8735e833b15b --- /dev/null +++ b/drivers/soc/mediatek/mt8365-pm-domains.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8365 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt8365[] =3D { + [MT8365_POWER_DOMAIN_MM] =3D { + .name =3D "mm", + .sta_mask =3D PWR_STATUS_DISP, + .ctl_offs =3D 0x30c, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .caps =3D MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_WAY_EN, + .bp_infracfg =3D { + BUS_PROT_WR(BIT(16) | BIT(17), 0x2a8, 0x2ac, 0x258), + BUS_PROT_WR(BIT(1) | BIT(2) | BIT(10) | BIT(11), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WAY_EN(BIT(6), 0x200, BIT(24), 0x0), + BUS_PROT_WAY_EN(BIT(5), 0x234, BIT(14), 0x28), + BUS_PROT_WR(BIT(6), 0x2a0, 0x2a4, 0x228), + }, + }, + [MT8365_POWER_DOMAIN_VENC] =3D { + .name =3D "venc", + .sta_mask =3D PWR_STATUS_VENC, + .ctl_offs =3D 0x0304, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_smi =3D { + BUS_PROT_WR(BIT(1), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_AUDIO] =3D { + .name =3D "audio", + .sta_mask =3D PWR_STATUS_AUDIO, + .ctl_offs =3D 0x0314, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(12, 8), + .sram_pdn_ack_bits =3D GENMASK(17, 13), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(27) | BIT(28), 0x2a8, 0x2ac, 0x258), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8365_POWER_DOMAIN_CONN] =3D { + .name =3D "conn", + .sta_mask =3D PWR_STATUS_CONN, + .ctl_offs =3D 0x032c, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D 0, + .sram_pdn_ack_bits =3D 0, + .bp_infracfg =3D { + BUS_PROT_WR(BIT(13), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(18), 0x2a8, 0x2ac, 0x258), + BUS_PROT_WR(BIT(14), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(21), 0x2a8, 0x2ac, 0x258), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8365_POWER_DOMAIN_MFG] =3D { + .name =3D "mfg", + .sta_mask =3D PWR_STATUS_MFG, + .ctl_offs =3D 0x0338, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(9, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(25), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(21) | BIT(22), 0x2a0, 0x2a4, 0x228), + }, + }, + [MT8365_POWER_DOMAIN_CAM] =3D { + .name =3D "cam", + .sta_mask =3D BIT(25), + .ctl_offs =3D 0x0344, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(9, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(19), 0x2a8, 0x2ac, 0x258), + }, + .bp_smi =3D { + BUS_PROT_WR(BIT(2), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_VDEC] =3D { + .name =3D "vdec", + .sta_mask =3D BIT(31), + .ctl_offs =3D 0x0370, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_smi =3D { + BUS_PROT_WR(BIT(3), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_APU] =3D { + .name =3D "apu", + .sta_mask =3D BIT(16), + .ctl_offs =3D 0x0378, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(14, 8), + .sram_pdn_ack_bits =3D GENMASK(21, 15), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(2) | BIT(20), 0x2a8, 0x2ac, 0x258), + }, + .bp_smi =3D { + BUS_PROT_WR(BIT(4), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_DSP] =3D { + .name =3D "dsp", + .sta_mask =3D BIT(17), + .ctl_offs =3D 0x037C, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(15, 12), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(24) | BIT(30) | BIT(31), 0x2a8, 0x2ac, 0x258), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP, + }, +}; + +static const struct scpsys_soc_data mt8365_scpsys_data =3D { + .domains_data =3D scpsys_domain_data_mt8365, + .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt8365), +}; + +#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 29a9028dd9b3..adb7716df0a8 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -23,6 +23,7 @@ #include "mt8186-pm-domains.h" #include "mt8192-pm-domains.h" #include "mt8195-pm-domains.h" +#include "mt8365-pm-domains.h" =20 #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -647,6 +648,10 @@ static const struct of_device_id scpsys_of_match[] =3D= { .compatible =3D "mediatek,mt8195-power-controller", .data =3D &mt8195_scpsys_data, }, + { + .compatible =3D "mediatek,mt8365-power-controller", + .data =3D &mt8365_scpsys_data, + }, { } }; =20 --=20 2.39.0