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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT023.mail.protection.outlook.com (10.13.177.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5986.14 via Frontend Transport; Thu, 5 Jan 2023 17:02:18 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 5 Jan 2023 11:02:17 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Lazar Lijo , Mario Limonciello , "Lijo Lazar" , "Pan, Xinhui" , David Airlie Subject: [PATCH v7 16/45] drm/amd: Use `amdgpu_ucode_*` helpers for GFX10 Date: Thu, 5 Jan 2023 11:01:02 -0600 Message-ID: <20230105170138.717-17-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105170138.717-1-mario.limonciello@amd.com> References: <20230105170138.717-1-mario.limonciello@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT023:EE_|CY5PR12MB6107:EE_ X-MS-Office365-Filtering-Correlation-Id: 6c035280-34eb-4707-b8ae-08daef3e9aa9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 17:02:18.7702 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c035280-34eb-4707-b8ae-08daef3e9aa9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6107 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unload. Reviewed-by: Alex Deucher Reviewed-by: Lijo Lazar Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 71 ++++++++------------------ 1 file changed, 20 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/a= mdgpu/gfx_v10_0.c index 49d34c7bbf20..140bb18ff768 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -3891,18 +3891,12 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_rin= g *ring, long timeout) =20 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) { - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw =3D NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw =3D NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw =3D NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw =3D NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw =3D NULL; - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw =3D NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); + amdgpu_ucode_release(&adev->gfx.mec2_fw); =20 kfree(adev->gfx.rlc.register_list_format); } @@ -4030,41 +4024,31 @@ static int gfx_v10_0_init_microcode(struct amdgpu_d= evice *adev) } =20 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); - err =3D request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; - err =3D amdgpu_ucode_validate(adev->gfx.pfp_fw); + err =3D amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); =20 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); - err =3D request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; - err =3D amdgpu_ucode_validate(adev->gfx.me_fw); + err =3D amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); =20 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); - err =3D request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); - if (err) - goto out; - err =3D amdgpu_ucode_validate(adev->gfx.ce_fw); + err =3D amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); =20 if (!amdgpu_sriov_vf(adev)) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); - err =3D request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); - if (err) - goto out; + err =3D amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); /* don't check this. There are apparently firmwares in the wild with * incorrect size in the header */ - err =3D amdgpu_ucode_validate(adev->gfx.rlc_fw); + if (err =3D=3D -ENODEV) + goto out; if (err) dev_dbg(adev->dev, "gfx10: amdgpu_ucode_validate() failed \"%s\"\n", @@ -4078,21 +4062,15 @@ static int gfx_v10_0_init_microcode(struct amdgpu_d= evice *adev) } =20 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); - err =3D request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err) - goto out; - err =3D amdgpu_ucode_validate(adev->gfx.mec_fw); + err =3D amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); =20 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks= ); - err =3D request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + err =3D amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); if (!err) { - err =3D amdgpu_ucode_validate(adev->gfx.mec2_fw); - if (err) - goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); } else { @@ -4103,21 +4081,12 @@ static int gfx_v10_0_init_microcode(struct amdgpu_d= evice *adev) gfx_v10_0_check_fw_write_wait(adev); out: if (err) { - dev_err(adev->dev, - "gfx10: Failed to init firmware \"%s\"\n", - fw_name); - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw =3D NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw =3D NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw =3D NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw =3D NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw =3D NULL; - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw =3D NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); + amdgpu_ucode_release(&adev->gfx.mec2_fw); } =20 gfx_v10_0_check_gfxoff_flag(adev); --=20 2.34.1