From nobody Tue Sep 16 08:27:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BFABC54EF0 for ; Thu, 5 Jan 2023 13:07:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234141AbjAENHm (ORCPT ); Thu, 5 Jan 2023 08:07:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229944AbjAENG4 (ORCPT ); Thu, 5 Jan 2023 08:06:56 -0500 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CE945C1D2; Thu, 5 Jan 2023 05:06:54 -0800 (PST) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 305AovPN031661; Thu, 5 Jan 2023 14:06:41 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=4diL3zrahtnSNm7i1x9vEtgyobNwseziaCJOdzFVfzM=; b=qcCNam2zW6fjXOpFlY0Puk/uoCrsHyNzXPcd1A5B0quEt4zu9pYYPtsPshYH3F74V1Lu 5e5wY0vRCRaWKkBsjEYGpqa+iQ9RNGJdb7yOWFCOCtTjANjR+iDZO2v18kMVuHBvK+dz nIkWr1pOOyQNIVCPDtW7sBdIIVMyFh9qhSQ1/64bZlLlDLf42LA0pBjGlV8VTVGaAxlf dHUGBOs/HkNvtHZXObBQuTW5wlK9TgmPar29TeD6hGVkVGdNNM8MlPpDINvQ6ObJcCyV 82eRrnPTNDj0nqNWVM1NU2jdayhH/I/FVZ0+vYP1xH2akXyVrZ6MZtUtM3XbjSpE38ll JQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3mwtasabx8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Jan 2023 14:06:41 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 40B7410002A; Thu, 5 Jan 2023 14:06:41 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 394AA23BDE9; Thu, 5 Jan 2023 14:06:41 +0100 (CET) Received: from localhost (10.201.20.178) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.13; Thu, 5 Jan 2023 14:06:40 +0100 From: Olivier Moysan To: Rob Herring , Krzysztof Kozlowski , Maxime Coquelin , Alexandre Torgue CC: Olivier Moysan , , , , Subject: [PATCH 1/3] ARM: dts: stm32: add timers support on stm32mp131 Date: Thu, 5 Jan 2023 14:06:09 +0100 Message-ID: <20230105130612.330155-2-olivier.moysan@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105130612.330155-1-olivier.moysan@foss.st.com> References: <20230105130612.330155-1-olivier.moysan@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.201.20.178] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-05_04,2023-01-04_02,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add timers support to STM32MP13x SoC family. Signed-off-by: Olivier Moysan --- arch/arm/boot/dts/stm32mp131.dtsi | 557 ++++++++++++++++++++++++++++++ 1 file changed, 557 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp1= 31.dtsi index 2a9b3a5bba83..3e527cc8a33c 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -121,6 +121,221 @@ scmi_shm: scmi-sram@0 { }; }; =20 + timers2: timer@40000000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x40000000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc TIM2_K>; + clock-names =3D "int"; + dmas =3D <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names =3D "ch1", "ch2", "ch3", "ch4", "up"; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@1 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <1>; + status =3D "disabled"; + }; + + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + }; + + timers3: timer@40001000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x40001000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc TIM3_K>; + clock-names =3D "int"; + dmas =3D <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names =3D "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@2 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <2>; + status =3D "disabled"; + }; + + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + }; + + timers4: timer@40002000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x40002000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc TIM4_K>; + clock-names =3D "int"; + dmas =3D <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names =3D "ch1", "ch2", "ch3", "up"; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@3 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <3>; + status =3D "disabled"; + }; + + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + }; + + timers5: timer@40003000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x40003000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc TIM5_K>; + clock-names =3D "int"; + dmas =3D <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names =3D "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@4 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <4>; + status =3D "disabled"; + }; + + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + }; + + timers6: timer@40004000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x40004000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc TIM6_K>; + clock-names =3D "int"; + dmas =3D <&dmamux1 69 0x400 0x1>; + dma-names =3D "up"; + status =3D "disabled"; + + timer@5 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <5>; + status =3D "disabled"; + }; + }; + + timers7: timer@40005000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x40005000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc TIM7_K>; + clock-names =3D "int"; + dmas =3D <&dmamux1 70 0x400 0x1>; + dma-names =3D "up"; + status =3D "disabled"; + + timer@6 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <6>; + status =3D "disabled"; + }; + }; + + lptimer1: timer@40009000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-lptimer"; + reg =3D <0x40009000 0x400>; + interrupts-extended =3D <&exti 47 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc LPTIM1_K>; + clock-names =3D "mux"; + wakeup-source; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + trigger@0 { + compatible =3D "st,stm32-lptimer-trigger"; + reg =3D <0>; + status =3D "disabled"; + }; + + counter { + compatible =3D "st,stm32-lptimer-counter"; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + }; + spi2: spi@4000b000 { compatible =3D "st,stm32h7-spi"; reg =3D <0x4000b000 0x400>; @@ -194,6 +409,88 @@ i2c2: i2c@40013000 { status =3D "disabled"; }; =20 + timers1: timer@44000000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x44000000 0x400>; + interrupts =3D , + , + , + ; + interrupt-names =3D "brk", "up", "trg-com", "cc"; + clocks =3D <&rcc TIM1_K>; + clock-names =3D "int"; + dmas =3D <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names =3D "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@0 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <0>; + status =3D "disabled"; + }; + + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + }; + + timers8: timer@44001000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x44001000 0x400>; + interrupts =3D , + , + , + ; + interrupt-names =3D "brk", "up", "trg-com", "cc"; + clocks =3D <&rcc TIM8_K>; + clock-names =3D "int"; + dmas =3D <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names =3D "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@7 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <7>; + status =3D "disabled"; + }; + + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + }; + spi1: spi@44004000 { compatible =3D "st,stm32h7-spi"; reg =3D <0x44004000 0x400>; @@ -397,6 +694,161 @@ i2c5: i2c@4c006000 { status =3D "disabled"; }; =20 + timers12: timer@4c007000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x4c007000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc TIM12_K>; + clock-names =3D "int"; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@11 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <11>; + status =3D "disabled"; + }; + }; + + timers13: timer@4c008000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x4c008000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc TIM13_K>; + clock-names =3D "int"; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@12 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <12>; + status =3D "disabled"; + }; + }; + + timers14: timer@4c009000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x4c009000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc TIM14_K>; + clock-names =3D "int"; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@13 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <13>; + status =3D "disabled"; + }; + }; + + timers15: timer@4c00a000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x4c00a000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc TIM15_K>; + clock-names =3D "int"; + dmas =3D <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names =3D "ch1", "up", "trig", "com"; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@14 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <14>; + status =3D "disabled"; + }; + }; + + timers16: timer@4c00b000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x4c00b000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc TIM16_K>; + clock-names =3D "int"; + dmas =3D <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names =3D "ch1", "up"; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@15 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <15>; + status =3D "disabled"; + }; + }; + + timers17: timer@4c00c000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-timers"; + reg =3D <0x4c00c000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc TIM17_K>; + clock-names =3D "int"; + dmas =3D <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names =3D "ch1", "up"; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@16 { + compatible =3D "st,stm32h7-timer-trigger"; + reg =3D <16>; + status =3D "disabled"; + }; + }; + rcc: rcc@50000000 { compatible =3D "st,stm32mp13-rcc", "syscon"; reg =3D <0x50000000 0x1000>; @@ -423,6 +875,111 @@ syscfg: syscon@50020000 { clocks =3D <&rcc SYSCFG>; }; =20 + lptimer2: timer@50021000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-lptimer"; + reg =3D <0x50021000 0x400>; + interrupts-extended =3D <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc LPTIM2_K>; + clock-names =3D "mux"; + wakeup-source; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + trigger@1 { + compatible =3D "st,stm32-lptimer-trigger"; + reg =3D <1>; + status =3D "disabled"; + }; + + counter { + compatible =3D "st,stm32-lptimer-counter"; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + }; + + lptimer3: timer@50022000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32-lptimer"; + reg =3D <0x50022000 0x400>; + interrupts-extended =3D <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc LPTIM3_K>; + clock-names =3D "mux"; + wakeup-source; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + trigger@2 { + compatible =3D "st,stm32-lptimer-trigger"; + reg =3D <2>; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + }; + + lptimer4: timer@50023000 { + compatible =3D "st,stm32-lptimer"; + reg =3D <0x50023000 0x400>; + interrupts-extended =3D <&exti 52 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc LPTIM4_K>; + clock-names =3D "mux"; + wakeup-source; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + }; + + lptimer5: timer@50024000 { + compatible =3D "st,stm32-lptimer"; + reg =3D <0x50024000 0x400>; + interrupts-extended =3D <&exti 53 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc LPTIM5_K>; + clock-names =3D "mux"; + wakeup-source; + status =3D "disabled"; + + pwm { + compatible =3D "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + }; + mdma: dma-controller@58000000 { compatible =3D "st,stm32h7-mdma"; reg =3D <0x58000000 0x1000>; --=20 2.25.1 From nobody Tue Sep 16 08:27:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7B75C54EBD for ; Thu, 5 Jan 2023 13:07:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234166AbjAENHn (ORCPT ); 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charset="utf-8" Add timer pins muxing for stm32mp135f-dk board. Signed-off-by: Olivier Moysan --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 60 ++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/s= tm32mp13-pinctrl.dtsi index d377d4c0bef5..b2dce3a29f39 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -54,6 +54,66 @@ pins { }; }; =20 + pwm3_pins_a: pwm3-0 { + pins { + pinmux =3D ; /* TIM3_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + pwm3_sleep_pins_a: pwm3-sleep-0 { + pins { + pinmux =3D ; /* TIM3_CH4 */ + }; + }; + + pwm4_pins_a: pwm4-0 { + pins { + pinmux =3D ; /* TIM4_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux =3D ; /* TIM4_CH2 */ + }; + }; + + pwm8_pins_a: pwm8-0 { + pins { + pinmux =3D ; /* TIM8_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + pwm8_sleep_pins_a: pwm8-sleep-0 { + pins { + pinmux =3D ; /* TIM8_CH3 */ + }; + }; + + pwm14_pins_a: pwm14-0 { + pins { + pinmux =3D ; /* TIM14_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + pwm14_sleep_pins_a: pwm14-sleep-0 { + pins { + pinmux =3D ; /* TIM14_CH1 */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux =3D , /* SDMMC1_D0 */ --=20 2.25.1 From nobody Tue Sep 16 08:27:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE49DC53210 for ; Thu, 5 Jan 2023 13:07:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230149AbjAENHt (ORCPT ); Thu, 5 Jan 2023 08:07:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234199AbjAENHJ (ORCPT ); Thu, 5 Jan 2023 08:07:09 -0500 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 515E84D4A3; Thu, 5 Jan 2023 05:07:06 -0800 (PST) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3059sZMn024285; Thu, 5 Jan 2023 14:06:56 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=7DNtAn5FSvBFs58HAuiuLotVK7ADNTWKpKT1zToNgew=; b=ZJpbS+iahkEvgrcpHDig50rDuYhsS1Y+spb3eO5PF2K2favjTaARGhzIdp4CeNjUQ2Kc I8GD4MhOXfPDFsEtXCF7aeATs6cvmltBrZfP+H9QcaH6vDUX2rRqR+pmRJqC77xoFGzV Hy6Kxm7O7ItUXFGd4aDteYeci5r+f+s7mj1SRK07PC4H+y8cPwsPhlgmWBsJdFsymOnX FcQgtctb5P6IAuQ+gsQfwLWj0H0Tih7+ZVTJCScOd2NyDHXw/O/TxNnL3mPw09MU+iw5 YQG25eWJyk8JI29MlpTE2DWBBDMwN/7JNx35cHKHu7+k90Kzu1+LU0fKxPVu9QP8J5s9 ww== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3mwuw299ar-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Jan 2023 14:06:56 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B007010002A; Thu, 5 Jan 2023 14:06:55 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A9ABB23BDEB; Thu, 5 Jan 2023 14:06:55 +0100 (CET) Received: from localhost (10.201.20.178) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.13; Thu, 5 Jan 2023 14:06:55 +0100 From: Olivier Moysan To: Rob Herring , Krzysztof Kozlowski , Maxime Coquelin , Alexandre Torgue CC: Olivier Moysan , , , , Subject: [PATCH 3/3] ARM: dts: stm32: add timers support on stm32mp135f-dk Date: Thu, 5 Jan 2023 14:06:11 +0100 Message-ID: <20230105130612.330155-4-olivier.moysan@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105130612.330155-1-olivier.moysan@foss.st.com> References: <20230105130612.330155-1-olivier.moysan@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.201.20.178] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-05_04,2023-01-04_02,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Configure timers support on stm32mp135f-dk. The timers TIM3, TIM4, TIM8 & TIM14 which can be used on expansion GPIO connector are disabled by default. Signed-off-by: Olivier Moysan --- arch/arm/boot/dts/stm32mp135f-dk.dts | 58 ++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32= mp135f-dk.dts index 9ff5a3eaf55b..338b4f633ee3 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -208,6 +208,64 @@ &spi5 { status =3D "disabled"; }; =20 +&timers3 { + /delete-property/dmas; + /delete-property/dma-names; + status =3D "disabled"; + pwm { + pinctrl-0 =3D <&pwm3_pins_a>; + pinctrl-1 =3D <&pwm3_sleep_pins_a>; + pinctrl-names =3D "default", "sleep"; + status =3D "okay"; + }; + timer@2 { + status =3D "okay"; + }; +}; + +&timers4 { + /delete-property/dmas; + /delete-property/dma-names; + status =3D "disabled"; + pwm { + pinctrl-0 =3D <&pwm4_pins_a>; + pinctrl-1 =3D <&pwm4_sleep_pins_a>; + pinctrl-names =3D "default", "sleep"; + status =3D "okay"; + }; + timer@3 { + status =3D "okay"; + }; +}; + +&timers8 { + /delete-property/dmas; + /delete-property/dma-names; + status =3D "disabled"; + pwm { + pinctrl-0 =3D <&pwm8_pins_a>; + pinctrl-1 =3D <&pwm8_sleep_pins_a>; + pinctrl-names =3D "default", "sleep"; + status =3D "okay"; + }; + timer@7 { + status =3D "okay"; + }; +}; + +&timers14 { + status =3D "disabled"; + pwm { + pinctrl-0 =3D <&pwm14_pins_a>; + pinctrl-1 =3D <&pwm14_sleep_pins_a>; + pinctrl-names =3D "default", "sleep"; + status =3D "okay"; + }; + timer@13 { + status =3D "okay"; + }; +}; + &uart4 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart4_pins_a>; --=20 2.25.1